306 lines
7.3 KiB
Plaintext
306 lines
7.3 KiB
Plaintext
package izapple2
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import (
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"fmt"
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"github.com/ivanizag/izapple2/component"
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"github.com/ivanizag/izapple2/storage"
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)
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// TODO: fast mode
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/*
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See:
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"Understanding the Apple II, chapter 9"
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Beneath Apple ProDOS, Appendix
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Phases: http://yesterbits.com/media/pubs/AppleOrchard/articles/disk-ii-part-1-1983-apr.pdf
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IMW Floppy Disk I/O Controller info: (https://www.brutaldeluxe.fr/documentation/iwm/apple2_IWM_INFO_19840510.pdf)
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Woz https://applesaucefdc.com/woz/reference2/
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Schematic: https://mirrors.apple2.org.za/ftp.apple.asimov.net/documentation/hardware/schematics/APPLE_DiskII_SCH.pdf
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*/
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// CardDisk2Sequencer is a DiskII interface card
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type CardDisk2Sequencer struct {
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cardBase
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p6ROM []uint8
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latch component.SN74LS259 // 8-bit latch
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register component.SN74LS323 // 8-bit shift/storage register
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flipFlop component.SN74LS174 // hex flip-flop
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motorDelay uint8 // NE556 timer, used to delay motor off
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drive [2]cardDisk2SequencerDrive
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lastPulse bool
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lastPulseCycles uint8 // There is a new pulse every 4ms, that's 8 cycles of 2Mhz
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lastCycle uint64 // 2 Mhz cycles
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}
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const disk2MotorOffDelay = uint8(20) // 2 Mhz cycles, TODO: how long?
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const disk2PulseCcyles = uint8(8) // 8 cycles = 4ms * 2Mhz
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// NewCardDisk2Sequencer creates a new CardDisk2Sequencer
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func NewCardDisk2Sequencer() *CardDisk2Sequencer {
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var c CardDisk2Sequencer
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c.name = "Disk II"
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c.loadRomFromResource("<internal>/DISK2.rom")
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data, _, err := storage.LoadResource("<internal>/DISK2P6raw.rom")
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if err != nil {
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// The resource should be internal and never fail
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panic(err)
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}
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c.p6ROM = data
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return &c
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}
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func (c *CardDisk2Sequencer) dumpState() {
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fmt.Printf("Q5 %v, Q4 %v, delay %v\n", c.latch.Q(5), c.latch.Q(4), c.motorDelay)
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}
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// GetInfo returns card info
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func (c *CardDisk2Sequencer) GetInfo() map[string]string {
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info := make(map[string]string)
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info["rom"] = "16 sector"
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// TODO: add drives info
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return info
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}
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func (c *CardDisk2Sequencer) reset() {
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// UtA2e 9-12, all switches forced to off
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c.latch.Reset()
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}
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func (c *CardDisk2Sequencer) assign(a *Apple2, slot int) {
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c.addCardSoftSwitches(func(_ *ioC0Page, address uint8, data uint8, write bool) uint8 {
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/*
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Slot card pins to SN74LS259 mapping:
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slot_address[3,2,1] => latch_address[2,1,0]
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slot_address[0] => latch_data
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slot_dev_selct => latch_write_enable // It will be true
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*/
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c.latch.Write(address>>1, (address&1) != 0, true)
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// Advance the Disk2 state machine since the last call to softswitches
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c.catchUp(data)
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//c.dumpState()
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/*
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Slot card pins to SN74LS259 mapping:
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slot_address[0] => latch_oe2_n
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*/
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register_output_enable_neg := (address & 1) != 0
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if !register_output_enable_neg {
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reg := c.register.Output()
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return component.ReversePins(reg)
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} else {
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return 33
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}
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}, "DISK2SEQ")
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c.cardBase.assign(a, slot)
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}
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func (c *CardDisk2Sequencer) catchUp(data uint8) {
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currentCycle := c.a.cpu.GetCycles() << 1 // Disk2 cycles are x2 cpu cycle
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motorOn := c.step(data, true)
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if motorOn && c.lastCycle == 0 {
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// The motor was off, now on. We start the count. We do at least a couple 2 Mhz cycles
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c.lastCycle = currentCycle - 2
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}
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c.lastCycle++
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for motorOn && c.lastCycle <= currentCycle {
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motorOn = c.step(data, false)
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c.lastCycle++
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}
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if !motorOn {
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c.lastCycle = 0 // No tracking done
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}
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}
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func (c *CardDisk2Sequencer) step(data uint8, firstStep bool) bool {
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/*
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Q4 and Q6 set on the sofswitches is stored on the
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latch.
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*/
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q5 := c.latch.Q(5) // Drive selection
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q4 := c.latch.Q(4) // Motor on (before delay)
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/*
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Motor On comes from the latched q4 via the 556 to
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provide a delay. The delay is reset while q4 is on.
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*/
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if q4 {
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c.motorDelay = disk2MotorOffDelay
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}
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motorOn := c.motorDelay > 0
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/*
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The pins for the cable drives ENBL1 and ENBL2 are
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connected to q5 and motor using half of the 74LS132
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NAND to combine them.
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*/
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c.drive[0].enable(!q5 && motorOn)
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c.drive[1].enable(q5 && motorOn)
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/*
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Motor on AND the 2 Mhz clock (Q3 pin 37 of the slot)
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are connected to the clok pulse of the shift register
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if off, the sequences does not advance. The and uses
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another quarter of the 74LS132 NAND.
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*/
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if !motorOn {
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c.flipFlop.Reset()
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return false
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}
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c.motorDelay--
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/*
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The register is not connected to the data bus directly.
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The pin correspondence is:
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/*
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Head movements. We assume it's instantaneous on Q0-Q3 change. We
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will place it on the first step.
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Q0 to Q3 are connected directly to the drives.
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*/
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if firstStep {
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q0 := c.latch.Q(0)
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q1 := c.latch.Q(1)
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q2 := c.latch.Q(3)
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q3 := c.latch.Q(3)
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c.drive[0].moveHead(q0, q1, q2, q3)
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c.drive[1].moveHead(q0, q1, q2, q3)
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}
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/*
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The reading from the drive is converted to a pulse detecting
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changes using Q3 and Q4 of the flip flop, combines with
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the last quarter of the 74LS132 NAND.
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The woz format provides the pulse directly and we wont emulate
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this detection.
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*/
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pulse := false
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c.lastPulseCycles++
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if c.lastPulseCycles == disk2PulseCcyles {
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pulse = c.drive[0].readPulse() ||
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c.drive[1].readPulse()
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c.lastPulseCycles = 0
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}
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/* The write protected signal comes directly from the any of the
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drives being enabled (motor on) and write protected.
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*/
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wProt := (c.drive[0].enabled && c.drive[0].writeProtected) ||
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(c.drive[1].enabled && c.drive[1].writeProtected)
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/*
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The next instruction for the sequencer is retrieved from
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the ROM P6 using the address:
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A0, A5, A6, A7 <= sequence from 74LS174
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A1 =< MSB of register (pin Q7)
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A2 <= Q6 from 9334
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A3 <= Q7 from 9334
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A4 <= pulse transition
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*/
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romAddress := component.PinsToByte([8]bool{
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c.flipFlop.Q(5), // seq1
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c.register.Q7(),
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c.latch.Q(6),
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c.latch.Q(7),
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pulse,
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c.flipFlop.Q(2), // seq0
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c.flipFlop.Q(1), // seq2
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c.flipFlop.Q(0), //seq3
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})
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sequence := component.PinsToByte([8]bool{
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c.flipFlop.Q(0),
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c.flipFlop.Q(1),
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c.flipFlop.Q(5),
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c.flipFlop.Q(2),
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})
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fmt.Printf("For Q6(%v) Q7(%v) H(%v) P(%v) Seq(%x) => ",
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c.latch.Q(6), c.latch.Q(6), c.register.Q7(), pulse, sequence,
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)
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romDataByte := c.p6ROM[romAddress]
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romData := component.ByteToPins(romDataByte)
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inst := component.PinsToByte([8]bool{
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romData[0],
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romData[1],
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romData[2],
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romData[3],
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})
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next := component.PinsToByte([8]bool{
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romData[7],
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romData[6],
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romData[5],
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romData[4],
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})
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fmt.Printf("cmd(%x) seq(%x)\n", inst, next)
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/*
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The next sequence is feed back to the flip-flops.
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Notes: Q3 and Q4 are not used as we are not emulating
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the pulse detection. MotorOn here is always true, the
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code for motorOn false is above.
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*/
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c.flipFlop.Update(
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romData[7],
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romData[6],
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romData[4],
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false,
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false,
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romData[5],
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motorOn,
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)
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/*
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sequenceNew := component.PinsToByte([8]bool{
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c.flipFlop.Q(2),
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c.flipFlop.Q(5),
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c.flipFlop.Q(1),
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c.flipFlop.Q(0),
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})
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*/
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/*
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The pins for the register shifter update are:
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SR(CLR) <- ROM D3
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S1 <- ROM D0
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S0 <- ROM D1
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DS0(SR) <- WPROT pin of the selected drive
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DS7(SL) <- ROM D2
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IO[7.0] <-> D[0-7] slot data bus (the order is reversed)
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*/
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c.register.Update(
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component.ReversePins(data),
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romData[1], // S0
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romData[0], // S1
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romData[3], // SR_N
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wProt, // DS0
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romData[2], // DS1
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)
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/*
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fmt.Printf("Seq %x. pulse %v, P6ROM[%02x]=%02x -> %x-%x, reg %02x\n",
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sequence, pulse, romAddress, romDataByte,
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sequenceNew, command,
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component.ReversePins(c.register.Output()))
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*/
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return true
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}
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