527 lines
19 KiB
Go
527 lines
19 KiB
Go
package main
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import "fmt"
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type state struct {
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registers registers
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memory memory
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}
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func step(s *state) {
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}
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const modeNone = -1
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const modeImmediate = 0
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const modeZeroPage = 1
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const modeZeroPageX = 3
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const modeZeroPageY = 6
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const modeAbsolute = 2
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const modeAbsoluteX = 4
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const modeAbsoluteY = 5
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const modeIndexedIndirectX = 7
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const modeIndirectIndexedY = 8
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const modeAccumulator = 9
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const modeRegisterX = 10
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const modeRegisterY = 11
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const modeIndirect = 12
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// https://www.masswerk.at/6502/6502_instruction_set.html
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// http://www.emulator101.com/reference/6502-reference.html
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// https://www.csh.rit.edu/~moffitt/docs/6502.html#FLAGS
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// https://ia800509.us.archive.org/18/items/Programming_the_6502/Programming_the_6502.pdf
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func getWordInLine(line []uint8) uint16 {
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return uint16(line[1]) + 0x100*uint16(line[2])
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}
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func resolveWithAddressMode(s *state, line []uint8, addressMode int) (value uint8, address uint16, setValue func(uint8)) {
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hasAddress := true
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register := regNone
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switch addressMode {
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case modeAccumulator:
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value = s.registers.getA()
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hasAddress = false
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register = regA
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case modeRegisterX:
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value = s.registers.getX()
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hasAddress = false
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register = regX
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case modeRegisterY:
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value = s.registers.getY()
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hasAddress = false
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register = regY
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case modeImmediate:
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value = line[1]
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hasAddress = false
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case modeZeroPage:
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address = uint16(line[1])
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case modeZeroPageX:
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address = uint16(line[1] + s.registers.getX())
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case modeZeroPageY:
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address = uint16(line[1] + s.registers.getY())
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case modeAbsolute:
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address = getWordInLine(line)
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case modeAbsoluteX:
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address = getWordInLine(line) + uint16(s.registers.getX())
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case modeAbsoluteY:
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address = getWordInLine(line) + uint16(s.registers.getY())
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case modeIndexedIndirectX:
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addressAddress := uint8(line[1] + s.registers.getX())
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address = s.memory.getZeroPageWord(addressAddress)
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case modeIndirect:
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addressAddress := getWordInLine(line)
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address = s.memory.getWord(addressAddress)
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case modeIndirectIndexedY:
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address = s.memory.getZeroPageWord(line[1]) +
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uint16(s.registers.getY())
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}
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if hasAddress {
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value = s.memory[address]
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}
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setValue = func(value uint8) {
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if hasAddress {
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s.memory[address] = value
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} else if register != regNone {
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s.registers.setRegister(register, value)
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} else {
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// Todo: assert impossible
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}
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}
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return
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}
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type opcode struct {
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name string
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bytes int8
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cycles int
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action opFunc
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}
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type opFunc func(s *state, line []uint8, opcode opcode)
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func buildOpTransfer(regSrc int, regDst int) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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value := s.registers.getRegister(regSrc)
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s.registers.setRegister(regDst, value)
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if regDst != regSP {
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s.registers.updateFlagZN(value)
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}
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}
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}
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func buildOpIncDec(addressMode int, inc bool) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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value, _, setValue := resolveWithAddressMode(s, line, addressMode)
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if inc {
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value++
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} else {
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value--
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}
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s.registers.updateFlagZN(value)
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setValue(value)
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}
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}
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func buildShift(addressMode int, isLeft bool, isRotate bool) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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value, _, setValue := resolveWithAddressMode(s, line, addressMode)
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oldCarry := s.registers.getFlagBit(flagC)
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var carry bool
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if isLeft {
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carry = (value & 0x80) != 0
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value <<= 1
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if isRotate {
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value += oldCarry
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}
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} else {
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carry = (value & 0x01) != 0
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value >>= 1
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if isRotate {
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value += oldCarry << 7
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}
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}
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s.registers.updateFlag(flagC, carry)
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s.registers.updateFlagZN(value)
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setValue(value)
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}
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}
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func buildOpLoad(addressMode int, regDst int) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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value, _, _ := resolveWithAddressMode(s, line, addressMode)
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s.registers.setRegister(regDst, value)
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s.registers.updateFlagZN(value)
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}
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}
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func buildOpStore(addressMode int, regSrc int) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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_, _, setValue := resolveWithAddressMode(s, line, addressMode)
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value := s.registers.getRegister(regSrc)
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setValue(value)
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}
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}
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func buildOpUpdateFlag(flag uint8, value bool) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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s.registers.updateFlag(flag, value)
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}
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}
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func buildOpBranch(flag uint8, value bool) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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if s.registers.getFlag(flag) == value {
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// This assumes that PC is already pointing to the next instruction
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pc := s.registers.getPC()
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pc += uint16(int8(line[1]))
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s.registers.setPC(pc)
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}
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}
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}
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func buildOpBit(addressMode int) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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value, _, _ := resolveWithAddressMode(s, line, addressMode)
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acc := s.registers.getA()
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s.registers.updateFlag(flagZ, value&acc == 0)
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s.registers.updateFlag(flagN, value&(1<<7) != 0)
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s.registers.updateFlag(flagV, value&(1<<6) != 0)
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}
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}
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func buildOpCompare(addressMode int, reg int) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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value, _, _ := resolveWithAddressMode(s, line, addressMode)
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reference := s.registers.getRegister(reg)
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s.registers.updateFlagZN(reference - value)
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s.registers.updateFlag(flagC, reference >= value)
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}
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}
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func operationAnd(a uint8, b uint8) uint8 { return a & b }
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func operationOr(a uint8, b uint8) uint8 { return a | b }
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func operationXor(a uint8, b uint8) uint8 { return a ^ b }
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func buildOpLogic(addressMode int, operation func(uint8, uint8) uint8) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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value, _, _ := resolveWithAddressMode(s, line, addressMode)
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result := operation(value, s.registers.getA())
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s.registers.setA(result)
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s.registers.updateFlagZN(result)
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}
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}
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func buildOpAdd(addressMode int) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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value, _, _ := resolveWithAddressMode(s, line, addressMode)
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if s.registers.getFlag(flagD) {
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// TODO BCD. See http://www.6502.org/tutorials/decimal_mode.html
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} else {
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total := uint16(s.registers.getA()) +
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uint16(value) +
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uint16(s.registers.getFlagBit(flagC))
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truncated := uint8(total)
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s.registers.setA(truncated)
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s.registers.updateFlagZN(truncated)
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s.registers.updateFlag(flagC, total > 0xFF)
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// TODO: missing overflow flag
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}
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}
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}
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func buildOpSub(addressMode int) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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value, _, _ := resolveWithAddressMode(s, line, addressMode)
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if s.registers.getFlag(flagD) {
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// TODO BCD
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} else {
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total := 0x100 + uint16(s.registers.getA()) -
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uint16(value) -
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uint16(s.registers.getFlagBit(flagC))
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truncated := uint8(total)
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s.registers.setA(truncated)
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s.registers.updateFlagZN(truncated)
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s.registers.updateFlag(flagC, total <= 0xFF)
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// TODO: missing overflow flag
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}
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}
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}
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const stackAddress uint16 = 0x0100
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func pushByte(s *state, value uint8) {
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adresss := stackAddress + uint16(s.registers.getSP())
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s.memory[adresss] = value
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s.registers.setSP(s.registers.getSP() - 1)
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}
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func pullByte(s *state) uint8 {
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s.registers.setSP(s.registers.getSP() + 1)
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adresss := stackAddress + uint16(s.registers.getSP())
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return s.memory[adresss]
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}
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func pushWord(s *state, value uint16) {
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pushByte(s, uint8(value>>8))
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pushByte(s, uint8(value))
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}
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func pullWord(s *state) uint16 {
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return uint16(pullByte(s)) +
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(uint16(pullByte(s)) << 8)
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}
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func opPLA(s *state, line []uint8, opcode opcode) {
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value := pullByte(s)
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s.registers.setA(value)
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s.registers.updateFlagZN(value)
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}
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func opPLP(s *state, line []uint8, opcode opcode) {
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value := pullByte(s)
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s.registers.setP(value)
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}
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func opPHA(s *state, line []uint8, opcode opcode) {
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pushByte(s, s.registers.getA())
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}
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func opPHP(s *state, line []uint8, opcode opcode) {
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pushByte(s, s.registers.getP()|(flagB+flag5))
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}
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func buildOpJump(addressMode int) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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_, address, _ := resolveWithAddressMode(s, line, addressMode)
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s.registers.setPC(address)
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}
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}
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func opNOP(s *state, line []uint8, opcode opcode) {}
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func opJSR(s *state, line []uint8, opcode opcode) {
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pushWord(s, s.registers.getPC())
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s.registers.setPC(getWordInLine(line))
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}
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func opRTI(s *state, line []uint8, opcode opcode) {
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s.registers.setP(pullByte(s))
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s.registers.setPC(pullWord(s))
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}
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func opRTS(s *state, line []uint8, opcode opcode) {
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s.registers.setPC(pullWord(s) + 1) // TODO: Do we really need to add 1?
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}
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func opBRK(s *state, line []uint8, opcode opcode) {
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s.registers.setFlag(flagI)
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pushWord(s, s.registers.getPC()+1) // TODO: De we have to add 1 or 2?
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pushByte(s, s.registers.getP()|(flagB+flag5))
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s.registers.setPC(s.memory.getWord(0xFFFE))
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}
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var opcodes = [256]opcode{
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0x00: opcode{"BRK", 1, 7, opBRK},
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0x4C: opcode{"JMP", 3, 3, buildOpJump(modeAbsolute)},
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0x6C: opcode{"JMP", 3, 3, buildOpJump(modeIndirect)},
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0x20: opcode{"JSR", 3, 6, opJSR},
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0x40: opcode{"RTI", 1, 6, opRTI},
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0x60: opcode{"RTS", 1, 6, opRTS},
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0x48: opcode{"PHA", 1, 3, opPHA},
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0x08: opcode{"PHP", 1, 3, opPHP},
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0x68: opcode{"PLA", 1, 4, opPLA},
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0x28: opcode{"PLP", 1, 4, opPLP},
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0x09: opcode{"ORA", 2, 2, buildOpLogic(modeImmediate, operationOr)},
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0x05: opcode{"ORA", 2, 3, buildOpLogic(modeZeroPage, operationOr)},
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0x15: opcode{"ORA", 2, 4, buildOpLogic(modeZeroPageX, operationOr)},
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0x0D: opcode{"ORA", 3, 4, buildOpLogic(modeAbsolute, operationOr)},
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0x1D: opcode{"ORA", 3, 4, buildOpLogic(modeAbsoluteX, operationOr)}, // Extra cycles
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0x19: opcode{"ORA", 3, 4, buildOpLogic(modeAbsoluteY, operationOr)}, // Extra cycles
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0x01: opcode{"ORA", 2, 6, buildOpLogic(modeIndexedIndirectX, operationOr)},
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0x11: opcode{"ORA", 2, 5, buildOpLogic(modeIndirectIndexedY, operationOr)}, // Extra cycles
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0x29: opcode{"AND", 2, 2, buildOpLogic(modeImmediate, operationAnd)},
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0x25: opcode{"AND", 2, 3, buildOpLogic(modeZeroPage, operationAnd)},
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0x35: opcode{"AND", 2, 4, buildOpLogic(modeZeroPageX, operationAnd)},
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0x2D: opcode{"AND", 3, 4, buildOpLogic(modeAbsolute, operationAnd)},
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0x3D: opcode{"AND", 3, 4, buildOpLogic(modeAbsoluteX, operationAnd)}, // Extra cycles
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0x39: opcode{"AND", 3, 4, buildOpLogic(modeAbsoluteY, operationAnd)}, // Extra cycles
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0x21: opcode{"AND", 2, 6, buildOpLogic(modeIndexedIndirectX, operationAnd)},
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0x31: opcode{"AND", 2, 5, buildOpLogic(modeIndirectIndexedY, operationAnd)}, // Extra cycles
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0x49: opcode{"EOR", 2, 2, buildOpLogic(modeImmediate, operationXor)},
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0x45: opcode{"EOR", 2, 3, buildOpLogic(modeZeroPage, operationXor)},
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0x55: opcode{"EOR", 2, 4, buildOpLogic(modeZeroPageX, operationXor)},
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0x4D: opcode{"EOR", 3, 4, buildOpLogic(modeAbsolute, operationXor)},
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0x5D: opcode{"EOR", 3, 4, buildOpLogic(modeAbsoluteX, operationXor)}, // Extra cycles
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0x59: opcode{"EOR", 3, 4, buildOpLogic(modeAbsoluteY, operationXor)}, // Extra cycles
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0x41: opcode{"EOR", 2, 6, buildOpLogic(modeIndexedIndirectX, operationXor)},
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0x51: opcode{"EOR", 2, 5, buildOpLogic(modeIndirectIndexedY, operationXor)}, // Extra cycles
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0x69: opcode{"ADC", 2, 2, buildOpAdd(modeImmediate)},
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0x65: opcode{"ADC", 2, 3, buildOpAdd(modeZeroPage)},
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0x75: opcode{"ADC", 2, 4, buildOpAdd(modeZeroPageX)},
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0x6D: opcode{"ADC", 3, 4, buildOpAdd(modeAbsolute)},
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0x7D: opcode{"ADC", 3, 4, buildOpAdd(modeAbsoluteX)}, // Extra cycles
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0x79: opcode{"ADC", 3, 4, buildOpAdd(modeAbsoluteY)}, // Extra cycles
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0x61: opcode{"ADC", 2, 6, buildOpAdd(modeIndexedIndirectX)},
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0x71: opcode{"ADC", 2, 5, buildOpAdd(modeIndirectIndexedY)}, // Extra cycles
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0xE9: opcode{"SBC", 2, 2, buildOpSub(modeImmediate)},
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0xE5: opcode{"SBC", 2, 3, buildOpSub(modeZeroPage)},
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0xF5: opcode{"SBC", 2, 4, buildOpSub(modeZeroPageX)},
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0xED: opcode{"SBC", 3, 4, buildOpSub(modeAbsolute)},
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0xFD: opcode{"SBC", 3, 4, buildOpSub(modeAbsoluteX)}, // Extra cycles
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0xF9: opcode{"SBC", 3, 4, buildOpSub(modeAbsoluteY)}, // Extra cycles
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0xE1: opcode{"SBC", 2, 6, buildOpSub(modeIndexedIndirectX)},
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0xF1: opcode{"SBC", 2, 5, buildOpSub(modeIndirectIndexedY)}, // Extra cycles
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0x24: opcode{"BIT", 2, 3, buildOpBit(modeZeroPage)},
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0x2C: opcode{"BIT", 2, 3, buildOpBit(modeAbsolute)},
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0xC9: opcode{"CMP", 2, 2, buildOpCompare(modeImmediate, regA)},
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0xC5: opcode{"CMP", 2, 3, buildOpCompare(modeZeroPage, regA)},
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0xD5: opcode{"CMP", 2, 4, buildOpCompare(modeZeroPageX, regA)},
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0xCD: opcode{"CMP", 3, 4, buildOpCompare(modeAbsolute, regA)},
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0xDD: opcode{"CMP", 3, 4, buildOpCompare(modeAbsoluteX, regA)}, // Extra cycles
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0xD9: opcode{"CMP", 3, 4, buildOpCompare(modeAbsoluteY, regA)}, // Extra cycles
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0xC1: opcode{"CMP", 2, 6, buildOpCompare(modeIndexedIndirectX, regA)},
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0xD1: opcode{"CMP", 2, 5, buildOpCompare(modeIndirectIndexedY, regA)}, // Extra cycles
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0xE0: opcode{"CPX", 2, 2, buildOpCompare(modeImmediate, regX)},
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0xE4: opcode{"CPX", 2, 3, buildOpCompare(modeZeroPage, regX)},
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0xEC: opcode{"CPX", 3, 4, buildOpCompare(modeAbsolute, regX)},
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0xC0: opcode{"CPY", 2, 2, buildOpCompare(modeImmediate, regY)},
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0xC4: opcode{"CPY", 2, 3, buildOpCompare(modeZeroPage, regY)},
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0xCC: opcode{"CPY", 3, 4, buildOpCompare(modeAbsolute, regY)},
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0x2A: opcode{"ROL", 1, 2, buildShift(modeAccumulator, true, true)},
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0x26: opcode{"ROL", 2, 5, buildShift(modeZeroPage, true, true)},
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0x36: opcode{"ROL", 2, 6, buildShift(modeZeroPageX, true, true)},
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0x2E: opcode{"ROL", 3, 6, buildShift(modeAbsolute, true, true)},
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0x3E: opcode{"ROL", 3, 7, buildShift(modeAbsoluteX, true, true)},
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0x6A: opcode{"ROR", 1, 2, buildShift(modeAccumulator, false, true)},
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0x66: opcode{"ROR", 2, 5, buildShift(modeZeroPage, false, true)},
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0x76: opcode{"ROR", 2, 6, buildShift(modeZeroPageX, false, true)},
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0x6E: opcode{"ROR", 3, 6, buildShift(modeAbsolute, false, true)},
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0x7E: opcode{"ROR", 3, 7, buildShift(modeAbsoluteX, false, true)},
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0x0A: opcode{"ASL", 1, 2, buildShift(modeAccumulator, true, false)},
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0x06: opcode{"ASL", 2, 5, buildShift(modeZeroPage, true, false)},
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0x16: opcode{"ASL", 2, 6, buildShift(modeZeroPageX, true, false)},
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0x0E: opcode{"ASL", 3, 6, buildShift(modeAbsolute, true, false)},
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0x1E: opcode{"ASL", 3, 7, buildShift(modeAbsoluteX, true, false)},
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0x4A: opcode{"LSR", 1, 2, buildShift(modeAccumulator, false, false)},
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0x46: opcode{"LSR", 2, 5, buildShift(modeZeroPage, false, false)},
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0x56: opcode{"LSR", 2, 6, buildShift(modeZeroPageX, false, false)},
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0x4E: opcode{"LSR", 3, 6, buildShift(modeAbsolute, false, false)},
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0x5E: opcode{"LSR", 3, 7, buildShift(modeAbsoluteX, false, false)},
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|
|
|
0x38: opcode{"SEC", 1, 2, buildOpUpdateFlag(flagC, true)},
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0xF8: opcode{"SED", 1, 2, buildOpUpdateFlag(flagD, true)},
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0x78: opcode{"SEI", 1, 2, buildOpUpdateFlag(flagI, true)},
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|
|
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0x18: opcode{"CLC", 1, 2, buildOpUpdateFlag(flagC, false)},
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|
0xD8: opcode{"CLD", 1, 2, buildOpUpdateFlag(flagD, false)},
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|
0x58: opcode{"CLI", 1, 2, buildOpUpdateFlag(flagI, false)},
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|
0xB8: opcode{"CLV", 1, 2, buildOpUpdateFlag(flagV, false)},
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|
|
|
0xE6: opcode{"INC", 2, 5, buildOpIncDec(modeZeroPage, true)},
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|
0xF6: opcode{"INC", 2, 6, buildOpIncDec(modeZeroPageX, true)},
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|
0xEE: opcode{"INC", 3, 6, buildOpIncDec(modeAbsolute, true)},
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|
0xFE: opcode{"INC", 3, 7, buildOpIncDec(modeAbsoluteX, true)},
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|
|
|
0xC6: opcode{"DEC", 2, 5, buildOpIncDec(modeZeroPage, false)},
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|
0xD6: opcode{"DEC", 2, 6, buildOpIncDec(modeZeroPageX, false)},
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|
0xCE: opcode{"DEC", 3, 6, buildOpIncDec(modeAbsolute, false)},
|
|
0xDE: opcode{"DEC", 3, 7, buildOpIncDec(modeAbsoluteX, false)},
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|
|
|
0xE8: opcode{"INX", 1, 2, buildOpIncDec(modeRegisterX, true)},
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|
0xC8: opcode{"INY", 1, 2, buildOpIncDec(modeRegisterY, true)},
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|
0xCA: opcode{"DEX", 1, 2, buildOpIncDec(modeRegisterX, false)},
|
|
0x88: opcode{"DEY", 1, 2, buildOpIncDec(modeRegisterY, false)},
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|
|
|
0xAA: opcode{"TAX", 1, 2, buildOpTransfer(regA, regX)},
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|
0xA8: opcode{"TAY", 1, 2, buildOpTransfer(regA, regY)},
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|
0x8A: opcode{"TXA", 1, 2, buildOpTransfer(regX, regA)},
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|
0x98: opcode{"TYA", 1, 2, buildOpTransfer(regY, regA)},
|
|
0x9A: opcode{"TXS", 1, 2, buildOpTransfer(regX, regSP)},
|
|
0xBA: opcode{"TSX", 1, 2, buildOpTransfer(regSP, regX)},
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|
|
|
0xA9: opcode{"LDA", 2, 2, buildOpLoad(modeImmediate, regA)},
|
|
0xA5: opcode{"LDA", 2, 3, buildOpLoad(modeZeroPage, regA)},
|
|
0xB5: opcode{"LDA", 2, 4, buildOpLoad(modeZeroPageX, regA)},
|
|
0xAD: opcode{"LDA", 3, 4, buildOpLoad(modeAbsolute, regA)},
|
|
0xBD: opcode{"LDA", 3, 4, buildOpLoad(modeAbsoluteX, regA)}, // Extra cycles
|
|
0xB9: opcode{"LDA", 3, 4, buildOpLoad(modeAbsoluteY, regA)}, // Extra cycles
|
|
0xA1: opcode{"LDA", 2, 6, buildOpLoad(modeIndexedIndirectX, regA)},
|
|
0xB1: opcode{"LDA", 2, 5, buildOpLoad(modeIndirectIndexedY, regA)}, // Extra cycles
|
|
|
|
0xA2: opcode{"LDX", 2, 2, buildOpLoad(modeImmediate, regX)},
|
|
0xA6: opcode{"LDX", 2, 3, buildOpLoad(modeZeroPage, regX)},
|
|
0xB6: opcode{"LDX", 2, 4, buildOpLoad(modeZeroPageY, regX)},
|
|
0xAE: opcode{"LDX", 3, 4, buildOpLoad(modeAbsolute, regX)},
|
|
0xBE: opcode{"LDX", 3, 4, buildOpLoad(modeAbsoluteY, regX)}, // Extra cycles
|
|
|
|
0xA0: opcode{"LDY", 2, 2, buildOpLoad(modeImmediate, regY)},
|
|
0xA4: opcode{"LDY", 2, 3, buildOpLoad(modeZeroPage, regY)},
|
|
0xB4: opcode{"LDY", 2, 4, buildOpLoad(modeZeroPageX, regY)},
|
|
0xAC: opcode{"LDY", 3, 4, buildOpLoad(modeAbsolute, regY)},
|
|
0xBC: opcode{"LDY", 3, 4, buildOpLoad(modeAbsoluteX, regY)}, // Extra cycles
|
|
|
|
0x85: opcode{"STA", 2, 3, buildOpStore(modeZeroPage, regA)},
|
|
0x95: opcode{"STA", 2, 4, buildOpStore(modeZeroPageX, regA)},
|
|
0x8D: opcode{"STA", 3, 4, buildOpStore(modeAbsolute, regA)},
|
|
0x9D: opcode{"STA", 3, 5, buildOpStore(modeAbsoluteX, regA)},
|
|
0x99: opcode{"STA", 3, 5, buildOpStore(modeAbsoluteY, regA)},
|
|
0x81: opcode{"STA", 2, 6, buildOpStore(modeIndexedIndirectX, regA)},
|
|
0x91: opcode{"STA", 2, 6, buildOpStore(modeIndirectIndexedY, regA)},
|
|
|
|
0x86: opcode{"STX", 2, 3, buildOpStore(modeZeroPage, regX)},
|
|
0x96: opcode{"STX", 2, 4, buildOpStore(modeZeroPageY, regX)},
|
|
0x8E: opcode{"STX", 3, 4, buildOpStore(modeAbsolute, regX)},
|
|
|
|
0x84: opcode{"STY", 2, 3, buildOpStore(modeZeroPage, regY)},
|
|
0x94: opcode{"STY", 2, 4, buildOpStore(modeZeroPageX, regY)},
|
|
0x8C: opcode{"STY", 3, 4, buildOpStore(modeAbsolute, regY)},
|
|
|
|
0x90: opcode{"BCC", 2, 2, buildOpBranch(flagC, false)}, // Extra cycles
|
|
0xB0: opcode{"BCS", 2, 2, buildOpBranch(flagC, true)}, // Extra cycles
|
|
0xD0: opcode{"BNE", 2, 2, buildOpBranch(flagZ, false)}, // Extra cycles
|
|
0xF0: opcode{"BEQ", 2, 2, buildOpBranch(flagZ, true)}, // Extra cycles
|
|
0x10: opcode{"BPL", 2, 2, buildOpBranch(flagN, false)}, // Extra cycles
|
|
0x30: opcode{"BMI", 2, 2, buildOpBranch(flagN, true)}, // Extra cycles
|
|
0x50: opcode{"BVC", 2, 2, buildOpBranch(flagV, false)}, // Extra cycles
|
|
0x70: opcode{"BVS", 2, 2, buildOpBranch(flagV, true)}, // Extra cycles
|
|
|
|
0xEA: opcode{"NOP", 1, 2, opNOP},
|
|
}
|
|
|
|
func executeLine(s *state, line []uint8) {
|
|
opcode := opcodes[line[0]]
|
|
opcode.action(s, line, opcode)
|
|
}
|
|
|
|
func executeInstruction(s *state) {
|
|
pc := s.registers.getPC()
|
|
opcode := opcodes[s.memory[pc]]
|
|
fmt.Printf("%#04x %s: ", pc, opcode.name)
|
|
pcNext := pc + uint16(opcode.bytes)
|
|
s.registers.setPC(pcNext)
|
|
line := s.memory[pc:pcNext]
|
|
opcode.action(s, line, opcode)
|
|
fmt.Printf("%v, %v\n", s.registers, line)
|
|
}
|