mirror of
https://github.com/ivanizag/izapple2.git
synced 2024-10-31 20:09:02 +00:00
269 lines
6.0 KiB
Go
269 lines
6.0 KiB
Go
package apple2
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import (
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"encoding/binary"
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"fmt"
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"io"
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)
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/*
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https://applesaucefdc.com/woz/reference2/
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Good explanation of the softswitches and the phases:
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http://yesterbits.com/media/pubs/AppleOrchard/articles/disk-ii-part-1-1983-apr.pdf
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"IMW Floppy Disk I/O Controller info" (https://www.brutaldeluxe.fr/documentation/iwm/apple2_IWM_INFO_19840510.pdf)
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"Understanfing the Apple II, chapter 9"
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35 tracks, 16 sectors, 256 bytes
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NIB: 35 tracks 6656 bytes, 232960 bytes
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*/
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const maxHalfTrack = 68
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type cardDisk2 struct {
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cardBase
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selected int // q5, Only 0 and 1 supported
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drive [2]cardDisk2Drive
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dataLatch uint8
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q6 bool
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q7 bool
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}
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type cardDisk2Drive struct {
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diskette *diskette16sector
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currentPhase uint8
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power bool // q4
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halfTrack int
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position int
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}
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const (
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diskBitCycle = 4 // There is a dataLatch bit transferred every 4 cycles
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diskLatchReadCycles = 7 // Loaded data is available for a little more than 7ns
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diskWriteByteCycle = 32 // Load data to write every 32 cycles
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diskWriteSelfSyncCycle = 40 // Save $FF every 40 cycles. Self sync is 10 bits: 1111 1111 00
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diskMotorStartMs = 150 // Time with the disk spinning to get full speed
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)
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func (c *cardDisk2) assign(a *Apple2, slot int) {
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// Q1, Q2, Q3 and Q4 phase control soft switches,
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for i := uint8(0); i < 4; i++ {
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phase := i
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c.addCardSoftSwitchR(phase<<1, func(_ *ioC0Page) uint8 {
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return c.dataLatch // All even addresses return the last dataLatch
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}, fmt.Sprintf("PHASE%vOFF", phase))
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c.addCardSoftSwitchR((phase<<1)+1, func(_ *ioC0Page) uint8 {
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// Move the head up or down depending on the previous phase.
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drive := &c.drive[c.selected]
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delta := (phase - drive.currentPhase + 4) % 4
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switch delta {
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case 1: // Up
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drive.halfTrack++
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case 2: // Illegal, let's say up
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drive.halfTrack++
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case 3: // Down
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drive.halfTrack--
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case 0: // No chamge
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}
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// Don't go over the limits
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if drive.halfTrack > maxHalfTrack {
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drive.halfTrack = maxHalfTrack
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} else if drive.halfTrack < 0 {
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drive.halfTrack = 0
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}
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drive.currentPhase = phase
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//fmt.Printf("DISKII: Current halftrack is %v\n", drive.halfTrack)
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return 0
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}, fmt.Sprintf("PHASE%vOFF", phase))
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}
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// Q4, power switch
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c.addCardSoftSwitchR(0x8, func(_ *ioC0Page) uint8 {
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if c.drive[c.selected].power {
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c.drive[c.selected].power = false
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c.a.releaseFastMode()
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}
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return c.dataLatch
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}, "Q4DRIVEOFF")
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c.addCardSoftSwitchR(0x9, func(_ *ioC0Page) uint8 {
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if !c.drive[c.selected].power {
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c.drive[c.selected].power = true
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c.a.requestFastMode()
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}
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return 0
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}, "")
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// Q5, drive selecion
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c.addCardSoftSwitchR(0xA, func(_ *ioC0Page) uint8 {
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c.selected = 0
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return c.dataLatch
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}, "Q5SELECT1")
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c.addCardSoftSwitchR(0xB, func(_ *ioC0Page) uint8 {
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c.selected = 1
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return 0
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}, "Q5SELECT2")
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// Q6, Q7
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for i := uint8(0xC); i <= 0xF; i++ {
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iCopy := i
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c.addCardSoftSwitchR(iCopy, func(_ *ioC0Page) uint8 {
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return c.softSwitchQ6Q7(iCopy, 0)
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}, "Q6Q7")
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c.addCardSoftSwitchW(iCopy, func(_ *ioC0Page, value uint8) {
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c.softSwitchQ6Q7(iCopy, value)
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}, "Q6Q7")
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}
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c.cardBase.assign(a, slot)
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}
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func (c *cardDisk2) softSwitchQ6Q7(index uint8, in uint8) uint8 {
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switch index {
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case 0xC: // Q6L
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c.q6 = false
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case 0xD: // Q6H
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c.q6 = true
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case 0xE: // Q/L
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c.q7 = false
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case 0xF: // Q7H
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c.q7 = true
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}
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c.processQ6Q7(in)
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if index&1 == 0 {
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// All even addresses return the last dataLatch
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return c.dataLatch
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}
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return 0
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}
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func (c *cardDisk2) processQ6Q7(in uint8) {
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d := &c.drive[c.selected]
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if d.diskette == nil {
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return
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}
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if !c.q6 {
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if !c.q7 { // Q6L-Q7L: Read
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track := d.halfTrack / 2
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c.dataLatch, d.position = d.diskette.read(track, d.position)
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} else { // Q6L-Q7H: Write the dataLatch value to disk. Shift data out
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track := d.halfTrack / 2
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d.position = d.diskette.write(track, d.position, c.dataLatch)
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}
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} else {
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if !c.q7 { // Q6H-Q7L: Sense write protect / prewrite state
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// Bit 7 of the control status register means write protected
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c.dataLatch = 0 // Never write protected
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} else { // Q6H-Q7H: Load data into the controller
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c.dataLatch = in
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}
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}
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}
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func (d *cardDisk2Drive) insertDiskette(dt *diskette16sector) {
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d.diskette = dt
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}
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func (c *cardDisk2) save(w io.Writer) error {
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err := binary.Write(w, binary.BigEndian, c.selected)
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if err != nil {
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return err
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}
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err = binary.Write(w, binary.BigEndian, c.dataLatch)
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if err != nil {
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return err
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}
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err = binary.Write(w, binary.BigEndian, c.q6)
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if err != nil {
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return err
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}
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err = binary.Write(w, binary.BigEndian, c.q7)
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if err != nil {
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return err
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}
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err = c.drive[0].save(w)
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if err != nil {
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return err
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}
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err = c.drive[1].save(w)
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if err != nil {
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return err
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}
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return c.cardBase.save(w)
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}
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func (c *cardDisk2) load(r io.Reader) error {
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err := binary.Read(r, binary.BigEndian, &c.selected)
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if err != nil {
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return err
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}
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err = binary.Read(r, binary.BigEndian, &c.dataLatch)
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if err != nil {
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return err
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}
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err = binary.Read(r, binary.BigEndian, &c.q6)
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if err != nil {
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return err
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}
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err = binary.Read(r, binary.BigEndian, &c.q7)
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if err != nil {
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return err
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}
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err = c.drive[0].load(r)
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if err != nil {
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return err
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}
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err = c.drive[1].load(r)
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if err != nil {
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return err
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}
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return c.cardBase.load(r)
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}
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func (d *cardDisk2Drive) save(w io.Writer) error {
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err := binary.Write(w, binary.BigEndian, d.currentPhase)
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if err != nil {
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return err
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}
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err = binary.Write(w, binary.BigEndian, d.power)
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if err != nil {
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return err
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}
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err = binary.Write(w, binary.BigEndian, d.halfTrack)
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if err != nil {
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return err
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}
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err = binary.Write(w, binary.BigEndian, d.position)
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if err != nil {
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return err
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}
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return nil
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}
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func (d *cardDisk2Drive) load(r io.Reader) error {
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err := binary.Read(r, binary.BigEndian, &d.currentPhase)
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if err != nil {
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return err
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}
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err = binary.Read(r, binary.BigEndian, &d.power)
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if err != nil {
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return err
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}
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err = binary.Read(r, binary.BigEndian, &d.halfTrack)
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if err != nil {
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return err
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}
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err = binary.Read(r, binary.BigEndian, &d.position)
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if err != nil {
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return err
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}
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return nil
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}
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