174 lines
7.1 KiB
Go
174 lines
7.1 KiB
Go
package core6502
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/*
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For the diffrences with NMOS6502 see:
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http://6502.org/tutorials/65c02opcodes.html
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http://wilsonminesco.com/NMOS-CMOSdif/
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http://www.obelisk.me.uk/65C02/reference.html
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http://www.obelisk.me.uk/65C02/addressing.html
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http://anyplatform.net/media/guides/cpus/65xx%20Processor%20Data.txt
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*/
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// NewCMOS65c02 returns an initialized 65c02
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func NewCMOS65c02(m Memory) *State {
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var s State
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s.mem = m
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var opcodes [256]opcode
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for i := 0; i < 256; i++ {
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opcodes[i] = opcodesNMOS6502[i]
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if opcodes65c02Delta[i].cycles != 0 {
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opcodes[i] = opcodes65c02Delta[i]
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}
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}
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add65c02NOPs(&opcodes)
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s.opcodes = &opcodes
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return &s
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}
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func add65c02NOPs(opcodes *[256]opcode) {
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nop11 := opcode{"NOP", 1, 1, modeImplicit, opNOP}
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nop22 := opcode{"NOP", 2, 2, modeImmediate, opNOP}
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nop23 := opcode{"NOP", 2, 3, modeImmediate, opNOP}
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nop24 := opcode{"NOP", 2, 4, modeImmediate, opNOP}
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nop34 := opcode{"NOP", 3, 4, modeAbsolute, opNOP}
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opcodes[0x02] = nop22
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opcodes[0x22] = nop22
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opcodes[0x42] = nop22
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opcodes[0x62] = nop22
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opcodes[0x82] = nop22
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opcodes[0xc2] = nop22
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opcodes[0xe2] = nop22
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opcodes[0x44] = nop23
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opcodes[0x54] = nop24
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opcodes[0xD4] = nop24
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opcodes[0xF4] = nop24
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opcodes[0x5c] = nop34
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opcodes[0xdc] = nop34
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opcodes[0xfc] = nop34
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for i := 0; i < 0x100; i = i + 0x10 {
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opcodes[i+0x03] = nop11
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// RMB and SMB; opcodes[i+0x07] = nop11
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opcodes[i+0x0b] = nop11
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// BBR and BBS: opcodes[i+0x0f] = nop11
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}
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/* Changes for Rockwell65c02
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nop12 := opcode{"NOP", 1, 2, modeImplicit, opNOP}
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opcodes[0xcb] = nop12
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opcodes[0xdb] = nop24
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*/
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// Detection of 65c816
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opcodes[0xbf].name = "XCE"
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}
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var opcodes65c02Delta = [256]opcode{
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// Functional difference
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0x00: {"BRK", 1, 7, modeImplicit, opBRKAlt},
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0x24: {"BIT", 2, 3, modeZeroPage, opBIT},
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0x6C: {"JMP", 3, 6, modeIndirect65c02Fix, opJMP},
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// Fixed BCD arithmetic flags
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0x69: {"ADC", 2, 2, modeImmediate, opADCAlt},
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0x65: {"ADC", 2, 3, modeZeroPage, opADCAlt},
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0x75: {"ADC", 2, 4, modeZeroPageX, opADCAlt},
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0x6D: {"ADC", 3, 4, modeAbsolute, opADCAlt},
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0x7D: {"ADC", 3, 4, modeAbsoluteX, opADCAlt}, // Extra cycles
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0x79: {"ADC", 3, 4, modeAbsoluteY, opADCAlt}, // Extra cycles
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0x61: {"ADC", 2, 6, modeIndexedIndirectX, opADCAlt},
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0x71: {"ADC", 2, 5, modeIndirectIndexedY, opADCAlt}, // Extra cycles
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0xE9: {"SBC", 2, 2, modeImmediate, opSBCAlt},
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0xE5: {"SBC", 2, 3, modeZeroPage, opSBCAlt},
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0xF5: {"SBC", 2, 4, modeZeroPageX, opSBCAlt},
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0xED: {"SBC", 3, 4, modeAbsolute, opSBCAlt},
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0xFD: {"SBC", 3, 4, modeAbsoluteX, opSBCAlt}, // Extra cycles
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0xF9: {"SBC", 3, 4, modeAbsoluteY, opSBCAlt}, // Extra cycles
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0xE1: {"SBC", 2, 6, modeIndexedIndirectX, opSBCAlt},
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0xF1: {"SBC", 2, 5, modeIndirectIndexedY, opSBCAlt}, // Extra cycles
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// Different cycle count
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0x1e: {"ASL", 3, 6, modeAbsoluteX65c02, buildOpShift(true, false)},
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0x3e: {"ROL", 3, 6, modeAbsoluteX65c02, buildOpShift(true, true)},
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0x5e: {"LSR", 3, 6, modeAbsoluteX65c02, buildOpShift(false, false)},
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0x7e: {"ROR", 3, 6, modeAbsoluteX65c02, buildOpShift(false, true)},
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// New indirect zero page addresssing mode
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0x12: {"ORA", 2, 5, modeIndirectZeroPage, buildOpLogic(operationOr)},
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0x32: {"AND", 2, 5, modeIndirectZeroPage, buildOpLogic(operationAnd)},
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0x52: {"EOR", 2, 5, modeIndirectZeroPage, buildOpLogic(operationXor)},
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0x72: {"ADC", 2, 5, modeIndirectZeroPage, opADCAlt},
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0x92: {"STA", 2, 5, modeIndirectZeroPage, buildOpStore(regA)},
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0xb2: {"LDA", 2, 5, modeIndirectZeroPage, buildOpLoad(regA)},
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0xd2: {"CMP", 2, 5, modeIndirectZeroPage, buildOpCompare(regA)},
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0xf2: {"SBC", 2, 5, modeIndirectZeroPage, opSBCAlt},
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// New addressing options
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0x89: {"BIT", 2, 2, modeImmediate, opBIT},
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0x34: {"BIT", 2, 4, modeZeroPageX, opBIT},
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0x3c: {"BIT", 3, 4, modeAbsoluteX, opBIT}, // Extra cycles
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0x1a: {"INC", 1, 2, modeAccumulator, buildOpIncDec(true)},
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0x3a: {"DEC", 1, 2, modeAccumulator, buildOpIncDec(false)},
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0x7c: {"JMP", 3, 6, modeAbsoluteIndexedIndirectX, opJMP},
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// Additional instructions: BRA, PHX, PHY, PLX, PLY, STZ, TRB, TSB
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0xda: {"PHX", 1, 3, modeImplicit, buildOpPush(regX)},
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0x5a: {"PHY", 1, 3, modeImplicit, buildOpPush(regY)},
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0xfa: {"PLX", 1, 4, modeImplicit, buildOpPull(regX)},
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0x7a: {"PLY", 1, 4, modeImplicit, buildOpPull(regY)},
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0x80: {"BRA", 2, 3, modeRelative, opJMP}, // Extra cycles
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0x64: {"STZ", 2, 3, modeZeroPage, opSTZ},
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0x74: {"STZ", 2, 4, modeZeroPageX, opSTZ},
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0x9c: {"STZ", 3, 4, modeAbsolute, opSTZ},
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0x9e: {"STZ", 3, 5, modeAbsoluteX, opSTZ},
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0x14: {"TRB", 2, 5, modeZeroPage, opTRB},
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0x1c: {"TRB", 3, 6, modeAbsolute, opTRB},
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0x04: {"TSB", 2, 5, modeZeroPage, opTSB},
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0x0c: {"TSB", 3, 6, modeAbsolute, opTSB},
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// Additional in Rockwell 65c02 and WDC 65c02?
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// They have a double addressing mode: zeropage and relative.
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0x0f: {"BBR0", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(0, false)}, // Extra cycles
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0x1f: {"BBR1", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(1, false)}, // Extra cycles
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0x2f: {"BBR2", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(2, false)}, // Extra cycles
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0x3f: {"BBR3", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(3, false)}, // Extra cycles
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0x4f: {"BBR4", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(4, false)}, // Extra cycles
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0x5f: {"BBR5", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(5, false)}, // Extra cycles
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0x6f: {"BBR6", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(6, false)}, // Extra cycles
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0x7f: {"BBR7", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(7, false)}, // Extra cycles
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0x8f: {"BBS0", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(0, true)}, // Extra cycles
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0x9f: {"BBS1", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(1, true)}, // Extra cycles
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0xaf: {"BBS2", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(2, true)}, // Extra cycles
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0xbf: {"BBS3", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(3, true)}, // Extra cycles
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0xcf: {"BBS4", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(4, true)}, // Extra cycles
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0xdf: {"BBS5", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(5, true)}, // Extra cycles
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0xef: {"BBS6", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(6, true)}, // Extra cycles
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0xff: {"BBS7", 3, 6, modeZeroPageAndRelative, buildOpBranchOnBit(7, true)}, // Extra cycles
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0x07: {"RMB0", 2, 5, modeZeroPage, buildOpSetBit(0, false)},
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0x17: {"RMB1", 2, 5, modeZeroPage, buildOpSetBit(1, false)},
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0x27: {"RMB2", 2, 5, modeZeroPage, buildOpSetBit(2, false)},
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0x37: {"RMB3", 2, 5, modeZeroPage, buildOpSetBit(3, false)},
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0x47: {"RMB4", 2, 5, modeZeroPage, buildOpSetBit(4, false)},
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0x57: {"RMB5", 2, 5, modeZeroPage, buildOpSetBit(5, false)},
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0x67: {"RMB6", 2, 5, modeZeroPage, buildOpSetBit(6, false)},
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0x77: {"RMB7", 2, 5, modeZeroPage, buildOpSetBit(7, false)},
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0x87: {"SMB0", 2, 5, modeZeroPage, buildOpSetBit(0, true)},
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0x97: {"SMB1", 2, 5, modeZeroPage, buildOpSetBit(1, true)},
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0xa7: {"SMB2", 2, 5, modeZeroPage, buildOpSetBit(2, true)},
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0xb7: {"SMB3", 2, 5, modeZeroPage, buildOpSetBit(3, true)},
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0xc7: {"SMB4", 2, 5, modeZeroPage, buildOpSetBit(4, true)},
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0xd7: {"SMB5", 2, 5, modeZeroPage, buildOpSetBit(5, true)},
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0xe7: {"SMB6", 2, 5, modeZeroPage, buildOpSetBit(6, true)},
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0xf7: {"SMB7", 2, 5, modeZeroPage, buildOpSetBit(7, true)},
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// Maybe additional Rockwell: STP, WAI
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}
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