592 lines
20 KiB
Go
592 lines
20 KiB
Go
package core6502
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import "fmt"
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// State represents the state of the simulated device
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type State struct {
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Reg Registers
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Mem Memory
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}
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const (
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modeImplicit = iota + 1
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modeImplicitX
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modeImplicitY
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modeAccumulator
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modeImmediate
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modeZeroPage
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modeZeroPageX
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modeZeroPageY
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modeRelative
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modeAbsolute
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modeAbsoluteX
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modeAbsoluteY
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modeIndirect
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modeIndexedIndirectX
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modeIndirectIndexedY
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)
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// https://www.masswerk.at/6502/6502_instruction_set.html
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// http://www.emulator101.com/reference/6502-reference.html
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// https://www.csh.rit.edu/~moffitt/docs/6502.html#FLAGS
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// https://ia800509.us.archive.org/18/items/Programming_the_6502/Programming_the_6502.pdf
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func getWordInLine(line []uint8) uint16 {
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return uint16(line[1]) + 0x100*uint16(line[2])
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}
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func resolve(s *State, line []uint8, opcode opcode) (value uint8, address uint16, setValue func(uint8)) {
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hasAddress := true
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register := regNone
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switch opcode.addressMode {
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case modeAccumulator:
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value = s.Reg.getA()
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hasAddress = false
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register = regA
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case modeImplicitX:
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value = s.Reg.getX()
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hasAddress = false
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register = regX
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case modeImplicitY:
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value = s.Reg.getY()
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hasAddress = false
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register = regY
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case modeImmediate:
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value = line[1]
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hasAddress = false
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case modeZeroPage:
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address = uint16(line[1])
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case modeZeroPageX:
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address = uint16(line[1] + s.Reg.getX())
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case modeZeroPageY:
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address = uint16(line[1] + s.Reg.getY())
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case modeAbsolute:
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address = getWordInLine(line)
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case modeAbsoluteX:
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address = getWordInLine(line) + uint16(s.Reg.getX())
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case modeAbsoluteY:
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address = getWordInLine(line) + uint16(s.Reg.getY())
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case modeIndexedIndirectX:
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addressAddress := uint8(line[1] + s.Reg.getX())
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address = s.Mem.getZeroPageWord(addressAddress)
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case modeIndirect:
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addressAddress := getWordInLine(line)
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address = s.Mem.getWord(addressAddress)
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case modeIndirectIndexedY:
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address = s.Mem.getZeroPageWord(line[1]) +
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uint16(s.Reg.getY())
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}
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if hasAddress {
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value = s.Mem.Peek(address)
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}
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setValue = func(value uint8) {
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if hasAddress {
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s.Mem.Poke(address, value)
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} else if register != regNone {
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s.Reg.setRegister(register, value)
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} else {
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// Todo: assert impossible
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}
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}
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return
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}
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type opcode struct {
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name string
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bytes uint8
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cycles int
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addressMode int
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action opFunc
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}
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type opFunc func(s *State, line []uint8, opcode opcode)
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func buildOpTransfer(regSrc int, regDst int) opFunc {
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return func(s *State, line []uint8, opcode opcode) {
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value := s.Reg.getRegister(regSrc)
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s.Reg.setRegister(regDst, value)
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if regDst != regSP {
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s.Reg.updateFlagZN(value)
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}
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}
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}
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func buildOpIncDec(inc bool) opFunc {
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return func(s *State, line []uint8, opcode opcode) {
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value, _, setValue := resolve(s, line, opcode)
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if inc {
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value++
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} else {
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value--
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}
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s.Reg.updateFlagZN(value)
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setValue(value)
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}
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}
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func buildOpShift(isLeft bool, isRotate bool) opFunc {
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return func(s *State, line []uint8, opcode opcode) {
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value, _, setValue := resolve(s, line, opcode)
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oldCarry := s.Reg.getFlagBit(flagC)
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var carry bool
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if isLeft {
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carry = (value & 0x80) != 0
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value <<= 1
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if isRotate {
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value += oldCarry
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}
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} else {
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carry = (value & 0x01) != 0
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value >>= 1
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if isRotate {
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value += oldCarry << 7
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}
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}
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s.Reg.updateFlag(flagC, carry)
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s.Reg.updateFlagZN(value)
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setValue(value)
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}
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}
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func buildOpLoad(regDst int) opFunc {
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return func(s *State, line []uint8, opcode opcode) {
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value, _, _ := resolve(s, line, opcode)
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s.Reg.setRegister(regDst, value)
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s.Reg.updateFlagZN(value)
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}
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}
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func buildOpStore(regSrc int) opFunc {
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return func(s *State, line []uint8, opcode opcode) {
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_, _, setValue := resolve(s, line, opcode)
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value := s.Reg.getRegister(regSrc)
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setValue(value)
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}
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}
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func buildOpUpdateFlag(flag uint8, value bool) opFunc {
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return func(s *State, line []uint8, opcode opcode) {
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s.Reg.updateFlag(flag, value)
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}
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}
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func buildOpBranch(flag uint8, value bool) opFunc {
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return func(s *State, line []uint8, opcode opcode) {
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if s.Reg.getFlag(flag) == value {
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// This assumes that PC is already pointing to the next instruction
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pc := s.Reg.getPC()
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pc += uint16(int8(line[1]))
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s.Reg.setPC(pc)
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}
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}
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}
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func opBIT(s *State, line []uint8, opcode opcode) {
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value, _, _ := resolve(s, line, opcode)
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acc := s.Reg.getA()
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// Future note: The immediate addressing mode (65C02 or 65816 only) does not affect V.
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s.Reg.updateFlag(flagZ, value&acc == 0)
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s.Reg.updateFlag(flagN, value&(1<<7) != 0)
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s.Reg.updateFlag(flagV, value&(1<<6) != 0)
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}
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func buildOpCompare(reg int) opFunc {
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return func(s *State, line []uint8, opcode opcode) {
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value, _, _ := resolve(s, line, opcode)
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reference := s.Reg.getRegister(reg)
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s.Reg.updateFlagZN(reference - value)
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s.Reg.updateFlag(flagC, reference >= value)
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}
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}
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func operationAnd(a uint8, b uint8) uint8 { return a & b }
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func operationOr(a uint8, b uint8) uint8 { return a | b }
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func operationXor(a uint8, b uint8) uint8 { return a ^ b }
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func buildOpLogic(operation func(uint8, uint8) uint8) opFunc {
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return func(s *State, line []uint8, opcode opcode) {
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value, _, _ := resolve(s, line, opcode)
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result := operation(value, s.Reg.getA())
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s.Reg.setA(result)
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s.Reg.updateFlagZN(result)
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}
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}
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func opADC(s *State, line []uint8, opcode opcode) {
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value, _, _ := resolve(s, line, opcode)
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aValue := s.Reg.getA()
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carry := s.Reg.getFlagBit(flagC)
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total := uint16(aValue) + uint16(value) + uint16(carry)
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signedTotal := int16(int8(aValue)) + int16(int8(value)) + int16(carry)
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truncated := uint8(total)
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if s.Reg.getFlag(flagD) {
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totalBcdLo := int(aValue&0x0f) + int(value&0x0f) + int(carry)
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totalBcdHi := int(aValue>>4) + int(value>>4)
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if totalBcdLo >= 10 {
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totalBcdHi++
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}
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totalBcd := (totalBcdHi%10)<<4 + (totalBcdLo % 10)
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s.Reg.setA(uint8(totalBcd))
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s.Reg.updateFlag(flagC, totalBcdHi > 9)
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} else {
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s.Reg.setA(truncated)
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s.Reg.updateFlag(flagC, total > 0xFF)
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}
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// ZNV flags behave for BCD as if the operation was binary?
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s.Reg.updateFlagZN(truncated)
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s.Reg.updateFlag(flagV, signedTotal < -128 || signedTotal > 127)
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}
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func opSBC(s *State, line []uint8, opcode opcode) {
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value, _, _ := resolve(s, line, opcode)
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aValue := s.Reg.getA()
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carry := s.Reg.getFlagBit(flagC)
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total := 0x100 + uint16(aValue) - uint16(value) + uint16(carry) - 1
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signedTotal := int16(int8(aValue)) - int16(int8(value)) + int16(carry) - 1
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truncated := uint8(total)
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if s.Reg.getFlag(flagD) {
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totalBcdLo := 10 + int(aValue&0x0f) - int(value&0x0f) + int(carry) - 1
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totalBcdHi := 10 + int(aValue>>4) - int(value>>4)
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if totalBcdLo < 10 {
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totalBcdHi--
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}
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totalBcd := (totalBcdHi%10)<<4 + (totalBcdLo % 10)
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s.Reg.setA(uint8(totalBcd))
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s.Reg.updateFlag(flagC, totalBcdHi >= 10)
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} else {
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s.Reg.setA(truncated)
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s.Reg.updateFlag(flagC, total > 0xFF)
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}
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// ZNV flags behave for SBC as if the operation was binary
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s.Reg.updateFlagZN(truncated)
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s.Reg.updateFlag(flagV, signedTotal < -128 || signedTotal > 127)
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}
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const stackAddress uint16 = 0x0100
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func pushByte(s *State, value uint8) {
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adresss := stackAddress + uint16(s.Reg.getSP())
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s.Mem.Poke(adresss, value)
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s.Reg.setSP(s.Reg.getSP() - 1)
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}
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func pullByte(s *State) uint8 {
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s.Reg.setSP(s.Reg.getSP() + 1)
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adresss := stackAddress + uint16(s.Reg.getSP())
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return s.Mem.Peek(adresss)
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}
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func pushWord(s *State, value uint16) {
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pushByte(s, uint8(value>>8))
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pushByte(s, uint8(value))
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}
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func pullWord(s *State) uint16 {
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return uint16(pullByte(s)) +
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(uint16(pullByte(s)) << 8)
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}
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func opPLA(s *State, line []uint8, opcode opcode) {
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value := pullByte(s)
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s.Reg.setA(value)
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s.Reg.updateFlagZN(value)
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}
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func opPLP(s *State, line []uint8, opcode opcode) {
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value := pullByte(s)
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s.Reg.setP(value)
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}
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func opPHA(s *State, line []uint8, opcode opcode) {
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pushByte(s, s.Reg.getA())
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}
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func opPHP(s *State, line []uint8, opcode opcode) {
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pushByte(s, s.Reg.getP()|(flagB+flag5))
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}
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func opJMP(s *State, line []uint8, opcode opcode) {
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_, address, _ := resolve(s, line, opcode)
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s.Reg.setPC(address)
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}
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func opNOP(s *State, line []uint8, opcode opcode) {}
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func opJSR(s *State, line []uint8, opcode opcode) {
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pushWord(s, s.Reg.getPC()-1)
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_, address, _ := resolve(s, line, opcode)
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s.Reg.setPC(address)
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}
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func opRTI(s *State, line []uint8, opcode opcode) {
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s.Reg.setP(pullByte(s))
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s.Reg.setPC(pullWord(s))
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}
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func opRTS(s *State, line []uint8, opcode opcode) {
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s.Reg.setPC(pullWord(s) + 1)
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}
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func opBRK(s *State, line []uint8, opcode opcode) {
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pushWord(s, s.Reg.getPC()+1)
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pushByte(s, s.Reg.getP()|(flagB+flag5))
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s.Reg.setFlag(flagI)
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s.Reg.setPC(s.Mem.getWord(0xFFFE))
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}
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var opcodes = [256]opcode{
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0x00: opcode{"BRK", 1, 7, modeImplicit, opBRK},
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0x4C: opcode{"JMP", 3, 3, modeAbsolute, opJMP},
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0x6C: opcode{"JMP", 3, 3, modeIndirect, opJMP},
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0x20: opcode{"JSR", 3, 6, modeAbsolute, opJSR},
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0x40: opcode{"RTI", 1, 6, modeImplicit, opRTI},
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0x60: opcode{"RTS", 1, 6, modeImplicit, opRTS},
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0x48: opcode{"PHA", 1, 3, modeImplicit, opPHA},
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0x08: opcode{"PHP", 1, 3, modeImplicit, opPHP},
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0x68: opcode{"PLA", 1, 4, modeImplicit, opPLA},
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0x28: opcode{"PLP", 1, 4, modeImplicit, opPLP},
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0x09: opcode{"ORA", 2, 2, modeImmediate, buildOpLogic(operationOr)},
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0x05: opcode{"ORA", 2, 3, modeZeroPage, buildOpLogic(operationOr)},
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0x15: opcode{"ORA", 2, 4, modeZeroPageX, buildOpLogic(operationOr)},
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0x0D: opcode{"ORA", 3, 4, modeAbsolute, buildOpLogic(operationOr)},
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0x1D: opcode{"ORA", 3, 4, modeAbsoluteX, buildOpLogic(operationOr)}, // Extra cycles
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0x19: opcode{"ORA", 3, 4, modeAbsoluteY, buildOpLogic(operationOr)}, // Extra cycles
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0x01: opcode{"ORA", 2, 6, modeIndexedIndirectX, buildOpLogic(operationOr)},
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0x11: opcode{"ORA", 2, 5, modeIndirectIndexedY, buildOpLogic(operationOr)}, // Extra cycles
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0x29: opcode{"AND", 2, 2, modeImmediate, buildOpLogic(operationAnd)},
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0x25: opcode{"AND", 2, 3, modeZeroPage, buildOpLogic(operationAnd)},
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0x35: opcode{"AND", 2, 4, modeZeroPageX, buildOpLogic(operationAnd)},
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0x2D: opcode{"AND", 3, 4, modeAbsolute, buildOpLogic(operationAnd)},
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0x3D: opcode{"AND", 3, 4, modeAbsoluteX, buildOpLogic(operationAnd)}, // Extra cycles
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0x39: opcode{"AND", 3, 4, modeAbsoluteY, buildOpLogic(operationAnd)}, // Extra cycles
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0x21: opcode{"AND", 2, 6, modeIndexedIndirectX, buildOpLogic(operationAnd)},
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0x31: opcode{"AND", 2, 5, modeIndirectIndexedY, buildOpLogic(operationAnd)}, // Extra cycles
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0x49: opcode{"EOR", 2, 2, modeImmediate, buildOpLogic(operationXor)},
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0x45: opcode{"EOR", 2, 3, modeZeroPage, buildOpLogic(operationXor)},
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0x55: opcode{"EOR", 2, 4, modeZeroPageX, buildOpLogic(operationXor)},
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0x4D: opcode{"EOR", 3, 4, modeAbsolute, buildOpLogic(operationXor)},
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0x5D: opcode{"EOR", 3, 4, modeAbsoluteX, buildOpLogic(operationXor)}, // Extra cycles
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0x59: opcode{"EOR", 3, 4, modeAbsoluteY, buildOpLogic(operationXor)}, // Extra cycles
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0x41: opcode{"EOR", 2, 6, modeIndexedIndirectX, buildOpLogic(operationXor)},
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0x51: opcode{"EOR", 2, 5, modeIndirectIndexedY, buildOpLogic(operationXor)}, // Extra cycles
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0x69: opcode{"ADC", 2, 2, modeImmediate, opADC},
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0x65: opcode{"ADC", 2, 3, modeZeroPage, opADC},
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0x75: opcode{"ADC", 2, 4, modeZeroPageX, opADC},
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0x6D: opcode{"ADC", 3, 4, modeAbsolute, opADC},
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0x7D: opcode{"ADC", 3, 4, modeAbsoluteX, opADC}, // Extra cycles
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0x79: opcode{"ADC", 3, 4, modeAbsoluteY, opADC}, // Extra cycles
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0x61: opcode{"ADC", 2, 6, modeIndexedIndirectX, opADC},
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0x71: opcode{"ADC", 2, 5, modeIndirectIndexedY, opADC}, // Extra cycles
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0xE9: opcode{"SBC", 2, 2, modeImmediate, opSBC},
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0xE5: opcode{"SBC", 2, 3, modeZeroPage, opSBC},
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0xF5: opcode{"SBC", 2, 4, modeZeroPageX, opSBC},
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0xED: opcode{"SBC", 3, 4, modeAbsolute, opSBC},
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0xFD: opcode{"SBC", 3, 4, modeAbsoluteX, opSBC}, // Extra cycles
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0xF9: opcode{"SBC", 3, 4, modeAbsoluteY, opSBC}, // Extra cycles
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0xE1: opcode{"SBC", 2, 6, modeIndexedIndirectX, opSBC},
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0xF1: opcode{"SBC", 2, 5, modeIndirectIndexedY, opSBC}, // Extra cycles
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0x24: opcode{"BIT", 2, 3, modeZeroPage, opBIT},
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0x2C: opcode{"BIT", 3, 3, modeAbsolute, opBIT},
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0xC9: opcode{"CMP", 2, 2, modeImmediate, buildOpCompare(regA)},
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0xC5: opcode{"CMP", 2, 3, modeZeroPage, buildOpCompare(regA)},
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0xD5: opcode{"CMP", 2, 4, modeZeroPageX, buildOpCompare(regA)},
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0xCD: opcode{"CMP", 3, 4, modeAbsolute, buildOpCompare(regA)},
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0xDD: opcode{"CMP", 3, 4, modeAbsoluteX, buildOpCompare(regA)}, // Extra cycles
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0xD9: opcode{"CMP", 3, 4, modeAbsoluteY, buildOpCompare(regA)}, // Extra cycles
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0xC1: opcode{"CMP", 2, 6, modeIndexedIndirectX, buildOpCompare(regA)},
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0xD1: opcode{"CMP", 2, 5, modeIndirectIndexedY, buildOpCompare(regA)}, // Extra cycles
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0xE0: opcode{"CPX", 2, 2, modeImmediate, buildOpCompare(regX)},
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0xE4: opcode{"CPX", 2, 3, modeZeroPage, buildOpCompare(regX)},
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0xEC: opcode{"CPX", 3, 4, modeAbsolute, buildOpCompare(regX)},
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0xC0: opcode{"CPY", 2, 2, modeImmediate, buildOpCompare(regY)},
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0xC4: opcode{"CPY", 2, 3, modeZeroPage, buildOpCompare(regY)},
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0xCC: opcode{"CPY", 3, 4, modeAbsolute, buildOpCompare(regY)},
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0x2A: opcode{"ROL", 1, 2, modeAccumulator, buildOpShift(true, true)},
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0x26: opcode{"ROL", 2, 5, modeZeroPage, buildOpShift(true, true)},
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0x36: opcode{"ROL", 2, 6, modeZeroPageX, buildOpShift(true, true)},
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0x2E: opcode{"ROL", 3, 6, modeAbsolute, buildOpShift(true, true)},
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0x3E: opcode{"ROL", 3, 7, modeAbsoluteX, buildOpShift(true, true)},
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0x6A: opcode{"ROR", 1, 2, modeAccumulator, buildOpShift(false, true)},
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0x66: opcode{"ROR", 2, 5, modeZeroPage, buildOpShift(false, true)},
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0x76: opcode{"ROR", 2, 6, modeZeroPageX, buildOpShift(false, true)},
|
|
0x6E: opcode{"ROR", 3, 6, modeAbsolute, buildOpShift(false, true)},
|
|
0x7E: opcode{"ROR", 3, 7, modeAbsoluteX, buildOpShift(false, true)},
|
|
|
|
0x0A: opcode{"ASL", 1, 2, modeAccumulator, buildOpShift(true, false)},
|
|
0x06: opcode{"ASL", 2, 5, modeZeroPage, buildOpShift(true, false)},
|
|
0x16: opcode{"ASL", 2, 6, modeZeroPageX, buildOpShift(true, false)},
|
|
0x0E: opcode{"ASL", 3, 6, modeAbsolute, buildOpShift(true, false)},
|
|
0x1E: opcode{"ASL", 3, 7, modeAbsoluteX, buildOpShift(true, false)},
|
|
|
|
0x4A: opcode{"LSR", 1, 2, modeAccumulator, buildOpShift(false, false)},
|
|
0x46: opcode{"LSR", 2, 5, modeZeroPage, buildOpShift(false, false)},
|
|
0x56: opcode{"LSR", 2, 6, modeZeroPageX, buildOpShift(false, false)},
|
|
0x4E: opcode{"LSR", 3, 6, modeAbsolute, buildOpShift(false, false)},
|
|
0x5E: opcode{"LSR", 3, 7, modeAbsoluteX, buildOpShift(false, false)},
|
|
|
|
0x38: opcode{"SEC", 1, 2, modeImplicit, buildOpUpdateFlag(flagC, true)},
|
|
0xF8: opcode{"SED", 1, 2, modeImplicit, buildOpUpdateFlag(flagD, true)},
|
|
0x78: opcode{"SEI", 1, 2, modeImplicit, buildOpUpdateFlag(flagI, true)},
|
|
0x18: opcode{"CLC", 1, 2, modeImplicit, buildOpUpdateFlag(flagC, false)},
|
|
0xD8: opcode{"CLD", 1, 2, modeImplicit, buildOpUpdateFlag(flagD, false)},
|
|
0x58: opcode{"CLI", 1, 2, modeImplicit, buildOpUpdateFlag(flagI, false)},
|
|
0xB8: opcode{"CLV", 1, 2, modeImplicit, buildOpUpdateFlag(flagV, false)},
|
|
|
|
0xE6: opcode{"INC", 2, 5, modeZeroPage, buildOpIncDec(true)},
|
|
0xF6: opcode{"INC", 2, 6, modeZeroPageX, buildOpIncDec(true)},
|
|
0xEE: opcode{"INC", 3, 6, modeAbsolute, buildOpIncDec(true)},
|
|
0xFE: opcode{"INC", 3, 7, modeAbsoluteX, buildOpIncDec(true)},
|
|
0xC6: opcode{"DEC", 2, 5, modeZeroPage, buildOpIncDec(false)},
|
|
0xD6: opcode{"DEC", 2, 6, modeZeroPageX, buildOpIncDec(false)},
|
|
0xCE: opcode{"DEC", 3, 6, modeAbsolute, buildOpIncDec(false)},
|
|
0xDE: opcode{"DEC", 3, 7, modeAbsoluteX, buildOpIncDec(false)},
|
|
0xE8: opcode{"INX", 1, 2, modeImplicitX, buildOpIncDec(true)},
|
|
0xC8: opcode{"INY", 1, 2, modeImplicitY, buildOpIncDec(true)},
|
|
0xCA: opcode{"DEX", 1, 2, modeImplicitX, buildOpIncDec(false)},
|
|
0x88: opcode{"DEY", 1, 2, modeImplicitY, buildOpIncDec(false)},
|
|
|
|
0xAA: opcode{"TAX", 1, 2, modeImplicit, buildOpTransfer(regA, regX)},
|
|
0xA8: opcode{"TAY", 1, 2, modeImplicit, buildOpTransfer(regA, regY)},
|
|
0x8A: opcode{"TXA", 1, 2, modeImplicit, buildOpTransfer(regX, regA)},
|
|
0x98: opcode{"TYA", 1, 2, modeImplicit, buildOpTransfer(regY, regA)},
|
|
0x9A: opcode{"TXS", 1, 2, modeImplicit, buildOpTransfer(regX, regSP)},
|
|
0xBA: opcode{"TSX", 1, 2, modeImplicit, buildOpTransfer(regSP, regX)},
|
|
|
|
0xA9: opcode{"LDA", 2, 2, modeImmediate, buildOpLoad(regA)},
|
|
0xA5: opcode{"LDA", 2, 3, modeZeroPage, buildOpLoad(regA)},
|
|
0xB5: opcode{"LDA", 2, 4, modeZeroPageX, buildOpLoad(regA)},
|
|
0xAD: opcode{"LDA", 3, 4, modeAbsolute, buildOpLoad(regA)},
|
|
0xBD: opcode{"LDA", 3, 4, modeAbsoluteX, buildOpLoad(regA)}, // Extra cycles
|
|
0xB9: opcode{"LDA", 3, 4, modeAbsoluteY, buildOpLoad(regA)}, // Extra cycles
|
|
0xA1: opcode{"LDA", 2, 6, modeIndexedIndirectX, buildOpLoad(regA)},
|
|
0xB1: opcode{"LDA", 2, 5, modeIndirectIndexedY, buildOpLoad(regA)}, // Extra cycles
|
|
0xA2: opcode{"LDX", 2, 2, modeImmediate, buildOpLoad(regX)},
|
|
0xA6: opcode{"LDX", 2, 3, modeZeroPage, buildOpLoad(regX)},
|
|
0xB6: opcode{"LDX", 2, 4, modeZeroPageY, buildOpLoad(regX)},
|
|
0xAE: opcode{"LDX", 3, 4, modeAbsolute, buildOpLoad(regX)},
|
|
0xBE: opcode{"LDX", 3, 4, modeAbsoluteY, buildOpLoad(regX)}, // Extra cycles
|
|
0xA0: opcode{"LDY", 2, 2, modeImmediate, buildOpLoad(regY)},
|
|
0xA4: opcode{"LDY", 2, 3, modeZeroPage, buildOpLoad(regY)},
|
|
0xB4: opcode{"LDY", 2, 4, modeZeroPageX, buildOpLoad(regY)},
|
|
0xAC: opcode{"LDY", 3, 4, modeAbsolute, buildOpLoad(regY)},
|
|
0xBC: opcode{"LDY", 3, 4, modeAbsoluteX, buildOpLoad(regY)}, // Extra cycles
|
|
|
|
0x85: opcode{"STA", 2, 3, modeZeroPage, buildOpStore(regA)},
|
|
0x95: opcode{"STA", 2, 4, modeZeroPageX, buildOpStore(regA)},
|
|
0x8D: opcode{"STA", 3, 4, modeAbsolute, buildOpStore(regA)},
|
|
0x9D: opcode{"STA", 3, 5, modeAbsoluteX, buildOpStore(regA)},
|
|
0x99: opcode{"STA", 3, 5, modeAbsoluteY, buildOpStore(regA)},
|
|
0x81: opcode{"STA", 2, 6, modeIndexedIndirectX, buildOpStore(regA)},
|
|
0x91: opcode{"STA", 2, 6, modeIndirectIndexedY, buildOpStore(regA)},
|
|
0x86: opcode{"STX", 2, 3, modeZeroPage, buildOpStore(regX)},
|
|
0x96: opcode{"STX", 2, 4, modeZeroPageY, buildOpStore(regX)},
|
|
0x8E: opcode{"STX", 3, 4, modeAbsolute, buildOpStore(regX)},
|
|
0x84: opcode{"STY", 2, 3, modeZeroPage, buildOpStore(regY)},
|
|
0x94: opcode{"STY", 2, 4, modeZeroPageX, buildOpStore(regY)},
|
|
0x8C: opcode{"STY", 3, 4, modeAbsolute, buildOpStore(regY)},
|
|
|
|
0x90: opcode{"BCC", 2, 2, modeRelative, buildOpBranch(flagC, false)}, // Extra cycles
|
|
0xB0: opcode{"BCS", 2, 2, modeRelative, buildOpBranch(flagC, true)}, // Extra cycles
|
|
0xD0: opcode{"BNE", 2, 2, modeRelative, buildOpBranch(flagZ, false)}, // Extra cycles
|
|
0xF0: opcode{"BEQ", 2, 2, modeRelative, buildOpBranch(flagZ, true)}, // Extra cycles
|
|
0x10: opcode{"BPL", 2, 2, modeRelative, buildOpBranch(flagN, false)}, // Extra cycles
|
|
0x30: opcode{"BMI", 2, 2, modeRelative, buildOpBranch(flagN, true)}, // Extra cycles
|
|
0x50: opcode{"BVC", 2, 2, modeRelative, buildOpBranch(flagV, false)}, // Extra cycles
|
|
0x70: opcode{"BVS", 2, 2, modeRelative, buildOpBranch(flagV, true)}, // Extra cycles
|
|
|
|
0xEA: opcode{"NOP", 1, 2, modeImplicit, opNOP},
|
|
}
|
|
|
|
func executeLine(s *State, line []uint8) {
|
|
opcode := opcodes[line[0]]
|
|
opcode.action(s, line, opcode)
|
|
}
|
|
|
|
// ExecuteInstruction transforms the state given after a single instruction is executed.
|
|
func ExecuteInstruction(s *State, log bool) {
|
|
pc := s.Reg.getPC()
|
|
opcode := opcodes[s.Mem.Peek(pc)]
|
|
|
|
line := make([]uint8, opcode.bytes)
|
|
for i := uint8(0); i < opcode.bytes; i++ {
|
|
line[i] = s.Mem.Peek(pc)
|
|
pc++
|
|
}
|
|
s.Reg.setPC(pc)
|
|
|
|
if log {
|
|
fmt.Printf("%#04x %-12s: ", pc, lineString(s, line, opcode))
|
|
}
|
|
opcode.action(s, line, opcode)
|
|
if log {
|
|
value, address, _ := resolve(s, line, opcode)
|
|
fmt.Printf("%v, [%04x:%02x], [%02x]\n", s.Reg, address, value, line)
|
|
}
|
|
}
|
|
|
|
// Reset resets the processor state. Moves the program counter to the vector in 0cfffc.
|
|
func Reset(s *State) {
|
|
startAddress := s.Mem.getWord(0xfffc)
|
|
s.Reg.setPC(startAddress)
|
|
}
|
|
|
|
func lineString(s *State, line []uint8, opcode opcode) string {
|
|
t := opcode.name
|
|
switch opcode.addressMode {
|
|
case modeImplicit:
|
|
case modeImplicitX:
|
|
case modeImplicitY:
|
|
//Nothing
|
|
case modeAccumulator:
|
|
t += fmt.Sprintf(" A")
|
|
case modeImmediate:
|
|
t += fmt.Sprintf(" #%02x", line[1])
|
|
case modeZeroPage:
|
|
t += fmt.Sprintf(" $%02x", line[1])
|
|
case modeZeroPageX:
|
|
t += fmt.Sprintf(" $%02x,X", line[1])
|
|
case modeZeroPageY:
|
|
t += fmt.Sprintf(" $%02x,Y", line[1])
|
|
case modeRelative:
|
|
t += fmt.Sprintf(" *%+x", int8(line[1]))
|
|
case modeAbsolute:
|
|
t += fmt.Sprintf(" $%04x", getWordInLine(line))
|
|
case modeAbsoluteX:
|
|
t += fmt.Sprintf(" $%04x,X", getWordInLine(line))
|
|
case modeAbsoluteY:
|
|
t += fmt.Sprintf(" $%04x,Y", getWordInLine(line))
|
|
case modeIndirect:
|
|
t += fmt.Sprintf(" ($%04x)", getWordInLine(line))
|
|
case modeIndexedIndirectX:
|
|
t += fmt.Sprintf(" ($%02x,X)", line[1])
|
|
case modeIndirectIndexedY:
|
|
t += fmt.Sprintf(" ($%02x),Y", line[1])
|
|
default:
|
|
t += "UNKNOWN MODE"
|
|
}
|
|
return t
|
|
}
|