123 lines
2.2 KiB
Go
123 lines
2.2 KiB
Go
package izapple2
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/*
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RAM card with 128Kb. It's like 8 language cards.
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See:
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http://www.applelogic.org/files/SATURN128MAN.pdf
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*/
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// CardSaturn is a Saturn128 card
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type CardSaturn struct {
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cardBase
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readState bool
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writeState uint8
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altBank bool
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activeBlock uint8
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}
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// NewCardSaturn creates a new CardSaturn
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func NewCardSaturn() *CardSaturn {
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var c CardSaturn
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c.name = "Saturn 128KB Ram Card"
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return &c
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}
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const (
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saturnBlocks = 8
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)
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func (c *CardSaturn) assign(a *Apple2, slot int) {
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c.readState = false
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c.writeState = lcWriteEnabled
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c.altBank = true
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c.activeBlock = 0
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a.mmu.initLanguageRAM(saturnBlocks)
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// TODO: use addCardSoftSwitches()
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for i := uint8(0x0); i <= 0xf; i++ {
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iCopy := i
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c.addCardSoftSwitchR(iCopy, func() uint8 {
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c.ssAction(iCopy)
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return 0
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}, "SATURNR")
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c.addCardSoftSwitchW(iCopy, func(uint8) {
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c.ssAction(iCopy)
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}, "SATURNW")
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}
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c.cardBase.assign(a, slot)
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c.applyState()
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}
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func (c *CardSaturn) ssAction(ss uint8) {
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switch ss {
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case 0:
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// RAM read, no writes
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c.altBank = false
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c.readState = true
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c.writeState = lcWriteDisabled
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case 1:
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// ROM read, RAM write
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c.altBank = false
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c.readState = false
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c.writeState++
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case 2:
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// ROM read, no writes
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c.altBank = false
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c.readState = false
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c.writeState = lcWriteDisabled
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case 3:
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//RAM read, RAM write
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c.altBank = false
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c.readState = true
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c.writeState++
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case 4:
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c.activeBlock = 0
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case 5:
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c.activeBlock = 1
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case 6:
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c.activeBlock = 2
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case 7:
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c.activeBlock = 3
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case 8:
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// RAM read, no writes
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c.altBank = true
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c.readState = true
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c.writeState = lcWriteDisabled
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case 9:
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// ROM read, RAM write
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c.altBank = true
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c.readState = false
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c.writeState++
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case 10:
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// ROM read, no writes
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c.altBank = true
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c.readState = false
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c.writeState = lcWriteDisabled
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case 11:
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//RAM read, RAM write
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c.altBank = true
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c.readState = true
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c.writeState++
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case 12:
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c.activeBlock = 4
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case 13:
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c.activeBlock = 5
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case 14:
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c.activeBlock = 6
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case 15:
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c.activeBlock = 7
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}
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if c.writeState > lcWriteEnabled {
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c.writeState = lcWriteEnabled
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}
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c.applyState()
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}
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func (c *CardSaturn) applyState() {
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c.a.mmu.setLanguageRAMActiveBlock(c.activeBlock)
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c.a.mmu.setLanguageRAM(c.readState, c.writeState == lcWriteEnabled, c.altBank)
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}
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