mirror of
https://github.com/ivanizag/izapple2.git
synced 2024-10-31 20:09:02 +00:00
183 lines
3.8 KiB
Go
183 lines
3.8 KiB
Go
package apple2
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import (
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"encoding/binary"
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"io"
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)
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/*
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RAM card with 128Kb. It's like 8 language cards.
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http://www.applelogic.org/files/SATURN128MAN.pdf
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*/
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type cardSaturn struct {
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cardBase
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readState bool
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writeState int
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activeBank int
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activeBlock int
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ramBankA [saturnBlocks]*memoryRange // First 4kb to map in 0xD000-0xDFFF
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ramBankB [saturnBlocks]*memoryRange // Second 4kb to map in 0xD000-0xDFFF
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ramUpper [saturnBlocks]*memoryRange // Upper 8kb to map in 0xE000-0xFFFF
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}
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const (
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// Write enabling requires two sofstwitch accesses
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saturnWriteDisabled = 0
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saturnWriteHalfEnabled = 1
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saturnWriteEnabled = 2
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)
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const (
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saturnBlocks = 8
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)
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func (c *cardSaturn) assign(a *Apple2, slot int) {
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c.readState = false
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c.writeState = lcWriteEnabled
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c.activeBank = 1
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for i := 0; i < saturnBlocks; i++ {
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c.ramBankA[i] = newMemoryRange(0xd000, make([]uint8, 0x1000))
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c.ramBankB[i] = newMemoryRange(0xd000, make([]uint8, 0x1000))
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c.ramUpper[i] = newMemoryRange(0xe000, make([]uint8, 0x2000))
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}
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for i := 0x0; i <= 0xf; i++ {
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iCopy := i
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c.ssr[iCopy] = func(*ioC0Page) uint8 {
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c.ssAction(iCopy)
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return 0
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}
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c.ssw[iCopy] = func(*ioC0Page, uint8) {
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// Writing does not reset write count
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c.ssAction(iCopy)
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}
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}
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c.cardBase.assign(a, slot)
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c.applyState()
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}
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func (c *cardSaturn) ssAction(ss int) {
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switch ss {
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case 0:
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// RAM read, no writes
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c.activeBank = 0
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c.readState = true
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c.writeState = lcWriteDisabled
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case 1:
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// ROM read, RAM write
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c.activeBank = 0
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c.readState = false
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c.writeState++
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case 2:
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// ROM read, no writes
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c.activeBank = 0
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c.readState = false
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c.writeState = lcWriteDisabled
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case 3:
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//RAM read, RAM write
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c.activeBank = 0
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c.readState = true
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c.writeState++
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case 4:
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c.activeBlock = 0
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case 5:
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c.activeBlock = 1
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case 6:
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c.activeBlock = 2
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case 7:
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c.activeBlock = 3
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case 8:
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// RAM read, no writes
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c.activeBank = 1
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c.readState = true
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c.writeState = lcWriteDisabled
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case 9:
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// ROM read, RAM write
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c.activeBank = 1
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c.readState = false
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c.writeState++
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case 10:
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// ROM read, no writes
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c.activeBank = 1
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c.readState = false
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c.writeState = lcWriteDisabled
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case 11:
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//RAM read, RAM write
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c.activeBank = 1
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c.readState = true
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c.writeState++
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case 12:
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c.activeBlock = 4
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case 13:
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c.activeBlock = 5
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case 14:
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c.activeBlock = 6
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case 15:
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c.activeBlock = 7
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}
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if c.writeState > lcWriteEnabled {
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c.writeState = lcWriteEnabled
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}
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c.applyState()
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}
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func (c *cardSaturn) getActiveBank() [8]*memoryRange {
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if c.activeBank == 0 {
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return c.ramBankA
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}
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return c.ramBankB
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}
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func (c *cardSaturn) applyState() {
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mmu := c.a.mmu
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block := c.activeBlock
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if c.readState {
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mmu.setPagesRead(0xd0, 0xdf, c.getActiveBank()[block])
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mmu.setPagesRead(0xe0, 0xff, c.ramUpper[block])
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} else {
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mmu.setPagesRead(0xd0, 0xff, mmu.physicalROM)
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}
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if c.writeState == lcWriteEnabled {
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mmu.setPagesWrite(0xd0, 0xdf, c.getActiveBank()[block])
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mmu.setPagesWrite(0xe0, 0xff, c.ramUpper[block])
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} else {
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mmu.setPagesWrite(0xd0, 0xff, nil)
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}
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}
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func (c *cardSaturn) save(w io.Writer) {
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for i := 0; i < saturnBlocks; i++ {
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binary.Write(w, binary.BigEndian, c.readState)
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binary.Write(w, binary.BigEndian, c.writeState)
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binary.Write(w, binary.BigEndian, c.activeBank)
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binary.Write(w, binary.BigEndian, c.activeBlock)
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c.ramBankA[i].save(w)
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c.ramBankB[i].save(w)
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c.ramUpper[i].save(w)
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}
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c.cardBase.save(w)
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}
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func (c *cardSaturn) load(r io.Reader) {
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for i := 0; i < saturnBlocks; i++ {
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binary.Read(r, binary.BigEndian, &c.readState)
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binary.Read(r, binary.BigEndian, &c.writeState)
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binary.Read(r, binary.BigEndian, &c.activeBank)
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binary.Read(r, binary.BigEndian, &c.activeBlock)
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c.ramBankA[i].load(r)
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c.ramBankB[i].load(r)
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c.ramUpper[i].load(r)
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c.applyState()
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}
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c.cardBase.load(r)
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}
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