mirror of
https://github.com/ivanizag/izapple2.git
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126 lines
2.9 KiB
Go
126 lines
2.9 KiB
Go
package izapple2
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/*
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Language card with 16 extra kb for the Apple ][ and ][+
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Manual: http://www.applelogic.org/files/LANGCARDMAN.pdf
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The language card doesn't have ROM for Cx00. It would not
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be used in slot 0 anyway.
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Note also that language cards for the Apple ][ had ROM on
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board to replace the main board F8 ROM with Autostart. That
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was not used/needed on the Apple ][+. As this emulates the
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Apple ][+, it is not considered. For the Plus it is often
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referred as Language card but it is really a 16 KB Ram card,
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"When RAM is deselected, the ROM on the Language card is selected for
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the top 2K ($F800-$FFFF), and the ROM on the main board is selected
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for $D000-$F7FF.
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Power on RESET initializes ROM to read mode and RAM to write mode,
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and selects the second 4K bank to map $D000-$DFFF."
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Writing to the softswitch disables writing in LC? Saw that
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somewhere but doing so fails IIe self check.
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*/
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// CardLanguage is an Language Card
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type CardLanguage struct {
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cardBase
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readState bool
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writeState uint8
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altBank bool // false is bank1, true is bank2
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}
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// NewCardLanguage creates a new CardLanguage
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func NewCardLanguage() *CardLanguage {
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var c CardLanguage
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c.name = "16KB Language Card"
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return &c
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}
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const (
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// Write enabling requires two softswitch accesses
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lcWriteDisabled = 0
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lcWriteHalfEnabled = 1
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lcWriteEnabled = 2
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)
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func (c *CardLanguage) reset() {
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if c.a.isApple2e {
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// UtA2e 1-3, 5-23
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c.readState = false
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c.writeState = lcWriteEnabled
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c.altBank = true // Start on bank2
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c.applyState()
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}
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}
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func (c *CardLanguage) assign(a *Apple2, slot int) {
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c.readState = false
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c.writeState = lcWriteEnabled
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c.altBank = true // Start on bank2
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a.mmu.initLanguageRAM(1)
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for i := uint8(0x0); i <= 0xf; i++ {
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iCopy := i
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c.addCardSoftSwitchR(iCopy, func() uint8 {
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c.ssAction(iCopy, false)
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return 0
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}, "LANGCARDR")
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c.addCardSoftSwitchW(iCopy, func(uint8) {
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c.ssAction(iCopy, true)
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}, "LANGCARDW")
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}
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c.cardBase.assign(a, slot)
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c.applyState()
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}
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func (c *CardLanguage) ssAction(ss uint8, write bool) {
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c.altBank = ((ss >> 3) & 1) == 0
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action := ss & 0x3
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switch action {
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case 0:
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// RAM read, no writes
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c.readState = true
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c.writeState = lcWriteDisabled
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case 1:
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// ROM read, RAM write
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c.readState = false
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if !write {
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c.writeState++
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}
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case 2:
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// ROM read, no writes
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c.readState = false
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c.writeState = lcWriteDisabled
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case 3:
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//RAM read, RAM write
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c.readState = true
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if !write {
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c.writeState++
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}
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}
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if write && c.writeState == lcWriteHalfEnabled {
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// UtA2e, 5-23. It is reset by even read access or any write acccess in the $C08x range
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// And https://github.com/zellyn/a2audit/issues/3
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c.writeState = lcWriteDisabled
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}
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if c.writeState > lcWriteEnabled {
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c.writeState = lcWriteEnabled
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}
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c.applyState()
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}
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func (c *CardLanguage) applyState() {
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c.a.mmu.setLanguageRAM(c.readState, c.writeState == lcWriteEnabled, c.altBank)
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}
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