141 lines
3.1 KiB
Go
141 lines
3.1 KiB
Go
package apple2
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import (
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"encoding/binary"
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"io"
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)
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/*
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Language card with 16 extra kb for the Apple ][ and ][+
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Manual: http://www.applelogic.org/files/LANGCARDMAN.pdf
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The language card doesn't have ROM for Cx00. It would not
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be used in slot 0 anyway.
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Note also that language cards for the Apple ][ had ROM on
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board to replace the main board F8 ROM with Autostart. That
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was not used/needed on the Apple ][+. As this emulates the
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Apple ][+, it is not considered. For the Plus it is often
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refered as Language card but it is really a 16 KB Ram card,
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"When RAM is deselected, the ROM on the Language card is selected for
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the top 2K ($F800-$FFFF), and the ROM on the main board is selected
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for $D000-$F7FF.
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Power on RESET initializes ROM to read mode and RAM to write mode,
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and selects the second 4K bank to map $D000-$DFFF."
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*/
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type cardLanguage struct {
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cardBase
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readState bool
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writeState uint8
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altBank bool // false is bank1, true is bank2
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}
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const (
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// Write enabling requires two softswitch accesses
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lcWriteDisabled = 0
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lcWriteHalfEnabled = 1
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lcWriteEnabled = 2
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)
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func (c *cardLanguage) assign(a *Apple2, slot int) {
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c.readState = false
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c.writeState = lcWriteEnabled
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c.altBank = true // Start on bank2
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if a.isApple2e {
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// The Apple //e with 128kb has two blocks of language upper RAM
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a.mmu.initLanguageRAM(2)
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} else {
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a.mmu.initLanguageRAM(1)
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}
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for i := uint8(0x0); i <= 0xf; i++ {
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iCopy := i
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c.addCardSoftSwitchR(iCopy, func(*ioC0Page) uint8 {
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c.ssAction(iCopy, false)
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return 0
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}, "LANGCARDR")
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c.addCardSoftSwitchW(iCopy, func(*ioC0Page, uint8) {
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c.ssAction(iCopy, true)
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}, "LANGCARDW")
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}
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c.cardBase.assign(a, slot)
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c.applyState()
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}
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func (c *cardLanguage) ssAction(ss uint8, write bool) {
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c.altBank = ((ss >> 3) & 1) == 0
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action := ss & 0x3
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switch action {
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case 0:
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// RAM read, no writes
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c.readState = true
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c.writeState = lcWriteDisabled
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case 1:
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// ROM read, RAM write
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c.readState = false
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c.writeState++
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case 2:
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// ROM read, no writes
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c.readState = false
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c.writeState = lcWriteDisabled
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case 3:
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//RAM read, RAM write
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c.readState = true
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c.writeState++
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}
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if c.writeState > lcWriteEnabled {
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c.writeState = lcWriteEnabled
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}
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// Writing to the softswtich disables writes.
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if write {
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c.writeState = lcWriteDisabled
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}
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c.applyState()
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}
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func (c *cardLanguage) applyState() {
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c.a.mmu.setLanguageRAM(c.readState, c.writeState == lcWriteEnabled, c.altBank)
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}
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func (c *cardLanguage) save(w io.Writer) error {
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err := binary.Write(w, binary.BigEndian, c.readState)
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if err != nil {
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return err
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}
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err = binary.Write(w, binary.BigEndian, c.writeState)
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if err != nil {
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return err
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}
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err = binary.Write(w, binary.BigEndian, c.altBank)
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if err != nil {
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return err
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}
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return c.cardBase.save(w)
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}
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func (c *cardLanguage) load(r io.Reader) error {
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err := binary.Read(r, binary.BigEndian, &c.readState)
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if err != nil {
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return err
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}
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err = binary.Read(r, binary.BigEndian, &c.writeState)
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if err != nil {
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return err
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}
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err = binary.Read(r, binary.BigEndian, &c.altBank)
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if err != nil {
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return err
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}
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c.applyState()
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return c.cardBase.load(r)
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}
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