269 lines
7.6 KiB
Go
269 lines
7.6 KiB
Go
package apple2
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import (
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"encoding/binary"
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"io"
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)
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// See https://fabiensanglard.net/fd_proxy/prince_of_persia/Inside%20the%20Apple%20IIe.pdf
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// See https://i.stack.imgur.com/yn21s.gif
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type memoryManager struct {
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apple2 *Apple2
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// Main RAM area: 0x0000 to 0xbfff
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physicalMainRAM *memoryRange // 0x0000 to 0xbfff, Up to 48 Kb
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physicalMainRAMAlt *memoryRange // 0x0000 to 0xbfff, Up to 48 Kb. Additional
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// Slots area: 0xc000 to 0xcfff
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cardsROM [8]memoryHandler //0xcs00 to 0xcsff. 256 bytes for each card
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cardsROMExtra [8]memoryHandler // 0xc800 to 0xcfff. 2048 bytes for each card
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physicalROMe memoryHandler // 0xc100 to 0xcfff, Zero or 4kb in the Apple2e
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// Upper area: 0xd000 to 0xffff
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physicalROM [4]memoryHandler // 0xd000 to 0xffff, 12 Kb. Up to four banks
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physicalDRAM []memoryHandler // 0xd000 to 0xdfff, 4KB. Up to 8 banks.
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physicalDAltRAM []memoryHandler // 0xd000 to 0xdfff, 4KB. Up to 8 banks.
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physicalEFRAM []memoryHandler // 0xe000 to 0xffff, 8KB. Up to 8 banks.
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// Configuration switches, Language cards
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lcSelectedBlock uint8 // Language card block selected. Usually, allways 0. But Saturn has 8
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lcActiveRead bool // Upper RAM active for read
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lcActiveWrite bool // Upper RAM active for read
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lcAltBank bool // Alternate
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// Configuration switches, Apple //e
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altZeroPage bool // Use extra RAM from 0x0000 to 0x01ff. And additional language card block
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altMainRAMActiveRead bool // Use extra RAM from 0x0200 to 0xbfff for read
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altMainRAMActiveWrite bool // Use extra RAM from 0x0200 to 0xbfff for write
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store80Active bool // Special pagination for text and graphics areas
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slotC3ROMActive bool // Apple2e slot 3 ROM shadow
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intCxROMActive bool // Apple2e slots internal ROM shadow
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activeSlot uint8 // Active slot owner of 0xc800 to 0xcfff
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// Configuration switches, Base64A
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romPage uint8 // Active ROM page
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}
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const (
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ioC8Off uint16 = 0xcfff
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addressLimitZero uint16 = 0x01ff
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addressStartText uint16 = 0x0400
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addressLimitText uint16 = 0x07ff
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addressStartHgr uint16 = 0x2000
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addressLimitHgr uint16 = 0x3fff
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addressLimitMainRAM uint16 = 0xbfff
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addressLimitIO uint16 = 0xc0ff
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addressLimitSlots uint16 = 0xc7ff
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addressLimitSlotsExtra uint16 = 0xcfff
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addressLimitDArea uint16 = 0xdfff
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)
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type memoryHandler interface {
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peek(uint16) uint8
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poke(uint16, uint8)
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}
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func newMemoryManager(a *Apple2) *memoryManager {
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var mmu memoryManager
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mmu.apple2 = a
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mmu.physicalMainRAM = newMemoryRange(0, make([]uint8, 0xc000))
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return &mmu
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}
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func (mmu *memoryManager) accessCArea(address uint16) memoryHandler {
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if mmu.intCxROMActive {
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return mmu.physicalROMe
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}
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// First slot area
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if address <= addressLimitSlots {
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slot := uint8((address >> 8) & 0x07)
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mmu.activeSlot = slot
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if !mmu.slotC3ROMActive && (slot == 3) {
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return mmu.physicalROMe
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}
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return mmu.cardsROM[slot]
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}
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// Extra slot area
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if address == ioC8Off {
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// Reset extra slot area owner
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mmu.activeSlot = 0
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}
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if !mmu.slotC3ROMActive && (mmu.activeSlot == 3) {
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return mmu.physicalROMe
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}
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return mmu.cardsROMExtra[mmu.activeSlot]
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}
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func (mmu *memoryManager) accessLCArea(address uint16) memoryHandler {
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block := mmu.lcSelectedBlock
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if mmu.altZeroPage {
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block = 1
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}
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if address <= addressLimitDArea {
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if mmu.lcAltBank {
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return mmu.physicalDAltRAM[block]
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}
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return mmu.physicalDRAM[block]
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}
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return mmu.physicalEFRAM[block]
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}
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func (mmu *memoryManager) getPhysicalMainRAM(alt bool) *memoryRange {
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if alt {
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return mmu.physicalMainRAMAlt
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}
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return mmu.physicalMainRAM
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}
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func (mmu *memoryManager) accessRead(address uint16) memoryHandler {
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if address <= addressLimitZero {
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return mmu.getPhysicalMainRAM(mmu.altZeroPage)
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}
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if mmu.store80Active && address <= addressLimitHgr {
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altPage := mmu.apple2.io.isSoftSwitchActive(ioFlagSecondPage)
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if address >= addressStartText && address <= addressLimitText {
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return mmu.getPhysicalMainRAM(altPage)
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}
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hires := mmu.apple2.io.isSoftSwitchActive(ioFlagHiRes)
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if hires && address >= addressStartHgr && address <= addressLimitHgr {
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return mmu.getPhysicalMainRAM(altPage)
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}
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}
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if address <= addressLimitMainRAM {
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return mmu.getPhysicalMainRAM(mmu.altMainRAMActiveRead)
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}
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if address <= addressLimitIO {
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return mmu.apple2.io
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}
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if address <= addressLimitSlotsExtra {
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return mmu.accessCArea(address)
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}
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if mmu.lcActiveRead {
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return mmu.accessLCArea(address)
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}
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return mmu.physicalROM[mmu.romPage]
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}
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func (mmu *memoryManager) accessWrite(address uint16) memoryHandler {
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if address <= addressLimitZero {
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return mmu.getPhysicalMainRAM(mmu.altZeroPage)
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}
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if address <= addressLimitHgr && mmu.store80Active {
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altPage := mmu.apple2.io.isSoftSwitchActive(ioFlagSecondPage)
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if address >= addressStartText && address <= addressLimitText {
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return mmu.getPhysicalMainRAM(altPage)
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}
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hires := mmu.apple2.io.isSoftSwitchActive(ioFlagHiRes)
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if hires && address >= addressStartHgr && address <= addressLimitHgr {
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return mmu.getPhysicalMainRAM(altPage)
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}
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}
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if address <= addressLimitMainRAM {
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return mmu.getPhysicalMainRAM(mmu.altMainRAMActiveWrite)
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}
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if address <= addressLimitIO {
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return mmu.apple2.io
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}
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if address <= addressLimitSlotsExtra {
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return mmu.accessCArea(address)
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}
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if mmu.lcActiveWrite {
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return mmu.accessLCArea(address)
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}
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return mmu.physicalROM[mmu.romPage]
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}
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// Peek returns the data on the given address
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func (mmu *memoryManager) Peek(address uint16) uint8 {
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mh := mmu.accessRead(address)
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if mh == nil {
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//fmt.Printf("Reading void addressing 0x%x\n", address)
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return 0xf4 // Or some random number
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}
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return mh.peek(address)
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}
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// Poke sets the data at the given address
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func (mmu *memoryManager) Poke(address uint16, value uint8) {
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mh := mmu.accessWrite(address)
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if mh == nil {
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//fmt.Printf("Writing to void addressing 0x%x\n", address)
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return
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}
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mh.poke(address, value)
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}
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// Memory initialization
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func (mmu *memoryManager) setCardROM(slot int, mh memoryHandler) {
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mmu.cardsROM[slot] = mh
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}
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func (mmu *memoryManager) setCardROMExtra(slot int, mh memoryHandler) {
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mmu.cardsROMExtra[slot] = mh
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}
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func (mmu *memoryManager) initLanguageRAM(groups int) {
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mmu.physicalDRAM = make([]memoryHandler, groups)
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mmu.physicalDAltRAM = make([]memoryHandler, groups)
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mmu.physicalEFRAM = make([]memoryHandler, groups)
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for i := 0; i < groups; i++ {
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mmu.physicalDRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x1000))
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mmu.physicalDAltRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x1000))
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mmu.physicalEFRAM[i] = newMemoryRange(0xe000, make([]uint8, 0x2000))
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}
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}
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func (mmu *memoryManager) InitRAMalt() {
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mmu.physicalMainRAMAlt = newMemoryRange(0, make([]uint8, 0xc000))
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}
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// Memory configuration
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func (mmu *memoryManager) setActiveROMPage(page uint8) {
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mmu.romPage = page
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}
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func (mmu *memoryManager) getActiveROMPage() uint8 {
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return mmu.romPage
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}
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func (mmu *memoryManager) setLanguageRAM(readActive bool, writeActive bool, altBank bool) {
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mmu.lcActiveRead = readActive
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mmu.lcActiveWrite = writeActive
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mmu.lcAltBank = altBank
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}
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func (mmu *memoryManager) setLanguageRAMBlock(block uint8) {
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block = block % uint8(len(mmu.physicalDRAM))
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mmu.lcSelectedBlock = block
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}
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// TODO: complete save and load
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func (mmu *memoryManager) save(w io.Writer) error {
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err := mmu.physicalMainRAM.save(w)
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if err != nil {
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return err
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}
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err = binary.Write(w, binary.BigEndian, mmu.activeSlot)
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if err != nil {
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return err
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}
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return nil
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}
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func (mmu *memoryManager) load(r io.Reader) error {
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err := mmu.physicalMainRAM.load(r)
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if err != nil {
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return err
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}
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err = binary.Read(r, binary.BigEndian, &mmu.activeSlot)
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if err != nil {
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return err
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}
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// mmu.activateCardRomExtra(mmu.activeSlot)
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return nil
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}
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