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puce6502.c
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554
puce6502.c
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/*
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puce6502 - MOS 6502 cpu emulator
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Last modified 1st of August 2020
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Copyright (c) 2018 Arthur Ferreira (arthur.ferreira2@gmail.com)
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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#include "puce6502.h"
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// function to be provided by user to handle read and writes to locations not
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// in ROM or in RAM : Soft Switches, extension cards ROMs, PIA, VIA, ACIA etc...
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extern uint8_t softSwitches(uint16_t address, uint8_t value);
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#define CARRY 0x01
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#define ZERO 0x02
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#define INTR 0x04
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#define DECIM 0x08
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#define BREAK 0x10
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#define UNDEF 0x20
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#define OFLOW 0x40
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#define SIGN 0x80
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struct Operand {
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uint8_t code;
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bool setAcc;
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uint16_t value, address;
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} ope;
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struct Register {
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uint8_t A,X,Y,SR,SP;
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uint16_t PC;
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} reg;
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// instruction timing :
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// http://nparker.llx.com/a2/opcodes.html
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// http://wouter.bbcmicro.net/general/6502/6502_opcodes.html
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// IMPLEMENTED :
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// The conditional branch instructions require a second extra cycle if the
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// branch happens and crosses a page boundary.
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// NOT IMPLEMENTED :
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// Absolute-X, absolute-Y, and Zpage-Y addressing modes need an extra cycle
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// if indexing crosses a page boundary, or if the instruction writes to memory.
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static int cycles[256] = { // cycle count per instruction
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7,6,0,0,0,3,5,0,3,2,2,0,0,4,6,0,3,5,0,0,0,4,6,0,2,4,0,0,0,4,7,0,
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6,6,0,0,3,3,5,0,4,2,2,0,4,4,6,0,3,5,0,0,0,4,6,0,2,4,0,0,0,4,7,0,
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6,6,0,0,0,3,5,0,3,2,2,0,3,4,6,0,3,5,0,0,0,4,6,0,2,4,0,0,0,4,7,0,
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6,6,0,0,0,3,5,0,4,2,2,0,5,4,6,0,3,5,0,0,0,4,6,0,2,4,0,0,0,4,7,0,
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0,6,0,0,3,3,3,0,2,0,2,0,4,4,4,0,3,6,0,0,4,4,4,0,2,5,2,0,0,5,0,0,
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2,6,2,0,3,3,3,0,2,2,2,0,4,4,4,0,3,5,0,0,4,4,4,0,2,4,2,0,4,4,4,0,
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2,6,0,0,3,3,5,0,2,2,2,0,4,4,6,0,3,5,0,0,0,4,6,0,2,4,0,0,0,4,7,0,
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2,6,0,0,3,3,5,0,2,2,2,0,4,4,6,0,3,5,0,0,0,4,6,0,2,4,0,0,0,4,7,0
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};
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//=============================================================== MEMORY AND I/O
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inline static uint8_t readMem(uint16_t address){
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if (address < RAMSIZE) return(ram[address]);
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if (address >= ROMSTART) return(rom[address - ROMSTART]);
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return softSwitches(address, 0); // MEMORY MAPPED I/O
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}
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inline static void writeMem(uint16_t address, uint8_t value){
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if (address < RAMSIZE) ram[address] = value;
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else if (address < ROMSTART) softSwitches(address, value);
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}
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//=============================================== STACK, SIGN AND OTHER ROUTINES
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inline static void push(uint8_t value){
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writeMem(0x100 + reg.SP--, value);
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}
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inline static uint8_t pull(){
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return(readMem(0x100 + ++reg.SP));
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}
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inline static void setSZ(uint8_t value){ // update both the Sign & Zero FLAGS
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if (value & 0x00FF) reg.SR &= ~ZERO;
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else reg.SR |= ZERO;
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if (value & 0x80) reg.SR |= SIGN;
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else reg.SR &= ~SIGN;
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}
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inline static void branch(){ // used by the 8 branch instructions
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ticks++;
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if (((reg.PC & 0xFF) + ope.address) & 0xFF00) ticks++;
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reg.PC += ope.address;
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}
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inline static void makeUpdates(uint8_t val){ // used by ASL, LSR, ROL and ROR
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if (ope.setAcc){
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reg.A = val;
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ope.setAcc = false;
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}
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else writeMem(ope.address, val);
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setSZ(val);
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}
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//============================================================= ADDRESSING MODES
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static void IMP(){ // IMPlicit
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}
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static void ACC(){ // ACCumulator
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ope.value = reg.A;
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ope.setAcc = true;
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}
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static void IMM(){ // IMMediate
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ope.address = reg.PC++;
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ope.value = readMem(ope.address);
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}
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static void ZPG(){ // Zero PaGe
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ope.address = readMem(reg.PC++);
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ope.value = readMem(ope.address);
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}
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static void ZPX(){ // Zero Page,X
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ope.address = (readMem(reg.PC++) + reg.X) & 0xFF;
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ope.value = readMem(ope.address);
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}
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static void ZPY(){ // Zero Page,Y
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ope.address = (readMem(reg.PC++) + reg.Y) & 0xFF;
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ope.value = readMem(ope.address);
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}
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static void REL(){ // RELative (for branch instructions)
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ope.address = readMem(reg.PC++);
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if (ope.address & 0x80) ope.address |= 0xFF00; // branch backward
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}
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static void ABS(){ // ABSolute
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ope.address = readMem(reg.PC) | (readMem(reg.PC + 1) << 8);
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ope.value = readMem(ope.address);
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reg.PC += 2;
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}
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static void ABX(){ // ABsolute,X
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ope.address = (readMem(reg.PC) | (readMem(reg.PC + 1) << 8)) + reg.X;
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ope.value = readMem(ope.address);
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reg.PC += 2;
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}
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static void ABY(){ // ABsolute,Y
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ope.address = (readMem(reg.PC) | (readMem(reg.PC + 1) << 8)) + reg.Y;
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ope.value = readMem(ope.address);
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reg.PC += 2;
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}
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static void IND(){ // INDirect - JMP ($ABCD) with page-boundary wraparound bug
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uint16_t vector1 = readMem(reg.PC) | (readMem(reg.PC + 1) << 8);
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uint16_t vector2 = (vector1 & 0xFF00) | ((vector1 + 1) & 0x00FF);
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ope.address = readMem(vector1) | (readMem(vector2) << 8);
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ope.value = readMem(ope.address);
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reg.PC += 2;
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}
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static void IDX(){ // InDexed indirect X
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uint16_t vector1 = ((readMem(reg.PC++) + reg.X) & 0xFF);
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ope.address = readMem(vector1 & 0x00FF)|(readMem((vector1+1) & 0x00FF) << 8);
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ope.value = readMem(ope.address);
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}
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static void IDY(){ // InDirect Indexed Y
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uint16_t vector1 = readMem(reg.PC++);
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uint16_t vector2 = (vector1 & 0xFF00) | ((vector1 + 1) & 0x00FF);
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ope.address = (readMem(vector1) | (readMem(vector2) << 8)) + reg.Y;
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ope.value = readMem(ope.address);
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}
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//================================================================= INSTRUCTIONS
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static void NOP(){ // NO Operation
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}
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void BRK(){ // BReaK
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push(((++reg.PC) >> 8) & 0xFF);
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push(reg.PC & 0xFF);
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push(reg.SR | BREAK);
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reg.SR |= INTR;
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reg.PC = readMem(0xFFFE) | (readMem(0xFFFF) << 8);
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}
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static void CLD(){ // CLear Decimal
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reg.SR &= ~DECIM;
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}
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static void SED(){ // SEt Decimal
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reg.SR |= DECIM;
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}
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static void CLC(){ // CLear Carry
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reg.SR &= ~CARRY;
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}
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static void SEC(){ // SEt Carry
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reg.SR |= CARRY;
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}
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static void CLI(){ // CLear Interrupt
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reg.SR &= ~INTR;
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}
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static void SEI(){ // SEt Interrupt
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reg.SR |= INTR;
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}
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static void CLV(){ // CLear oVerflow
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reg.SR &= ~OFLOW;
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}
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static void LDA(){ // LoaD Accumulator
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reg.A = ope.value;
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setSZ(reg.A);
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}
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static void LDX(){ // LoaD X
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reg.X = ope.value;
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setSZ(reg.X);
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}
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static void LDY(){ // LoaD Y
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reg.Y = ope.value;
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setSZ(reg.Y);
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}
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static void STA(){ // STore Accumulator
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writeMem(ope.address, reg.A);
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}
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static void STX(){ // STore X
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writeMem(ope.address, reg.X);
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}
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static void STY(){ // STore Y
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writeMem(ope.address, reg.Y);
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}
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static void DEC(){ // DECrement
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writeMem(ope.address, --ope.value);
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setSZ(ope.value);
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}
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static void DEX(){ // DEcrement X
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setSZ(--reg.X);
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}
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static void DEY(){ // DEcrement Y
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setSZ(--reg.Y);
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}
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static void INC(){ // INCrement
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writeMem(ope.address, ++ope.value);
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setSZ(ope.value);
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}
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static void INX(){ // INcrement X
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setSZ(++reg.X);
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}
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static void INY(){ // INcrement Y
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setSZ(++reg.Y);
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}
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static void TAX(){ // Transfer Accumulator to X
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reg.X = reg.A;
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setSZ(reg.X);
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}
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static void TAY(){ // Transfer Accumulator to Y
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reg.Y = reg.A;
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setSZ(reg.Y);
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}
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static void TXA(){ // Transfer X to Accumulator
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reg.A = reg.X;
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setSZ(reg.A);
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}
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static void TYA(){ // Transfer Y to Accumulator
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reg.A = reg.Y;
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setSZ(reg.A);
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}
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static void TSX(){ // Transfer Sp to X
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reg.X = reg.SP;
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setSZ(reg.X);
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}
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static void TXS(){ // Transfer X to Sp
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reg.SP = reg.X;
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}
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static void BEQ(){ // Branch on EQual (zero set)
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if (reg.SR & ZERO) branch();
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}
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static void BNE(){ // Branch on Not Equal (zero clear)
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if (!(reg.SR & ZERO)) branch();
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}
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static void BMI(){ // Branch if MInus : when negative, when SIGN is set
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if (reg.SR & SIGN) branch();
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}
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static void BPL(){ // Branch if PLus : when positive, when SIGN is clear
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if (!(reg.SR & SIGN)) branch();
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}
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static void BVS(){ // Branch on oVerflow Set
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if (reg.SR & OFLOW) branch();
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}
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static void BVC(){ // Branch on oVerflow Clear
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if (!(reg.SR & OFLOW)) branch();
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}
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static void BCS(){ // Branch on Carry Set
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if (reg.SR & CARRY) branch();
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}
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static void BCC(){ // Branch on Carry Clear
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if (!(reg.SR & CARRY)) branch();
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}
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static void PHA(){ // PusH A to the stack
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push(reg.A);
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}
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static void PLA(){ // PulL stack into A
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reg.A = pull();
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setSZ(reg.A);
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}
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static void PHP(){ // PusH Programm (Status) register to the stack
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push(reg.SR | BREAK);
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}
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static void PLP(){ // PulL stack into Programm (SR) register
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reg.SR = pull() | UNDEF;
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}
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static void JMP(){ // JuMP
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reg.PC = ope.address;
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}
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static void JSR(){ // Jump Sub-Routine
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push((--reg.PC >> 8) & 0xFF);
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push(reg.PC & 0xFF);
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reg.PC = ope.address;
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}
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static void RTS(){ // ReTurn from Sub-routine
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reg.PC = (pull() | (pull() << 8)) + 1;
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}
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static void RTI(){ // ReTurn from Interrupt
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reg.SR = pull();
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reg.PC = pull() | (pull() << 8);
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}
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static void CMP(){ // Compare with A
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setSZ(reg.A - ope.value);
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if (reg.A >= ope.value) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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}
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static void CPX(){ // Compare with X
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setSZ(reg.X - ope.value);
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if (reg.X >= ope.value) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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}
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static void CPY(){ // Compare with Y
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setSZ(reg.Y - ope.value);
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if (reg.Y >= ope.value) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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}
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static void AND(){ // AND with A
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reg.A &= ope.value;
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setSZ(reg.A);
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}
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static void ORA(){ // OR with A
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reg.A |= ope.value;
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setSZ(reg.A);
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}
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static void EOR(){ // Exclusive Or with A
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reg.A ^= ope.value;
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setSZ(reg.A);
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}
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static void BIT(){ // BIT with A - http://www.6502.org/tutorials/vflag.html
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if (reg.A & ope.value) reg.SR &= ~ZERO;
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else reg.SR |= ZERO;
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reg.SR = (reg.SR & 0x3F) | (ope.value & 0xC0); // update SIGN & OFLOW
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}
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static void ASL(){ // Arithmetic Shift Left
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uint16_t result = (ope.value << 1);
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if (result & 0xFF00) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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makeUpdates((uint8_t)(result & 0xFF));
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}
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static void LSR(){ // Logical Shift Right
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if (ope.value & 1) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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makeUpdates((uint8_t)((ope.value >> 1) & 0xFF));
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}
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static void ROL(){ // ROtate Left
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uint16_t result = ((ope.value << 1) | (reg.SR & CARRY));
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if (result & 0x100) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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makeUpdates((uint8_t)(result & 0xFF));
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}
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static void ROR(){ // ROtate Right
|
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uint16_t result = (ope.value >> 1) | ((reg.SR & CARRY) << 7);
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if (ope.value & 0x1) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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makeUpdates((uint8_t)(result & 0xFF));
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}
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||||
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static void ADC(){ // ADd with Carry
|
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uint16_t result = reg.A + ope.value + (reg.SR & CARRY);
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setSZ(result);
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if (((result)^(reg.A))&((result)^(ope.value))&0x0080) reg.SR |= OFLOW;
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else reg.SR &= ~OFLOW;
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if (reg.SR&DECIM) result += ((((result+0x66)^reg.A^ope.value)>>3)&0x22)*3;
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if (result & 0xFF00) reg.SR |= CARRY;
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else reg.SR &= ~CARRY;
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reg.A = (result & 0xFF);
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||||
}
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||||
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static void SBC(){ // SuBtract with Carry
|
||||
ope.value ^= 0xFF;
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if (reg.SR & DECIM) ope.value -= 0x0066;
|
||||
uint16_t result = reg.A + ope.value + (reg.SR & CARRY);
|
||||
setSZ(result);
|
||||
if (((result)^(reg.A))&((result)^(ope.value))&0x0080) reg.SR |= OFLOW;
|
||||
else reg.SR &= ~OFLOW;
|
||||
if (reg.SR&DECIM) result += ((((result+0x66)^reg.A^ope.value)>>3)&0x22)*3;
|
||||
if (result & 0xFF00) reg.SR |= CARRY;
|
||||
else reg.SR &= ~CARRY;
|
||||
reg.A = (result & 0xFF);
|
||||
}
|
||||
|
||||
static void UND(){ // UNDefined (not a valid or supported 6502 opcode)
|
||||
BRK();
|
||||
}
|
||||
|
||||
|
||||
//================================================================== JUMP TABLES
|
||||
|
||||
static void (*instruction[])(void) = {
|
||||
BRK, ORA, UND, UND, UND, ORA, ASL, UND, PHP, ORA, ASL, UND, UND, ORA, ASL, UND,
|
||||
BPL, ORA, UND, UND, UND, ORA, ASL, UND, CLC, ORA, UND, UND, UND, ORA, ASL, UND,
|
||||
JSR, AND, UND, UND, BIT, AND, ROL, UND, PLP, AND, ROL, UND, BIT, AND, ROL, UND,
|
||||
BMI, AND, UND, UND, UND, AND, ROL, UND, SEC, AND, UND, UND, UND, AND, ROL, UND,
|
||||
RTI, EOR, UND, UND, UND, EOR, LSR, UND, PHA, EOR, LSR, UND, JMP, EOR, LSR, UND,
|
||||
BVC, EOR, UND, UND, UND, EOR, LSR, UND, CLI, EOR, UND, UND, UND, EOR, LSR, UND,
|
||||
RTS, ADC, UND, UND, UND, ADC, ROR, UND, PLA, ADC, ROR, UND, JMP, ADC, ROR, UND,
|
||||
BVS, ADC, UND, UND, UND, ADC, ROR, UND, SEI, ADC, UND, UND, UND, ADC, ROR, UND,
|
||||
UND, STA, UND, UND, STY, STA, STX, UND, DEY, UND, TXA, UND, STY, STA, STX, UND,
|
||||
BCC, STA, UND, UND, STY, STA, STX, UND, TYA, STA, TXS, UND, UND, STA, UND, UND,
|
||||
LDY, LDA, LDX, UND, LDY, LDA, LDX, UND, TAY, LDA, TAX, UND, LDY, LDA, LDX, UND,
|
||||
BCS, LDA, UND, UND, LDY, LDA, LDX, UND, CLV, LDA, TSX, UND, LDY, LDA, LDX, UND,
|
||||
CPY, CMP, UND, UND, CPY, CMP, DEC, UND, INY, CMP, DEX, UND, CPY, CMP, DEC, UND,
|
||||
BNE, CMP, UND, UND, UND, CMP, DEC, UND, CLD, CMP, UND, UND, UND, CMP, DEC, UND,
|
||||
CPX, SBC, UND, UND, CPX, SBC, INC, UND, INX, SBC, NOP, UND, CPX, SBC, INC, UND,
|
||||
BEQ, SBC, UND, UND, UND, SBC, INC, UND, SED, SBC, UND, UND, UND, SBC, INC, UND
|
||||
};
|
||||
|
||||
static void (*addressing[])(void) = {
|
||||
IMP, IDX, IMP, IMP, IMP, ZPG, ZPG, IMP, IMP, IMM, ACC, IMP, IMP, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, IMP, ZPX, ZPX, IMP, IMP, ABY, IMP, IMP, IMP, ABX, ABX, IMP,
|
||||
ABS, IDX, IMP, IMP, ZPG, ZPG, ZPG, IMP, IMP, IMM, ACC, IMP, ABS, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, IMP, ZPX, ZPX, IMP, IMP, ABY, IMP, IMP, IMP, ABX, ABX, IMP,
|
||||
IMP, IDX, IMP, IMP, IMP, ZPG, ZPG, IMP, IMP, IMM, ACC, IMP, ABS, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, IMP, ZPX, ZPX, IMP, IMP, ABY, IMP, IMP, IMP, ABX, ABX, IMP,
|
||||
IMP, IDX, IMP, IMP, IMP, ZPG, ZPG, IMP, IMP, IMM, ACC, IMP, IND, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, IMP, ZPX, ZPX, IMP, IMP, ABY, IMP, IMP, IMP, ABX, ABX, IMP,
|
||||
IMP, IDX, IMP, IMP, ZPG, ZPG, ZPG, IMP, IMP, IMP, IMP, IMP, ABS, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, ZPX, ZPX, ZPY, IMP, IMP, ABY, IMP, IMP, IMP, ABX, IMP, IMP,
|
||||
IMM, IDX, IMM, IMP, ZPG, ZPG, ZPG, IMP, IMP, IMM, IMP, IMP, ABS, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, ZPX, ZPX, ZPY, IMP, IMP, ABY, IMP, IMP, ABX, ABX, ABY, IMP,
|
||||
IMM, IDX, IMP, IMP, ZPG, ZPG, ZPG, IMP, IMP, IMM, IMP, IMP, ABS, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, IMP, ZPX, ZPX, IMP, IMP, ABY, IMP, IMP, IMP, ABX, ABX, IMP,
|
||||
IMM, IDX, IMP, IMP, ZPG, ZPG, ZPG, IMP, IMP, IMM, IMP, IMP, ABS, ABS, ABS, IMP,
|
||||
REL, IDY, IMP, IMP, IMP, ZPX, ZPX, IMP, IMP, ABY, IMP, IMP, IMP, ABX, ABX, IMP
|
||||
};
|
||||
|
||||
|
||||
//========================================================= USER INTERFACE (API)
|
||||
|
||||
void puce6502Reset(){
|
||||
reg.PC = readMem(0xFFFC) | (readMem(0xFFFD) << 8);
|
||||
reg.SP = 0xFF;
|
||||
reg.SR = (reg.SR | INTR) & ~DECIM;
|
||||
ope.setAcc = false;
|
||||
ticks += 7;
|
||||
}
|
||||
|
||||
void puce6502Exec(long long int cycleCount){
|
||||
cycleCount += ticks; // cycleCount becomes the target ticks value
|
||||
while (ticks < cycleCount) {
|
||||
ope.code = readMem(reg.PC++); // FETCH and increment the Program Counter
|
||||
addressing[ope.code](); // DECODE against the addressing mode
|
||||
instruction[ope.code](); // EXECUTE the instruction
|
||||
ticks += cycles[ope.code]; // update ticks count
|
||||
}
|
||||
}
|
||||
|
||||
void puce6502Break() {
|
||||
BRK();
|
||||
}
|
||||
|
||||
void puce6502Goto(uint16_t address) {
|
||||
reg.PC = address;
|
||||
}
|
||||
@ -1,7 +1,7 @@
|
||||
/*
|
||||
Puce6502 - MOS 6502 cpu emulator
|
||||
Last modified 1st of August 2020
|
||||
Copyright (c) 2017 Arthur Ferreira
|
||||
Copyright (c) 2018 Arthur Ferreira (arthur.ferreira2@gmail.com)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
|
||||
Loading…
Reference in New Issue
Block a user