first cut of cpu + apple i/o
This commit is contained in:
Steven Hugg
commit
9768a71474
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@ -0,0 +1,6 @@
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test:
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rustc -o appletest --test apple.rs
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./appletest
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@ -0,0 +1,239 @@
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use mem::Mem;
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use util::Xorshift;
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static GR_TXMODE: int = 1;
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static GR_MIXMODE: int = 2;
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static GR_PAGE1: int = 4;
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static GR_HIRES: int = 8;
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static DBG_CPU: int = 1;
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static DBG_RDMEM: int = 2;
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static DBG_WRMEM: int = 4;
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static HW_LO: u16 = 0xC000;
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static ROM_LO: u16 = 0xD000;
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static ROM_LEN: u16 = 0x3000;
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pub trait Peripheral
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{
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fn doIO(&mut self, addr: u16, val: u8) -> u8;
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fn doHighIO(&mut self, addr: u16, val: u8) -> u8;
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}
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struct LangCardState
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{
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// language card switches
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auxRAMselected: bool,
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auxRAMbank: u8,
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writeinhibit: bool,
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// value to add when reading & writing each of these banks
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// bank 1 is D000-FFFF, bank 2 is D000-DFFF
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bank1rdoffset: int,
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bank2rdoffset: int,
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bank1wroffset: int,
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bank2wroffset: int,
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}
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impl LangCardState
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{
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fn new(auxRAMselected: bool, auxRAMbank: u8, writeinhibit: bool) -> LangCardState {
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LangCardState {
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auxRAMselected: auxRAMselected,
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auxRAMbank: auxRAMbank,
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writeinhibit: writeinhibit,
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// reset language card constants
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// 0x3000 = map 0xd000-0xffff -> 0x10000-0x12fff
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// -0x1000 = map 0xd000-0xdfff -> 0xc000-0xcfff
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bank1rdoffset: if auxRAMselected { 0x3000 } else { 0x0 },
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bank2rdoffset: if auxRAMselected { if auxRAMbank==2 { -0x1000 } else { 0x3000 } } else { 0x0 },
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bank1wroffset: if !writeinhibit { 0x3000 } else { 0x0 },
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bank2wroffset: if !writeinhibit { if auxRAMbank==2 { -0x1000 } else { 0x3000 } } else { 0x0 },
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}
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}
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}
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pub struct AppleII
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{
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mem: [u8, ..0x13000],
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slots: [Option<~Peripheral>, ..8],
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debugflags: int,
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kbdlatch: u8,
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grswitch: u16,
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soundstate: bool,
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aux: LangCardState,
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nreads: u16 // counts # of reads for noise() fn
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}
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impl Mem for AppleII
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{
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fn loadb(&mut self, addr: u16) -> u8
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{
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debug!("Read {:x}", addr);
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self.nreads += 1;
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let val =
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// see if it's from main memory (0x0000-0xbfff)
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if (addr < HW_LO) {
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self.mem[addr] & 0xff
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// see if it came from the ROM/LC area (0xd000-0xffff)
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} else if (addr >= ROM_LO) {
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if (addr >= 0xe000) {
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self.mem[addr as int + self.aux.bank1rdoffset] & 0xff
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} else {
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self.mem[addr as int + self.aux.bank2rdoffset] & 0xff
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}
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}
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// it must be an I/O location (0xc000-0xcfff)
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else if (addr < HW_LO + 0x100) {
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self.doIO(addr, 0)
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} else {
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match self.slots[(addr >> 8) & 7] {
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None => self.noise(),
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Some(ref mut p) => p.doHighIO(addr, 0) // TODO: maybe have optional value, or new method
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}
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};
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debug!("Read {:x} = {:x}", addr, val);
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return val;
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}
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fn storeb(&mut self, addr: u16, val: u8)
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{
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debug!("write {:x} = {:x}", addr, val);
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// see if it's from main memory (0x0000-0xbfff)
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if (addr < HW_LO)
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{
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self.mem[addr] = val;
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//dirty[addr >> 7] = true;
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}
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// see if it came from the ROM/LC area (0xd000-0xffff)
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else if (addr >= ROM_LO && /* auxRAMselected && */ !self.aux.writeinhibit)
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{
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if (addr >= 0xe000) {
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self.mem[addr as int + self.aux.bank1wroffset] = val;
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} else {
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self.mem[addr as int + self.aux.bank2wroffset] = val;
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}
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}
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// it must be an I/O location (0xc000-0xcfff)
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else if (addr < HW_LO + 0x100) {
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self.doIO(addr, val);
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} else {
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match self.slots[(addr >> 8) & 7] {
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None => (), // no-op
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Some(ref mut p) => { p.doHighIO(addr, val); }
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}
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}
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}
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}
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impl AppleII
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{
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pub fn new() -> AppleII { AppleII {
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mem: [ 0, ..0x13000 ],
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// TODO: slots: [ None, ..8 ],
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// https://gist.github.com/carl-eastlund/6264938
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slots: [ None, None, None, None, None, None, None, None ],
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aux: LangCardState::new(false, 1, true),
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debugflags: 0,
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kbdlatch: 0,
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grswitch: 0,
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soundstate: false,
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nreads: 0
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} }
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fn noise(&mut self) -> u8 { self.mem[self.nreads & 0xffff] }
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fn setGrSwitch(&mut self, addr: u16)
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{
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// graphics
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if ((addr & 1) != 0) {
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self.grswitch |= 1 << ((addr >> 1) & 0x07);
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} else {
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self.grswitch &= !(1 << ((addr >> 1) & 0x07));
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}
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debug!("switch {} grswitch = {}", addr, self.grswitch);
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}
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fn setAnnunciator(&mut self, addr: u16)
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{
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// nothing yet
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}
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fn fakeJoystick(&mut self, addr: u16) -> u8
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{
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// tapein, joystick, buttons
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match addr & 7 {
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1..3 => self.noise() & 0x7f, // buttons (off)
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4..5 => self.noise() | 0x80, // joystick
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_ => self.noise()
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}
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}
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fn doIO(&mut self, addr: u16, val: u8) -> u8
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{
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let slot = (addr >> 4) & 0x0f;
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match slot {
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0 => self.kbdlatch, // keyboard
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1 => { self.clearStrobe(); self.noise() } // reset kbd strobe
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3 => { self.soundstate = !self.soundstate; self.noise() } // speaker
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5 => { if ((addr & 0x0f) < 8) { self.setGrSwitch(addr); } else { self.setAnnunciator(addr); } self.noise() }
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6 => self.fakeJoystick(addr),
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7 if (addr == 0xc070) => self.noise() | 0x80, // joystick reset
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8 => { self.doLanguageCardIO(addr); self.noise() }
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9..15 => match self.slots[slot-8] {
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None => self.noise(),
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Some(ref mut p) => p.doIO(addr, val)
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},
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_ => self.noise()
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}
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}
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fn clearStrobe(&mut self)
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{
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self.kbdlatch &= 0x7f;
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debug!("Clear strobe");
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}
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pub fn keyPressed(&mut self, keycode: u8)
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{
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let mut key = (keycode | 0x80) & 0xff;
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// since we're an Apple II+, we don't do lowercase
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if (key >= 0xe1 && key <= 0xfa) { key -= 0x20; }
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self.kbdlatch = key;
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debug!("Key pressed: {}", key);
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}
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fn doLanguageCardIO(&mut self, addr:u16)
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{
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self.aux = match addr & 0xf
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{
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// Select aux RAM bank 2, write protected.
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0|4 => LangCardState::new(true, 2, true),
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// Select ROM, write enable aux RAM bank 2.
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1|5 => LangCardState::new(false, 2, false),
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// Select ROM, write protect aux RAM (either bank).
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2|6|10|14 => LangCardState::new(false, self.aux.auxRAMbank, true),
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// Select aux RAM bank 2, write enabled.
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3|7 => LangCardState::new(true, 2, false),
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// Select aux RAM bank 1, write protected.
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8|12 => LangCardState::new(true, 1, false),
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// Select ROM, write enable aux RAM bank 1.
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9|13 => LangCardState::new(false, 1, false),
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// Select aux RAM bank 1, write enabled.
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11|15 => LangCardState::new(true, 1, false),
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// TODO: shouldn't need this
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_ => fail!()
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}
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}
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pub fn read_roms(&mut self)
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{
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use std::io::File;
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use std::vec::bytes::copy_memory;
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let ap2rom = File::open(&Path::new("apple2.rom")).read_bytes(0x3000);
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copy_memory(self.mem.mut_slice(0xd000, 0xd000+0x3000), ap2rom);
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debug!("loaded apple2.rom");
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}
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}
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@ -0,0 +1,31 @@
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//
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// sprocketnes/nes.rs
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//
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// Author: Patrick Walton
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//
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#[feature(link_args, macro_rules)];
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//#[no_main];
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//extern mod native;
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//extern mod sdl;
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// NB: This must be first to pick up the macro definitions. What a botch.
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#[macro_escape]
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pub mod util;
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#[macro_escape]
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pub mod cpu;
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pub mod mem;
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pub mod a2;
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//pub mod diskii;
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mod tests;
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/*
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#[no_mangle]
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pub extern "C" fn SDL_main(argc: i32, argv: **u8) -> i32 {
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native::start(argc as int, argv, proc() main::start(argc, argv)) as i32
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}
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*/
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@ -0,0 +1,726 @@
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//
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// sprocketnes/cpu.rs
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//
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// Author: Patrick Walton
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//
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use mem::{Mem, MemUtil};
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//
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// Constants
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//
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static CARRY_FLAG: u8 = 1 << 0;
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static ZERO_FLAG: u8 = 1 << 1;
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static IRQ_FLAG: u8 = 1 << 2;
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static DECIMAL_FLAG: u8 = 1 << 3;
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static BREAK_FLAG: u8 = 1 << 4;
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static OVERFLOW_FLAG: u8 = 1 << 6;
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static NEGATIVE_FLAG: u8 = 1 << 7;
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static NMI_VECTOR: u16 = 0xfffa;
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static RESET_VECTOR: u16 = 0xfffc;
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static BRK_VECTOR: u16 = 0xfffe;
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/// The number of cycles that each machine operation takes. Indexed by opcode number.
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///
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/// FIXME: This is copied from FCEU.
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static CYCLE_TABLE: [u8, ..256] = [
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/*0x00*/ 7,6,2,8,3,3,5,5,3,2,2,2,4,4,6,6,
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/*0x10*/ 2,5,2,8,4,4,6,6,2,4,2,7,4,4,7,7,
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/*0x20*/ 6,6,2,8,3,3,5,5,4,2,2,2,4,4,6,6,
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/*0x30*/ 2,5,2,8,4,4,6,6,2,4,2,7,4,4,7,7,
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/*0x40*/ 6,6,2,8,3,3,5,5,3,2,2,2,3,4,6,6,
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/*0x50*/ 2,5,2,8,4,4,6,6,2,4,2,7,4,4,7,7,
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/*0x60*/ 6,6,2,8,3,3,5,5,4,2,2,2,5,4,6,6,
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/*0x70*/ 2,5,2,8,4,4,6,6,2,4,2,7,4,4,7,7,
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/*0x80*/ 2,6,2,6,3,3,3,3,2,2,2,2,4,4,4,4,
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/*0x90*/ 2,6,2,6,4,4,4,4,2,5,2,5,5,5,5,5,
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/*0xA0*/ 2,6,2,6,3,3,3,3,2,2,2,2,4,4,4,4,
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/*0xB0*/ 2,5,2,5,4,4,4,4,2,4,2,4,4,4,4,4,
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/*0xC0*/ 2,6,2,8,3,3,5,5,2,2,2,2,4,4,6,6,
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/*0xD0*/ 2,5,2,8,4,4,6,6,2,4,2,7,4,4,7,7,
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/*0xE0*/ 2,6,3,8,3,3,5,5,2,2,2,2,4,4,6,6,
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/*0xF0*/ 2,5,2,8,4,4,6,6,2,4,2,7,4,4,7,7,
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];
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//
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// Registers
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//
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struct Regs {
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a: u8,
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x: u8,
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y: u8,
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s: u8,
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flags: u8,
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pc: u16
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}
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impl Regs {
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fn new() -> Regs { Regs { a: 0, x: 0, y: 0, s: 0xfd, flags: 0x24, pc: 0xc000 } }
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}
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//
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// Addressing modes
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//
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trait AddressingMode<M> {
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fn load(&self, cpu: &mut Cpu<M>) -> u8;
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fn store(&self, cpu: &mut Cpu<M>, val: u8);
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}
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struct AccumulatorAddressingMode;
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impl<M:Mem> AddressingMode<M> for AccumulatorAddressingMode {
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fn load(&self, cpu: &mut Cpu<M>) -> u8 { cpu.regs.a }
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fn store(&self, cpu: &mut Cpu<M>, val: u8) { cpu.regs.a = val }
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}
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struct ImmediateAddressingMode;
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impl<M:Mem> AddressingMode<M> for ImmediateAddressingMode {
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fn load(&self, cpu: &mut Cpu<M>) -> u8 { cpu.loadb_bump_pc() }
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fn store(&self, _: &mut Cpu<M>, _: u8) {
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// Not particularly type-safe, but probably not worth using trait inheritance for this.
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fail!("can't store to immediate")
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}
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}
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struct MemoryAddressingMode(u16);
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impl<M:Mem> AddressingMode<M> for MemoryAddressingMode {
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fn load(&self, cpu: &mut Cpu<M>) -> u8 { match *self { MemoryAddressingMode(addr) => cpu.loadb(addr) } }
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fn store(&self, cpu: &mut Cpu<M>, val: u8) { match *self { MemoryAddressingMode(addr) => cpu.storeb(addr, val) } }
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}
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//
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// Opcode decoding
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//
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// This is implemented as a macro so that both the disassembler and the emulator can use it.
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//
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macro_rules! decode_op {
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($op:expr, $this:ident) => {
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// We try to keep this in the same order as the implementations above.
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// TODO: Use arm macros to fix some of this duplication.
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match $op {
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// Loads
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0xa1 => { let v = $this.indexed_indirect_x(); $this.lda(v) }
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0xa5 => { let v = $this.zero_page(); $this.lda(v) }
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0xa9 => { let v = $this.immediate(); $this.lda(v) }
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0xad => { let v = $this.absolute(); $this.lda(v) }
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0xb1 => { let v = $this.indirect_indexed_y(); $this.lda(v) }
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0xb5 => { let v = $this.zero_page_x(); $this.lda(v) }
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0xb9 => { let v = $this.absolute_y(); $this.lda(v) }
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0xbd => { let v = $this.absolute_x(); $this.lda(v) }
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0xa2 => { let v = $this.immediate(); $this.ldx(v) }
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0xa6 => { let v = $this.zero_page(); $this.ldx(v) }
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0xb6 => { let v = $this.zero_page_y(); $this.ldx(v) }
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0xae => { let v = $this.absolute(); $this.ldx(v) }
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0xbe => { let v = $this.absolute_y(); $this.ldx(v) }
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0xa0 => { let v = $this.immediate(); $this.ldy(v) }
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0xa4 => { let v = $this.zero_page(); $this.ldy(v) }
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0xb4 => { let v = $this.zero_page_x(); $this.ldy(v) }
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0xac => { let v = $this.absolute(); $this.ldy(v) }
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0xbc => { let v = $this.absolute_x(); $this.ldy(v) }
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// Stores
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0x85 => { let v = $this.zero_page(); $this.sta(v) }
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0x95 => { let v = $this.zero_page_x(); $this.sta(v) }
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0x8d => { let v = $this.absolute(); $this.sta(v) }
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0x9d => { let v = $this.absolute_x(); $this.sta(v) }
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0x99 => { let v = $this.absolute_y(); $this.sta(v) }
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0x81 => { let v = $this.indexed_indirect_x(); $this.sta(v) }
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0x91 => { let v = $this.indirect_indexed_y(); $this.sta(v) }
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0x86 => { let v = $this.zero_page(); $this.stx(v) }
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0x96 => { let v = $this.zero_page_y(); $this.stx(v) }
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0x8e => { let v = $this.absolute(); $this.stx(v) }
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0x84 => { let v = $this.zero_page(); $this.sty(v) }
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0x94 => { let v = $this.zero_page_x(); $this.sty(v) }
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0x8c => { let v = $this.absolute(); $this.sty(v) }
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// Arithmetic
|
||||
0x69 => { let v = $this.immediate(); $this.adc(v) }
|
||||
0x65 => { let v = $this.zero_page(); $this.adc(v) }
|
||||
0x75 => { let v = $this.zero_page_x(); $this.adc(v) }
|
||||
0x6d => { let v = $this.absolute(); $this.adc(v) }
|
||||
0x7d => { let v = $this.absolute_x(); $this.adc(v) }
|
||||
0x79 => { let v = $this.absolute_y(); $this.adc(v) }
|
||||
0x61 => { let v = $this.indexed_indirect_x(); $this.adc(v) }
|
||||
0x71 => { let v = $this.indirect_indexed_y(); $this.adc(v) }
|
||||
|
||||
0xe9 => { let v = $this.immediate(); $this.sbc(v) }
|
||||
0xe5 => { let v = $this.zero_page(); $this.sbc(v) }
|
||||
0xf5 => { let v = $this.zero_page_x(); $this.sbc(v) }
|
||||
0xed => { let v = $this.absolute(); $this.sbc(v) }
|
||||
0xfd => { let v = $this.absolute_x(); $this.sbc(v) }
|
||||
0xf9 => { let v = $this.absolute_y(); $this.sbc(v) }
|
||||
0xe1 => { let v = $this.indexed_indirect_x(); $this.sbc(v) }
|
||||
0xf1 => { let v = $this.indirect_indexed_y(); $this.sbc(v) }
|
||||
|
||||
// Comparisons
|
||||
0xc9 => { let v = $this.immediate(); $this.cmp(v) }
|
||||
0xc5 => { let v = $this.zero_page(); $this.cmp(v) }
|
||||
0xd5 => { let v = $this.zero_page_x(); $this.cmp(v) }
|
||||
0xcd => { let v = $this.absolute(); $this.cmp(v) }
|
||||
0xdd => { let v = $this.absolute_x(); $this.cmp(v) }
|
||||
0xd9 => { let v = $this.absolute_y(); $this.cmp(v) }
|
||||
0xc1 => { let v = $this.indexed_indirect_x(); $this.cmp(v) }
|
||||
0xd1 => { let v = $this.indirect_indexed_y(); $this.cmp(v) }
|
||||
|
||||
0xe0 => { let v = $this.immediate(); $this.cpx(v) }
|
||||
0xe4 => { let v = $this.zero_page(); $this.cpx(v) }
|
||||
0xec => { let v = $this.absolute(); $this.cpx(v) }
|
||||
|
||||
0xc0 => { let v = $this.immediate(); $this.cpy(v) }
|
||||
0xc4 => { let v = $this.zero_page(); $this.cpy(v) }
|
||||
0xcc => { let v = $this.absolute(); $this.cpy(v) }
|
||||
|
||||
// Bitwise operations
|
||||
0x29 => { let v = $this.immediate(); $this.and(v) }
|
||||
0x25 => { let v = $this.zero_page(); $this.and(v) }
|
||||
0x35 => { let v = $this.zero_page_x(); $this.and(v) }
|
||||
0x2d => { let v = $this.absolute(); $this.and(v) }
|
||||
0x3d => { let v = $this.absolute_x(); $this.and(v) }
|
||||
0x39 => { let v = $this.absolute_y(); $this.and(v) }
|
||||
0x21 => { let v = $this.indexed_indirect_x(); $this.and(v) }
|
||||
0x31 => { let v = $this.indirect_indexed_y(); $this.and(v) }
|
||||
|
||||
0x09 => { let v = $this.immediate(); $this.ora(v) }
|
||||
0x05 => { let v = $this.zero_page(); $this.ora(v) }
|
||||
0x15 => { let v = $this.zero_page_x(); $this.ora(v) }
|
||||
0x0d => { let v = $this.absolute(); $this.ora(v) }
|
||||
0x1d => { let v = $this.absolute_x(); $this.ora(v) }
|
||||
0x19 => { let v = $this.absolute_y(); $this.ora(v) }
|
||||
0x01 => { let v = $this.indexed_indirect_x(); $this.ora(v) }
|
||||
0x11 => { let v = $this.indirect_indexed_y(); $this.ora(v) }
|
||||
|
||||
0x49 => { let v = $this.immediate(); $this.eor(v) }
|
||||
0x45 => { let v = $this.zero_page(); $this.eor(v) }
|
||||
0x55 => { let v = $this.zero_page_x(); $this.eor(v) }
|
||||
0x4d => { let v = $this.absolute(); $this.eor(v) }
|
||||
0x5d => { let v = $this.absolute_x(); $this.eor(v) }
|
||||
0x59 => { let v = $this.absolute_y(); $this.eor(v) }
|
||||
0x41 => { let v = $this.indexed_indirect_x(); $this.eor(v) }
|
||||
0x51 => { let v = $this.indirect_indexed_y(); $this.eor(v) }
|
||||
|
||||
0x24 => { let v = $this.zero_page(); $this.bit(v) }
|
||||
0x2c => { let v = $this.absolute(); $this.bit(v) }
|
||||
|
||||
// Shifts and rotates
|
||||
0x2a => { let v = $this.accumulator(); $this.rol(v) }
|
||||
0x26 => { let v = $this.zero_page(); $this.rol(v) }
|
||||
0x36 => { let v = $this.zero_page_x(); $this.rol(v) }
|
||||
0x2e => { let v = $this.absolute(); $this.rol(v) }
|
||||
0x3e => { let v = $this.absolute_x(); $this.rol(v) }
|
||||
|
||||
0x6a => { let v = $this.accumulator(); $this.ror(v) }
|
||||
0x66 => { let v = $this.zero_page(); $this.ror(v) }
|
||||
0x76 => { let v = $this.zero_page_x(); $this.ror(v) }
|
||||
0x6e => { let v = $this.absolute(); $this.ror(v) }
|
||||
0x7e => { let v = $this.absolute_x(); $this.ror(v) }
|
||||
|
||||
0x0a => { let v = $this.accumulator(); $this.asl(v) }
|
||||
0x06 => { let v = $this.zero_page(); $this.asl(v) }
|
||||
0x16 => { let v = $this.zero_page_x(); $this.asl(v) }
|
||||
0x0e => { let v = $this.absolute(); $this.asl(v) }
|
||||
0x1e => { let v = $this.absolute_x(); $this.asl(v) }
|
||||
|
||||
0x4a => { let v = $this.accumulator(); $this.lsr(v) }
|
||||
0x46 => { let v = $this.zero_page(); $this.lsr(v) }
|
||||
0x56 => { let v = $this.zero_page_x(); $this.lsr(v) }
|
||||
0x4e => { let v = $this.absolute(); $this.lsr(v) }
|
||||
0x5e => { let v = $this.absolute_x(); $this.lsr(v) }
|
||||
|
||||
// Increments and decrements
|
||||
0xe6 => { let v = $this.zero_page(); $this.inc(v) }
|
||||
0xf6 => { let v = $this.zero_page_x(); $this.inc(v) }
|
||||
0xee => { let v = $this.absolute(); $this.inc(v) }
|
||||
0xfe => { let v = $this.absolute_x(); $this.inc(v) }
|
||||
|
||||
0xc6 => { let v = $this.zero_page(); $this.dec(v) }
|
||||
0xd6 => { let v = $this.zero_page_x(); $this.dec(v) }
|
||||
0xce => { let v = $this.absolute(); $this.dec(v) }
|
||||
0xde => { let v = $this.absolute_x(); $this.dec(v) }
|
||||
|
||||
0xe8 => $this.inx(),
|
||||
0xca => $this.dex(),
|
||||
0xc8 => $this.iny(),
|
||||
0x88 => $this.dey(),
|
||||
|
||||
// Register moves
|
||||
0xaa => $this.tax(),
|
||||
0xa8 => $this.tay(),
|
||||
0x8a => $this.txa(),
|
||||
0x98 => $this.tya(),
|
||||
0x9a => $this.txs(),
|
||||
0xba => $this.tsx(),
|
||||
|
||||
// Flag operations
|
||||
0x18 => $this.clc(),
|
||||
0x38 => $this.sec(),
|
||||
0x58 => $this.cli(),
|
||||
0x78 => $this.sei(),
|
||||
0xb8 => $this.clv(),
|
||||
0xd8 => $this.cld(),
|
||||
0xf8 => $this.sed(),
|
||||
|
||||
// Branches
|
||||
0x10 => $this.bpl(),
|
||||
0x30 => $this.bmi(),
|
||||
0x50 => $this.bvc(),
|
||||
0x70 => $this.bvs(),
|
||||
0x90 => $this.bcc(),
|
||||
0xb0 => $this.bcs(),
|
||||
0xd0 => $this.bne(),
|
||||
0xf0 => $this.beq(),
|
||||
|
||||
// Jumps
|
||||
0x4c => $this.jmp(),
|
||||
0x6c => $this.jmpi(),
|
||||
|
||||
// Procedure calls
|
||||
0x20 => $this.jsr(),
|
||||
0x60 => $this.rts(),
|
||||
0x00 => $this.brk(),
|
||||
0x40 => $this.rti(),
|
||||
|
||||
// Stack operations
|
||||
0x48 => $this.pha(),
|
||||
0x68 => $this.pla(),
|
||||
0x08 => $this.php(),
|
||||
0x28 => $this.plp(),
|
||||
|
||||
// No operation
|
||||
0xea => $this.nop(),
|
||||
|
||||
_ => fail!("unimplemented or illegal instruction")
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Main CPU implementation
|
||||
//
|
||||
|
||||
type Cycles = u64;
|
||||
|
||||
/// The main CPU structure definition.
|
||||
pub struct Cpu<M> {
|
||||
cy: Cycles,
|
||||
regs: Regs,
|
||||
mem: M,
|
||||
}
|
||||
|
||||
// The CPU implements Mem so that it can handle writes to the DMA register.
|
||||
impl<M:Mem> Mem for Cpu<M> {
|
||||
fn loadb(&mut self, addr: u16) -> u8 { self.mem.loadb(addr) }
|
||||
fn storeb(&mut self, addr: u16, val: u8) {
|
||||
// Handle OAM_DMA.
|
||||
if addr == 0x4014 {
|
||||
self.dma(val)
|
||||
} else {
|
||||
self.mem.storeb(addr, val)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<M:Mem> Cpu<M> {
|
||||
// Debugging
|
||||
#[cfg(cpuspew)]
|
||||
fn trace(&mut self) {
|
||||
let mut disassembler = Disassembler {
|
||||
pc: self.regs.pc,
|
||||
mem: &mut self.mem
|
||||
};
|
||||
println!(
|
||||
"%04X %-20s A:%02X X:%02X Y:%02X P:%02X SP:%02X CYC:%4u",
|
||||
self.regs.pc as uint,
|
||||
disassembler.disassemble(),
|
||||
self.regs.a as uint,
|
||||
self.regs.x as uint,
|
||||
self.regs.y as uint,
|
||||
self.regs.flags as uint,
|
||||
self.regs.s as uint,
|
||||
self.cy as uint
|
||||
);
|
||||
}
|
||||
#[cfg(not(cpuspew))]
|
||||
fn trace(&mut self) {}
|
||||
|
||||
// Performs DMA to the OAMDATA ($2004) register.
|
||||
fn dma(&mut self, hi_addr: u8) {
|
||||
for addr in range(hi_addr as uint << 8, (hi_addr + 1) as uint << 8) {
|
||||
let val = self.loadb(addr as u16);
|
||||
self.storeb(0x2004, val);
|
||||
|
||||
// FIXME: The last address sometimes takes 1 cycle, sometimes 2 -- NESdev isn't very
|
||||
// clear on this.
|
||||
self.cy += 2;
|
||||
}
|
||||
}
|
||||
|
||||
// Memory access helpers
|
||||
/// Loads the byte at the program counter and increments the program counter.
|
||||
fn loadb_bump_pc(&mut self) -> u8 {
|
||||
let val = self.loadb(self.regs.pc);
|
||||
self.regs.pc += 1;
|
||||
val
|
||||
}
|
||||
/// Loads two bytes (little-endian) at the program counter and bumps the program counter over
|
||||
/// them.
|
||||
fn loadw_bump_pc(&mut self) -> u16 {
|
||||
let val = self.loadw(self.regs.pc);
|
||||
self.regs.pc += 2;
|
||||
val
|
||||
}
|
||||
|
||||
// Stack helpers
|
||||
fn pushb(&mut self, val: u8) {
|
||||
self.storeb(0x100 + self.regs.s as u16, val);
|
||||
self.regs.s -= 1;
|
||||
}
|
||||
fn pushw(&mut self, val: u16) {
|
||||
// FIXME: Is this correct? FCEU has two self.storeb()s here. Might have different
|
||||
// semantics...
|
||||
self.storew(0x100 + (self.regs.s - 1) as u16, val);
|
||||
self.regs.s -= 2;
|
||||
}
|
||||
fn popb(&mut self) -> u8 {
|
||||
let val = self.loadb(0x100 + self.regs.s as u16 + 1);
|
||||
self.regs.s += 1;
|
||||
val
|
||||
}
|
||||
fn popw(&mut self) -> u16 {
|
||||
// FIXME: See comment in pushw().
|
||||
let val = self.loadw(0x100 + self.regs.s as u16 + 1);
|
||||
self.regs.s += 2;
|
||||
val
|
||||
}
|
||||
|
||||
// Flag helpers
|
||||
fn get_flag(&self, flag: u8) -> bool { (self.regs.flags & flag) != 0 }
|
||||
fn set_flag(&mut self, flag: u8, on: bool) {
|
||||
if on {
|
||||
self.regs.flags |= flag;
|
||||
} else {
|
||||
self.regs.flags &= !flag;
|
||||
}
|
||||
}
|
||||
fn set_flags(&mut self, val: u8) {
|
||||
// Flags get munged in a strange way relating to the unused bit 5 on the NES.
|
||||
self.regs.flags = (val | 0x30) - 0x10;
|
||||
}
|
||||
fn set_zn(&mut self, val: u8) -> u8 {
|
||||
self.set_flag(ZERO_FLAG, val == 0);
|
||||
self.set_flag(NEGATIVE_FLAG, (val & 0x80) != 0);
|
||||
val
|
||||
}
|
||||
|
||||
// Addressing modes
|
||||
fn immediate(&mut self) -> ImmediateAddressingMode { ImmediateAddressingMode }
|
||||
fn accumulator(&mut self) -> AccumulatorAddressingMode { AccumulatorAddressingMode }
|
||||
fn zero_page(&mut self) -> MemoryAddressingMode {
|
||||
MemoryAddressingMode(self.loadb_bump_pc() as u16)
|
||||
}
|
||||
fn zero_page_x(&mut self) -> MemoryAddressingMode {
|
||||
MemoryAddressingMode((self.loadb_bump_pc() + self.regs.x) as u16)
|
||||
}
|
||||
fn zero_page_y(&mut self) -> MemoryAddressingMode {
|
||||
MemoryAddressingMode((self.loadb_bump_pc() + self.regs.y) as u16)
|
||||
}
|
||||
fn absolute(&mut self) -> MemoryAddressingMode {
|
||||
MemoryAddressingMode(self.loadw_bump_pc())
|
||||
}
|
||||
fn absolute_x(&mut self) -> MemoryAddressingMode {
|
||||
MemoryAddressingMode(self.loadw_bump_pc() + self.regs.x as u16)
|
||||
}
|
||||
fn absolute_y(&mut self) -> MemoryAddressingMode {
|
||||
MemoryAddressingMode(self.loadw_bump_pc() + self.regs.y as u16)
|
||||
}
|
||||
fn indexed_indirect_x(&mut self) -> MemoryAddressingMode {
|
||||
let val = self.loadb_bump_pc();
|
||||
let addr = self.loadw_zp(val + self.regs.x);
|
||||
MemoryAddressingMode(addr)
|
||||
}
|
||||
fn indirect_indexed_y(&mut self) -> MemoryAddressingMode {
|
||||
let val = self.loadb_bump_pc();
|
||||
let addr = self.loadw_zp(val) + self.regs.y as u16;
|
||||
MemoryAddressingMode(addr)
|
||||
}
|
||||
|
||||
//
|
||||
// Instructions
|
||||
//
|
||||
|
||||
// Loads
|
||||
fn lda<AM:AddressingMode<M>>(&mut self, am: AM) {
|
||||
let val = am.load(self);
|
||||
self.regs.a = self.set_zn(val)
|
||||
}
|
||||
fn ldx<AM:AddressingMode<M>>(&mut self, am: AM) {
|
||||
let val = am.load(self);
|
||||
self.regs.x = self.set_zn(val)
|
||||
}
|
||||
fn ldy<AM:AddressingMode<M>>(&mut self, am: AM) {
|
||||
let val = am.load(self);
|
||||
self.regs.y = self.set_zn(val)
|
||||
}
|
||||
|
||||
// Stores
|
||||
fn sta<AM:AddressingMode<M>>(&mut self, am: AM) { am.store(self, self.regs.a) }
|
||||
fn stx<AM:AddressingMode<M>>(&mut self, am: AM) { am.store(self, self.regs.x) }
|
||||
fn sty<AM:AddressingMode<M>>(&mut self, am: AM) { am.store(self, self.regs.y) }
|
||||
|
||||
// Arithmetic
|
||||
#[inline(always)]
|
||||
fn adc<AM:AddressingMode<M>>(&mut self, am: AM) {
|
||||
let val = am.load(self);
|
||||
let mut result = self.regs.a as u32 + val as u32;
|
||||
if self.get_flag(CARRY_FLAG) {
|
||||
result += 1;
|
||||
}
|
||||
|
||||
self.set_flag(CARRY_FLAG, (result & 0x100) != 0);
|
||||
|
||||
let result = result as u8;
|
||||
self.set_flag(OVERFLOW_FLAG,
|
||||
(self.regs.a ^ val) & 0x80 == 0 && (self.regs.a ^ result) & 0x80 == 0x80);
|
||||
self.regs.a = self.set_zn(result);
|
||||
}
|
||||
#[inline(always)]
|
||||
fn sbc<AM:AddressingMode<M>>(&mut self, am: AM) {
|
||||
let val = am.load(self);
|
||||
let mut result = self.regs.a as u32 - val as u32;
|
||||
if !self.get_flag(CARRY_FLAG) {
|
||||
result -= 1;
|
||||
}
|
||||
|
||||
self.set_flag(CARRY_FLAG, (result & 0x100) == 0);
|
||||
|
||||
let result = result as u8;
|
||||
self.set_flag(OVERFLOW_FLAG,
|
||||
(self.regs.a ^ result) & 0x80 != 0 && (self.regs.a ^ val) & 0x80 == 0x80);
|
||||
self.regs.a = self.set_zn(result);
|
||||
}
|
||||
|
||||
// Comparisons
|
||||
fn cmp_base<AM:AddressingMode<M>>(&mut self, x: u8, am: AM) {
|
||||
let y = am.load(self);
|
||||
let result = x as u32 - y as u32;
|
||||
self.set_flag(CARRY_FLAG, (result & 0x100) == 0);
|
||||
let _ = self.set_zn(result as u8);
|
||||
}
|
||||
fn cmp<AM:AddressingMode<M>>(&mut self, am: AM) { self.cmp_base(self.regs.a, am) }
|
||||
fn cpx<AM:AddressingMode<M>>(&mut self, am: AM) { self.cmp_base(self.regs.x, am) }
|
||||
fn cpy<AM:AddressingMode<M>>(&mut self, am: AM) { self.cmp_base(self.regs.y, am) }
|
||||
|
||||
// Bitwise operations
|
||||
fn and<AM:AddressingMode<M>>(&mut self, am: AM) {
|
||||
let val = am.load(self) & self.regs.a;
|
||||
self.regs.a = self.set_zn(val)
|
||||
}
|
||||
fn ora<AM:AddressingMode<M>>(&mut self, am: AM) {
|
||||
let val = am.load(self) | self.regs.a;
|
||||
self.regs.a = self.set_zn(val)
|
||||
}
|
||||
fn eor<AM:AddressingMode<M>>(&mut self, am: AM) {
|
||||
let val = am.load(self) ^ self.regs.a;
|
||||
self.regs.a = self.set_zn(val)
|
||||
}
|
||||
fn bit<AM:AddressingMode<M>>(&mut self, am: AM) {
|
||||
let val = am.load(self);
|
||||
self.set_flag(ZERO_FLAG, (val & self.regs.a) == 0);
|
||||
self.set_flag(NEGATIVE_FLAG, (val & 0x80) != 0);
|
||||
self.set_flag(OVERFLOW_FLAG, (val & 0x40) != 0);
|
||||
}
|
||||
|
||||
// Shifts and rotates
|
||||
fn shl_base<AM:AddressingMode<M>>(&mut self, lsb: bool, am: AM) {
|
||||
let val = am.load(self);
|
||||
let new_carry = (val & 0x80) != 0;
|
||||
let mut result = val << 1;
|
||||
if lsb {
|
||||
result |= 1;
|
||||
}
|
||||
self.set_flag(CARRY_FLAG, new_carry);
|
||||
let val = self.set_zn(result as u8);
|
||||
am.store(self, val)
|
||||
}
|
||||
fn shr_base<AM:AddressingMode<M>>(&mut self, msb: bool, am: AM) {
|
||||
let val = am.load(self);
|
||||
let new_carry = (val & 0x1) != 0;
|
||||
let mut result = val >> 1;
|
||||
if msb {
|
||||
result |= 0x80;
|
||||
}
|
||||
self.set_flag(CARRY_FLAG, new_carry);
|
||||
let val = self.set_zn(result as u8);
|
||||
am.store(self, val)
|
||||
}
|
||||
fn rol<AM:AddressingMode<M>>(&mut self, am: AM) {
|
||||
let val = self.get_flag(CARRY_FLAG);
|
||||
self.shl_base(val, am)
|
||||
}
|
||||
fn ror<AM:AddressingMode<M>>(&mut self, am: AM) {
|
||||
let val = self.get_flag(CARRY_FLAG);
|
||||
self.shr_base(val, am)
|
||||
}
|
||||
fn asl<AM:AddressingMode<M>>(&mut self, am: AM) { self.shl_base(false, am) }
|
||||
fn lsr<AM:AddressingMode<M>>(&mut self, am: AM) { self.shr_base(false, am) }
|
||||
|
||||
// Increments and decrements
|
||||
fn inc<AM:AddressingMode<M>>(&mut self, am: AM) {
|
||||
let val = am.load(self);
|
||||
let val = self.set_zn(val + 1);
|
||||
am.store(self, val)
|
||||
}
|
||||
fn dec<AM:AddressingMode<M>>(&mut self, am: AM) {
|
||||
let val = am.load(self);
|
||||
let val = self.set_zn(val - 1);
|
||||
am.store(self, val)
|
||||
}
|
||||
fn inx(&mut self) { self.regs.x = self.set_zn(self.regs.x + 1) }
|
||||
fn dex(&mut self) { self.regs.x = self.set_zn(self.regs.x - 1) }
|
||||
fn iny(&mut self) { self.regs.y = self.set_zn(self.regs.y + 1) }
|
||||
fn dey(&mut self) { self.regs.y = self.set_zn(self.regs.y - 1) }
|
||||
|
||||
// Register moves
|
||||
fn tax(&mut self) { self.regs.x = self.set_zn(self.regs.a) }
|
||||
fn tay(&mut self) { self.regs.y = self.set_zn(self.regs.a) }
|
||||
fn txa(&mut self) { self.regs.a = self.set_zn(self.regs.x) }
|
||||
fn tya(&mut self) { self.regs.a = self.set_zn(self.regs.y) }
|
||||
fn txs(&mut self) { self.regs.s = self.regs.x }
|
||||
fn tsx(&mut self) { self.regs.x = self.set_zn(self.regs.s) }
|
||||
|
||||
// Flag operations
|
||||
fn clc(&mut self) { self.set_flag(CARRY_FLAG, false) }
|
||||
fn sec(&mut self) { self.set_flag(CARRY_FLAG, true) }
|
||||
fn cli(&mut self) { self.set_flag(IRQ_FLAG, false) }
|
||||
fn sei(&mut self) { self.set_flag(IRQ_FLAG, true) }
|
||||
fn clv(&mut self) { self.set_flag(OVERFLOW_FLAG, false) }
|
||||
fn cld(&mut self) { self.set_flag(DECIMAL_FLAG, false) }
|
||||
fn sed(&mut self) { self.set_flag(DECIMAL_FLAG, true) }
|
||||
|
||||
// Branches
|
||||
fn bra_base(&mut self, cond: bool) {
|
||||
let disp = self.loadb_bump_pc() as i8;
|
||||
if cond {
|
||||
self.regs.pc = (self.regs.pc as i32 + disp as i32) as u16;
|
||||
}
|
||||
}
|
||||
fn bpl(&mut self) {
|
||||
let flag = !self.get_flag(NEGATIVE_FLAG);
|
||||
self.bra_base(flag)
|
||||
}
|
||||
fn bmi(&mut self) {
|
||||
let flag = self.get_flag(NEGATIVE_FLAG);
|
||||
self.bra_base(flag)
|
||||
}
|
||||
fn bvc(&mut self) {
|
||||
let flag = !self.get_flag(OVERFLOW_FLAG);
|
||||
self.bra_base(flag)
|
||||
}
|
||||
fn bvs(&mut self) {
|
||||
let flag = self.get_flag(OVERFLOW_FLAG);
|
||||
self.bra_base(flag)
|
||||
}
|
||||
fn bcc(&mut self) {
|
||||
let flag = !self.get_flag(CARRY_FLAG);
|
||||
self.bra_base(flag)
|
||||
}
|
||||
fn bcs(&mut self) {
|
||||
let flag = self.get_flag(CARRY_FLAG);
|
||||
self.bra_base(flag)
|
||||
}
|
||||
fn bne(&mut self) {
|
||||
let flag = !self.get_flag(ZERO_FLAG);
|
||||
self.bra_base(flag)
|
||||
}
|
||||
fn beq(&mut self) {
|
||||
let flag = self.get_flag(ZERO_FLAG);
|
||||
self.bra_base(flag)
|
||||
}
|
||||
|
||||
// Jumps
|
||||
fn jmp(&mut self) { self.regs.pc = self.loadw_bump_pc() }
|
||||
fn jmpi(&mut self) {
|
||||
let addr = self.loadw_bump_pc();
|
||||
|
||||
// Replicate the famous CPU bug...
|
||||
let lo = self.loadb(addr);
|
||||
let hi = self.loadb((addr & 0xff00) | ((addr + 1) & 0x00ff));
|
||||
|
||||
self.regs.pc = (hi as u16 << 8) | lo as u16;
|
||||
}
|
||||
|
||||
// Procedure calls
|
||||
fn jsr(&mut self) {
|
||||
let addr = self.loadw_bump_pc();
|
||||
self.pushw(self.regs.pc - 1);
|
||||
self.regs.pc = addr;
|
||||
}
|
||||
fn rts(&mut self) { self.regs.pc = self.popw() + 1 }
|
||||
fn brk(&mut self) {
|
||||
self.pushw(self.regs.pc + 1);
|
||||
self.pushb(self.regs.flags); // FIXME: FCEU sets BREAK_FLAG and U_FLAG here, why?
|
||||
self.set_flag(IRQ_FLAG, true);
|
||||
self.regs.pc = self.loadw(BRK_VECTOR);
|
||||
}
|
||||
fn rti(&mut self) {
|
||||
let flags = self.popb();
|
||||
self.set_flags(flags);
|
||||
self.regs.pc = self.popw(); // NB: no + 1
|
||||
}
|
||||
|
||||
// Stack operations
|
||||
fn pha(&mut self) { self.pushb(self.regs.a) }
|
||||
fn pla(&mut self) {
|
||||
let val = self.popb();
|
||||
self.regs.a = self.set_zn(val)
|
||||
}
|
||||
fn php(&mut self) { self.pushb(self.regs.flags | BREAK_FLAG) }
|
||||
fn plp(&mut self) {
|
||||
let val = self.popb();
|
||||
self.set_flags(val)
|
||||
}
|
||||
|
||||
// No operation
|
||||
fn nop(&mut self) {}
|
||||
|
||||
// The main fetch-and-decode routine
|
||||
pub fn step(&mut self) {
|
||||
self.trace();
|
||||
|
||||
let op = self.loadb_bump_pc();
|
||||
decode_op!(op, self);
|
||||
|
||||
self.cy += CYCLE_TABLE[op] as Cycles;
|
||||
}
|
||||
|
||||
/// External interfaces
|
||||
pub fn reset(&mut self) { self.regs.pc = self.loadw(RESET_VECTOR); }
|
||||
|
||||
pub fn nmi(&mut self) {
|
||||
self.pushw(self.regs.pc);
|
||||
self.pushb(self.regs.flags);
|
||||
self.regs.pc = self.loadw(NMI_VECTOR);
|
||||
}
|
||||
|
||||
pub fn irq(&mut self) {
|
||||
if self.get_flag(IRQ_FLAG) {
|
||||
return;
|
||||
}
|
||||
|
||||
self.pushw(self.regs.pc);
|
||||
self.pushb(self.regs.flags);
|
||||
self.regs.pc = self.loadw(BRK_VECTOR);
|
||||
}
|
||||
|
||||
/// The constructor.
|
||||
pub fn new(mem: M) -> Cpu<M> { Cpu { cy: 0, regs: Regs::new(), mem: mem } }
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
//
|
||||
// sprocketnes/mem.rs
|
||||
//
|
||||
// Author: Patrick Walton
|
||||
//
|
||||
|
||||
//
|
||||
// The memory interface
|
||||
//
|
||||
|
||||
/// The basic memory interface
|
||||
pub trait Mem {
|
||||
fn loadb(&mut self, addr: u16) -> u8;
|
||||
fn storeb(&mut self, addr: u16, val: u8);
|
||||
}
|
||||
|
||||
pub trait MemUtil {
|
||||
fn loadw(&mut self, addr: u16) -> u16;
|
||||
fn storew(&mut self, addr: u16, val: u16);
|
||||
fn loadw_zp(&mut self, addr: u8) -> u16;
|
||||
}
|
||||
|
||||
impl<M:Mem> MemUtil for M {
|
||||
fn loadw(&mut self, addr: u16) -> u16 {
|
||||
self.loadb(addr) as u16 | (self.loadb(addr + 1) as u16 << 8)
|
||||
}
|
||||
fn storew(&mut self, addr: u16, val: u16) {
|
||||
self.storeb(addr, (val & 0xff) as u8);
|
||||
self.storeb(addr + 1, ((val >> 8) & 0xff) as u8);
|
||||
}
|
||||
// Like loadw, but has wraparound behavior on the zero page for address 0xff.
|
||||
fn loadw_zp(&mut self, addr: u8) -> u16 {
|
||||
self.loadb(addr as u16) as u16 | (self.loadb((addr + 1) as u16) as u16 << 8)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
|
||||
use cpu::Cpu;
|
||||
use mem::Mem;
|
||||
use a2::AppleII;
|
||||
|
||||
//
|
||||
|
||||
fn return_two() -> int {
|
||||
2
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn return_two_test() {
|
||||
let x = return_two();
|
||||
assert!(x == 2);
|
||||
}
|
||||
|
||||
pub struct Ram { mem: [u8, ..0x800] }
|
||||
|
||||
impl Mem for Ram {
|
||||
fn loadb(&mut self, addr: u16) -> u8 { self.mem[addr & 0x7ff] }
|
||||
fn storeb(&mut self, addr: u16, val: u8) { self.mem[addr & 0x7ff] = val }
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_cpu()
|
||||
{
|
||||
let ram = Ram { mem: [ 0, ..0x800 ] };
|
||||
let mut cpu = Cpu::new(ram);
|
||||
cpu.reset();
|
||||
assert!(cpu.regs.pc == 0);
|
||||
cpu.step();
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_a2()
|
||||
{
|
||||
let mut a2 = AppleII::new();
|
||||
a2.read_roms();
|
||||
let mut cpu = Cpu::new(a2);
|
||||
cpu.reset();
|
||||
for i in range(0,100) {
|
||||
cpu.step();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
//
|
||||
// sprocketnes/util.rs
|
||||
//
|
||||
// Author: Patrick Walton
|
||||
//
|
||||
|
||||
use std::io::File;
|
||||
use std::libc::{c_int, c_void, time_t};
|
||||
use std::ptr::null;
|
||||
|
||||
//
|
||||
// A tiny custom serialization infrastructure, used for savestates.
|
||||
//
|
||||
// TODO: Use the standard library's ToBytes and add a FromBytes -- or don't; this is such a small
|
||||
// amount of code it barely seems worth it.
|
||||
//
|
||||
|
||||
pub trait Save {
|
||||
fn save(&mut self, fd: &mut File);
|
||||
fn load(&mut self, fd: &mut File);
|
||||
}
|
||||
|
||||
impl Save for u8 {
|
||||
fn save(&mut self, fd: &mut File) { fd.write([ *self ]) }
|
||||
fn load(&mut self, fd: &mut File) { let mut buf = [ 0 ]; fd.read(buf); *self = buf[0]; }
|
||||
}
|
||||
|
||||
impl Save for u16 {
|
||||
fn save(&mut self, fd: &mut File) { fd.write([ *self as u8, (*self >> 8) as u8 ]) }
|
||||
fn load(&mut self, fd: &mut File) {
|
||||
let mut buf = [ 0, 0 ];
|
||||
fd.read(buf);
|
||||
*self = (buf[0] as u16) | ((buf[1] as u16) << 8);
|
||||
}
|
||||
}
|
||||
|
||||
impl Save for u64 {
|
||||
fn save(&mut self, fd: &mut File) {
|
||||
let mut buf = [ 0, ..8 ];
|
||||
for i in range(0, 8) {
|
||||
buf[i] = ((*self) >> (i * 8)) as u8;
|
||||
}
|
||||
fd.write(buf);
|
||||
}
|
||||
fn load(&mut self, fd: &mut File) {
|
||||
let mut buf = [ 0, ..8 ];
|
||||
fd.read(buf);
|
||||
*self = 0;
|
||||
for i in range(0, 8) {
|
||||
*self = *self | (buf[i] as u64 << (i * 8));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a> Save for &'a mut [u8] {
|
||||
fn save(&mut self, fd: &mut File) {
|
||||
fd.write(*self);
|
||||
}
|
||||
fn load(&mut self, fd: &mut File) {
|
||||
fd.read(*self);
|
||||
}
|
||||
}
|
||||
|
||||
impl Save for bool {
|
||||
fn save(&mut self, fd: &mut File) { fd.write([ if *self { 0 } else { 1 } ]) }
|
||||
fn load(&mut self, fd: &mut File) {
|
||||
let mut val: [u8, ..1] = [ 0 ];
|
||||
fd.read(val);
|
||||
*self = val[0] != 0
|
||||
}
|
||||
}
|
||||
|
||||
// A convenience macro to save and load entire structs.
|
||||
macro_rules! save_struct(
|
||||
($name:ident { $($field:ident),* }) => (
|
||||
impl Save for $name {
|
||||
fn save(&mut self, fd: &mut File) {
|
||||
$(self.$field.save(fd);)*
|
||||
}
|
||||
fn load(&mut self, fd: &mut File) {
|
||||
$(self.$field.load(fd);)*
|
||||
}
|
||||
}
|
||||
)
|
||||
)
|
||||
|
||||
macro_rules! save_enum(
|
||||
($name:ident { $val_0:ident, $val_1:ident }) => (
|
||||
impl Save for $name {
|
||||
fn save(&mut self, fd: &mut File) {
|
||||
let mut val: u8 = match *self { $val_0 => 0, $val_1 => 1 };
|
||||
val.save(fd)
|
||||
}
|
||||
fn load(&mut self, fd: &mut File) {
|
||||
let mut val: u8 = 0;
|
||||
val.load(fd);
|
||||
*self = if val == 0 { $val_0 } else { $val_1 };
|
||||
}
|
||||
}
|
||||
)
|
||||
)
|
||||
|
||||
//
|
||||
// Random number generation
|
||||
//
|
||||
|
||||
pub struct Xorshift {
|
||||
x: u32,
|
||||
y: u32,
|
||||
z: u32,
|
||||
w: u32,
|
||||
}
|
||||
|
||||
impl Xorshift {
|
||||
pub fn new() -> Xorshift {
|
||||
Xorshift { x: 123456789, y: 362436069, z: 521288629, w: 88675123 }
|
||||
}
|
||||
|
||||
pub fn next(&mut self) -> u32 {
|
||||
let t = self.x ^ (self.x << 11);
|
||||
self.x = self.y; self.y = self.z; self.z = self.w;
|
||||
self.w = self.w ^ (self.w >> 19) ^ (t ^ (t >> 8));
|
||||
self.w
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Simple assertions
|
||||
//
|
||||
|
||||
#[cfg(debug)]
|
||||
pub fn debug_assert(cond: bool, msg: &str) {
|
||||
if !cond {
|
||||
println(msg);
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(not(debug))]
|
||||
pub fn debug_assert(_: bool, _: &str) {}
|
||||
|
||||
#[cfg(debug)]
|
||||
pub fn debug_print(msg: &str) {
|
||||
println(msg);
|
||||
}
|
||||
|
||||
#[cfg(not(debug))]
|
||||
pub fn debug_print(_: &str) {}
|
||||
|
||||
//
|
||||
// Bindings for `gettimeofday(2)`
|
||||
//
|
||||
|
||||
struct timeval {
|
||||
tv_sec: time_t,
|
||||
tv_usec: u32,
|
||||
}
|
||||
|
||||
extern {
|
||||
fn gettimeofday(tp: *mut timeval, tzp: *c_void) -> c_int;
|
||||
}
|
||||
|
||||
pub fn current_time_millis() -> u64 {
|
||||
unsafe {
|
||||
let mut tv = timeval { tv_sec: 0, tv_usec: 0 };
|
||||
gettimeofday(&mut tv, null());
|
||||
(tv.tv_sec as u64) * 1000 + (tv.tv_usec as u64) / 1000
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue