mirror of https://github.com/rbanffy/sdisk2.git
281 lines
4.8 KiB
ArmAsm
281 lines
4.8 KiB
ArmAsm
/*------------------------------------------------------
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DISK II Emulator Farmware (1 of 2) for ATMEGA328P
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2009.11.16 by Koichi Nishida
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------------------------------------------------------*/
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/*
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This is a part of the firmware for DISK II emulator by Nishida Radio.
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Copyright (C) 2009 Koichi NISHIDA
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email to Koichi NISHIDA: tulip-house@msf.biglobe.ne.jp
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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if the crystal on your SDISK II is 25 MHz,
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I recommend you to replace it with 27 MHz,
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or ask Nishida Radio.
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if you don't want to replace it, change the following to
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.equ CRYSTAL, 25
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*/
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.equ CRYSTAL, 27
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.equ PINB, 0x03
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.equ DDRB, 0x04
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.equ PORTB, 0x05
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.equ PINC, 0x06
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.equ DDRC, 0x07
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.equ PORTC, 0x08
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.equ PIND, 0x09
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.equ DDRD, 0x0a
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.equ PORTD, 0x0b
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.equ SREG, 0x3f
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.equ TCNT0, 0x26
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.global __vector_1
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.global __vector_16
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.global wait5
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.global readPulse
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.global bitByte
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.global sector
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.global prepare
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.global writeData
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.global writeBack
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.global writePtr
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.func wait5
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wait5:
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ldi r18,24
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wait51:
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nop
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dec r18
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brne wait51
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sbiw r24,1
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brne wait5
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ret
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.endfunc
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.func wait1
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wait1:
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nop ; 1
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nop ; 1
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nop ; 1
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nop ; 1
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nop ; 1
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nop ; 1
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nop ; 1
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nop ; 1
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.if CRYSTAL==25
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nop ; 1
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.endif
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ret ; 4
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.endfunc
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.func __vector_16
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__vector_16:
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push r26
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in r26, SREG
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push r26
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push r27
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push r18
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lds r26,readPulse
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lds r18,protect
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or r26,r18
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out PORTC,r26
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.if CRYSTAL==27
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ldi r26,170 ; 1
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.else
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ldi r26,180 ; 1
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.endif
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out TCNT0,r26 ; 1
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ldi r18,0 ; 1
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rcall wait1 ; 11
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lds r26,protect ; 2
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out PORTC,r26
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lds r27,prepare
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and r27,r27
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breq NOT_PREPARE
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sts readPulse,r18
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pop r18
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pop r27
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pop r26
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out SREG,r26
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pop r26
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reti
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NOT_PREPARE:
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ldi r26,0b00110000 ; 1
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out PORTD,r26 ; 1
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in r26,PIND ; 1
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andi r26,1 ; 1
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lsl r26 ; 1
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mov r18,r26 ; 1
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ldi r26,0b00010000 ; 1
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out PORTD,r26 ; 1
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lds r26,bitbyte
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lds r27,(bitbyte+1)
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adiw r26,1
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sts bitbyte,r26
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sts (bitbyte+1),r27
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cpi r26,((402*8)%256)
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brne LBL1
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cpi r27,((402*8)/256)
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brne LBL1
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; set prepare flag
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ldi r26,1
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sts prepare,r26
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; discard 112 byte (including CRC 2 byte)
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push r28
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ldi r28,112
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DSC_LP2:
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ldi r26,8
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DSC_LP1:
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ldi r27,0b00110000 ; 1
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out PORTD,r27 ; 1
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ldi r27,0b00010000 ; 1
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out PORTD,r27
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dec r26
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brne DSC_LP1
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dec r28
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brne DSC_LP2
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pop r28
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LBL1:
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sts readPulse,r18
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pop r18
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pop r27
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pop r26
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out SREG,r26
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pop r26
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reti
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.endfunc
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.func __vector_1
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__vector_1:
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push r18 ; 1
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in r18, SREG ; 1
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push r18 ; 1
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sbic PINC,0
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rjmp NOT_ENABLE
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push r19 ; 2
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lds r19,magState; 2
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WLP8:
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; wait start bit 1
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in r18,PINC ; 1
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andi r18,4 ; 1
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eor r18,r19 ; 1
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breq WLP8 ; 2/1
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in r18,PINC ; 1
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andi r18,4 ; 1
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sts magState,r18; 2
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ldi r18, 8 ; 1
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WLP9:
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dec r18 ; 1
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brne WLP9 ; 2
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nop ; 1
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push r20 ; 2
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push r21 ; 2
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push r22 ; 2
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push r23 ; 2
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push r24 ; 2
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push r30 ; 2
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push r31 ; 2
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ldi r22,0 ; 1 start storing
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lds r30,(writePtr)
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lds r31,(writePtr+1)
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ldi r19,lo8(349) ;1
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ldi r20,hi8(349) ;1
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rjmp ENTR ; 2
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WLP2:
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lds r21,magState; 2
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WLP6:
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; wait start bit 1
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in r23,PINC ; 1
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andi r23,4 ; 1
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eor r23,r21 ; 1
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breq WLP6 ; 2/1
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in r23,PINC ; 1
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andi r23,4 ; 1
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sts magState,r23; 2
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ldi r23, 14 ; 1
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WLP7:
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dec r23 ; 1
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brne WLP7 ; 2
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ENTR:
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ldi r18,7 ; 1
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ldi r24,1 ; 1
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WLP1:
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in r23,PIND ; 1
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andi r23,4 ; 1
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brne WRITE_END ; 1
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nop ; 1
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.if CRYSTAL==27
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ldi r23, 30 ; 1
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.else
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nop
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ldi r23,27 ; 1
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.endif
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WLP3:
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dec r23 ; 1
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brne WLP3 ; 2
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WLP5:
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in r23,PINC ; 1
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andi r23,4 ; 1
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lds r21,magState; 2
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sts magState,r23; 2
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eor r23,r21 ; 1
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lsr r23 ; 1
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lsr r23 ; 1
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lsl r24 ; 1
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or r24,r23 ; 1
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dec r18 ; 1
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brne WLP1 ; 2/1
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cpi r24,0xD5 ; 1
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brne NOT_START ; 2/1
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ldi r22,1 ; 1
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NOT_START:
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cpi r22,0 ; 1
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breq WLP2 ; 1
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st Z+,r24 ; 2
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subi r19,1 ; 1
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sbci r20,0 ; 1
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brne WLP2 ; 2/1
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WRITE_END:
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push r25
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push r26
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push r27
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call writeBack
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pop r27
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pop r26
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pop r25
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pop r31
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pop r30
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pop r24
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pop r23
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pop r22
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pop r21
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pop r20
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pop r19
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NOT_ENABLE:
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pop r18
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out SREG,r18
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pop r18
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reti
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.endfunc
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