Add all documented 6502 opcodes.
This commit is contained in:
edmccard
parent
c5fb366184
commit
0e330f8285
550
src/cpu6502.d
550
src/cpu6502.d
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@ -1,3 +1,26 @@
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/+
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+ cpu6502.d
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+
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+ Copyright: 2012 Ed McCardell, 2007 Gerald Stocker
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+
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+ This file is part of twoapple-reboot.
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+
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+ twoapple-reboot is free software; you can redistribute it and/or modify
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+ it under the terms of the GNU General Public License as published by
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+ the Free Software Foundation; either version 2 of the License, or
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+ (at your option) any later version.
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+
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+ twoapple-reboot is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ GNU General Public License for more details.
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+
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+ You should have received a copy of the GNU General Public License
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+ along with twoapple-reboot; if not, write to the Free Software
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+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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+/
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module cpu6502;
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@ -78,12 +101,6 @@ static if (!__traits(compiles, { bool b = opArray; })) enum opArray = 0;
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static assert (versionCheck);
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// This needs to be before any mixins which call any CTFE functions
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// that make use of these constants.
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enum { IMP, IMM, ZP, ZPX, ZPY, IZX, IZY, ABS, ABX, ABY, IND, REL,
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ZPI, ABI, NP1, NP8, KIL }
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final class Cpu(string chip, bool strict, bool cumulative)
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{
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static assert(chip == "6502" || chip == "65C02" || chip == "65c02");
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@ -122,13 +139,11 @@ final class Cpu(string chip, bool strict, bool cumulative)
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ubyte A, X, Y, S;
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ushort PC;
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// The status flags.
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ubyte N, Z;
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bool V, D, I, C;
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static if (opArray)
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{
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mixin(OpArrayDef());
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}
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static if (opArray) { mixin(OpArrayDef()); }
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// TODO: other methods for stopping cpu
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bool keepRunning;
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@ -192,10 +207,6 @@ enum ushort IRQ_VECTOR = 0xFFFE;
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private:
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version(OpFunctions) mixin(OpBodies("6502", vStrict, vCumulative));
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version(OpFunctions) mixin(OpBodies("65C02", vStrict, vCumulative));
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string OpArrayDef()
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{
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version(OpDelegates)
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@ -243,6 +254,18 @@ string OpBodies(string chip, bool strict, bool cumulative)
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If!(cumulative)("int cycles = 1;\n") ~
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OpBody(op, chip, strict, cumulative) ~ "}\n";
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}
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/+
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foreach (op; 13..256)
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version(OpDelegates)
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ret ~= "final void opcode_" ~ Hex2(op) ~ "()\n{\n" ~
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If!(cumulative)("int cycles = 1;\n") ~
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"" ~ "}\n";
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version(OpFunctions)
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ret ~= "void opcode_" ~ Hex2(op) ~
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"(T)(T cpu) if (is" ~ chip ~ "!T)\n{\n" ~
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If!(cumulative)("int cycles = 1;\n") ~
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"" ~ "}\n";
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+/
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return ret;
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}
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}
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@ -308,7 +331,8 @@ string OpBody(int op, string chip, bool s, bool c)
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return Jump(op, chip, s, c) ~
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Done(c);
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case "KIL":
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return "";
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return Attr("PC") ~ "--;\n" ~
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Done(c);
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case "BPL":
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return Branch("!(" ~ Attr("N") ~ " & 0x80)", nmos, s, c) ~
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Done(c);
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@ -337,82 +361,96 @@ string OpBody(int op, string chip, bool s, bool c)
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return Branch("!" ~ Attr("Z"), nmos, s, c) ~
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Done(c);
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case "CLC":
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return AddrImplied(s, c) ~
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return AddrIMP(s, c) ~
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ClearFlag("C") ~
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Done(c);
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case "SEC":
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return AddrImplied(s, c) ~
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return AddrIMP(s, c) ~
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SetFlag("C") ~
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Done(c);
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case "CLI":
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return AddrImplied(s, c) ~
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return AddrIMP(s, c) ~
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ClearFlag("I") ~
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Done(c);
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case "SEI":
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return AddrImplied(s, c) ~
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return AddrIMP(s, c) ~
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SetFlag("I") ~
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Done(c);
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case "CLV":
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return AddrImplied(s, c) ~
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return AddrIMP(s, c) ~
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ClearFlag("V") ~
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Done(c);
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case "CLD":
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return AddrImplied(s, c) ~
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return AddrIMP(s, c) ~
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ClearFlag("D") ~
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Done(c);
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case "SED":
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return AddrImplied(s, c) ~
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return AddrIMP(s, c) ~
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SetFlag("D") ~
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Done(c);
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case "NOP":
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return ""; // address modes
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return Nop(op, chip, s, c) ~
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Done(c);
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case "TAX":
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return "";
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return Transfer(op, "A", "X", s, c) ~
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Done(c);
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case "TXA":
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return "";
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return Transfer(op, "X", "A", s, c) ~
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Done(c);
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case "TAY":
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return "";
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return Transfer(op, "A", "Y", s, c) ~
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Done(c);
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case "TYA":
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return "";
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return Transfer(op, "Y", "A", s, c) ~
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Done(c);
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case "TSX":
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return "";
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return Transfer(op, "S", "X", s, c) ~
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Done(c);
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case "TXS":
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return "";
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return Transfer(op, "X", "S", s, c) ~
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Done(c);
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case "DEX":
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return DecReg("X", s, c) ~
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return AddrIMP(s, c) ~
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Dec(Attr("X")) ~
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Done(c);
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case "DEY":
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return DecReg("Y", s, c) ~
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return AddrIMP(s, c) ~
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Dec(Attr("Y")) ~
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Done(c);
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case "INX":
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return IncReg("X", s, c) ~
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return AddrIMP(s, c) ~
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Inc(Attr("X")) ~
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Done(c);
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case "INY":
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return IncReg("Y", s, c) ~
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return AddrIMP(s, c) ~
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Inc(Attr("Y")) ~
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Done(c);
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case "PHP":
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return AddrImplied(s, c) ~
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return AddrIMP(s, c) ~
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Push(Attr("statusToByte()"), s, c) ~
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Done(c);
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case "PLP":
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return AddrImplied(s, c) ~
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return AddrIMP(s, c) ~
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PullStatus(s, c) ~
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Done(c);
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case "PLA":
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return AddrImplied(s, c) ~
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PullInto(Attr("A"), s, c) ~
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SetNZ(Attr("A")) ~
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return PullReg("A", s, c) ~
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Done(c);
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case "PLX":
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return "";
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return PullReg("X", s, c) ~
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Done(c);
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case "PLY":
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return "";
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return PullReg("Y", s, c) ~
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Done(c);
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case "PHA":
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return "";
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return PushReg("A", s, c) ~
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Done(c);
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case "PHX":
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return "";
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return PushReg("X", s, c) ~
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Done(c);
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case "PHY":
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return "";
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return PushReg("Y", s, c) ~
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Done(c);
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case "LDA":
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return Load(op, "A", chip, s, c) ~
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Done(c);
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@ -434,7 +472,8 @@ string OpBody(int op, string chip, bool s, bool c)
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case "STZ":
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return "";
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case "BIT":
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return ""; // address modes
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return Bit(op, chip, s, c) ~
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Done(c);
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case "CMP":
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return Compare(op, "A", chip, s, c) ~
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Done(c);
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@ -460,23 +499,35 @@ string OpBody(int op, string chip, bool s, bool c)
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return Sub(op, chip, s, c) ~
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Done(c);
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case "ASL":
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return ""; // n/c (op, cyc)
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if (op == 0x0a)
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return AddrIMP(s, c) ~ ShiftLeft(Attr("A")) ~ Done(c);
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else
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return RMW(op, ShiftLeft("data"), chip, s, c) ~ Done(c);
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case "ROL":
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return ""; // n/c (op, cyc)
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if (op == 0x2a)
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return AddrIMP(s, c) ~ RotateLeft(Attr("A")) ~ Done(c);
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else
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return RMW(op, RotateLeft("data"), chip, s, c) ~ Done(c);
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case "LSR":
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return ""; // n/c (op, cyc)
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if (op == 0x4a)
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return AddrIMP(s, c) ~ ShiftRight(Attr("A")) ~ Done(c);
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else
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return RMW(op, ShiftRight("data"), chip, s, c) ~ Done(c);
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case "ROR":
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return ""; // n/c (op, cyc)
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if (op == 0x6a)
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return AddrIMP(s, c) ~ ShiftRight(Attr("A")) ~ Done(c);
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else
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return RMW(op, RotateRight("data"), chip, s, c) ~ Done(c);
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case "INC":
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if (op == 0x1a)
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return IncReg("A", s, c) ~ Done(c);
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return AddrIMP(s, c) ~ Inc(Attr("A")) ~ Done(c);
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else
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return RMW(op, "data++;\n", chip, s, c) ~ Done(c);
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return RMW(op, Inc("data"), chip, s, c) ~ Done(c);
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case "DEC":
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if (op == 0x3a)
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return DecReg("A", s, c) ~ Done(c);
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return AddrIMP(s, c) ~ Dec(Attr("A")) ~ Done(c);
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else
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return RMW(op, "data--;\n", chip, s, c) ~ Done(c);
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return RMW(op, Dec("data"), chip, s, c) ~ Done(c);
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case "TRB":
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return "";
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case "TSB":
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@ -521,52 +572,116 @@ string OpBody(int op, string chip, bool s, bool c)
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}
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string AddrImmediate(bool s, bool c)
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string AddrIMM(bool s, bool c)
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{
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return Local("ushort", "address") ~ " = " ~ Attr("PC") ~ "++;\n";
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return Local("ushort") ~ "address = " ~ Attr("PC") ~ "++;\n";
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}
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string AddrImplied(bool s, bool c)
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string AddrIMP(bool s, bool c)
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{
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return Peek(Attr("PC"), s, c);
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}
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string AddrZP(bool s, bool c)
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{
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return ReadOp(Local("ushort", "address"), c);
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}
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string AddrAbsoluteIdx(int op, string reg, string chip, bool s, bool c)
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string AddrZPXY(string reg, string chip, bool s, bool c)
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{
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bool nmos = (chip == "6502");
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return ReadOp(Local("ushort", "base"), c) ~
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If!(nmos)(
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Peek("base", s, c),
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Peek(Attr("PC"), s, c)) ~
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Local("ushort") ~
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"address = cast(ubyte)(base + " ~ Attr(reg) ~ ");\n";
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}
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string AddrIZX(string chip, bool s, bool c)
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{
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bool nmos = (chip == "6502");
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return ReadOp(Local("ushort", "base"), c) ~
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If!(nmos)(
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Peek("base", s, c),
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Peek(Attr("PC"), s, c)) ~
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ReadWordZP("ushort", "address", "base + " ~ Attr("X"), c);
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}
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string AddrIZY(int op, string chip, bool s, bool c)
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{
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int exCyc = opExCyc(op, chip);
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bool nmos = (chip == "6502");
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return ReadOp("ubyte vector", c) ~
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ReadWordZP("ushort", "base", "vector", c) ~
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Local("ushort") ~
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"address = cast(ushort)(base + " ~ Attr("Y") ~ ");\n" ~
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CheckShortcut("address", Attr("PC"),
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exCyc, nmos, s, c);
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}
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string AddrABS(bool s, bool c)
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{
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return ReadWordOp("ushort", "address", c);
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}
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string AddrABXY(int op, string reg, string chip, bool s, bool c)
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{
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bool nmos = (chip == "6502");
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int exCyc = opExCyc(op, chip);
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string IDX = Attr(reg);
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return ReadWordOpLocal("ushort", "base", c) ~
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Local("ushort","address")~" = cast(ushort)(base + " ~ IDX ~ ");\n" ~
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"ushort guess = (base & 0xFF00) | cast(ubyte)address;\n" ~
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"if (guess != address)\n{\n" ~
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If!(nmos)(Peek("guess", s, c), Peek(Attr("PC"), s, c)) ~
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return ReadWordOp("ushort", "base", c) ~
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Local("ushort") ~ "address = cast(ushort)(base + " ~ IDX ~ ");\n" ~
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CheckShortcut("address", Attr("PC"), exCyc, nmos, s, c);
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}
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string AddrZPI(bool s, bool c)
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{
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return ReadOp(Local("ushort", "base"), c) ~
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ReadWordZP("ushort", "address", "base", c);
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}
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string Branch(string check, bool nmos, bool s, bool c)
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{
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string PC = Attr("PC");
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return ReadOp(Local("ubyte", "op1"), c) ~
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"if (" ~ check ~ ")\n{\n" ~
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Peek(PC, s, c) ~
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Local("ushort", "base") ~ " = " ~ PC ~ ";\n" ~
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PC ~ " = cast(ushort)(" ~ PC ~ " + cast(byte)op1);\n" ~
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CheckShortcut(Attr("PC"), "base", 0, nmos, s, c) ~
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"}\n";
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}
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string CheckShortcut(string addr, string pc, int exCyc, bool nmos, bool s,
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bool c)
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{
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return "ushort guess = (base & 0xFF00) | cast(ubyte)" ~ addr ~ ";\n" ~
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"if (guess != " ~ addr ~ ")\n{\n" ~
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If!(nmos)(Peek("guess", s, c),
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Peek(pc, s, c)) ~
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"}\n" ~
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If!(exCyc)("else\n{\n" ~ Peek("address", s, c) ~ "}\n");
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}
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string Branch(string check, bool nmos, bool s, bool c)
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string Nop(int op, string chip, bool s, bool c)
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{
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string PC = Attr("PC");
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return ReadInto(Local("ubyte", "op1"), PC, c) ~
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IncPC() ~
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"if (" ~ check ~ ")\n{\n" ~
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Peek(PC, s, c) ~
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Local("ushort", "base") ~ " = " ~ PC ~ ";\n" ~
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PC ~ " = cast(ushort)(" ~ PC ~ " + cast(byte)op1);\n" ~
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"ushort guess = (base & 0xFF00) | cast(ubyte)" ~ PC ~ ";\n" ~
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"if (guess != " ~ PC ~ ")\n{\n" ~
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If!(nmos)(Peek("guess", s, c), Peek("base", s, c)) ~
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"}\n}\n";
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auto mode = opMode(op, chip);
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if (mode == IMP || mode == NP1 || mode == NP8)
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return Address(op, chip, s, c);
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else
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return Address(op, chip, s, c) ~
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Peek("address", true, c);
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}
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string Break(bool s, bool c)
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{
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return AddrImplied(s, c) ~
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return AddrIMP(s, c) ~
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IncPC() ~
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PushPC(s, c) ~
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Push(Attr("statusToByte()"), s, c) ~
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@ -577,11 +692,9 @@ string Break(bool s, bool c)
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string RetSub(bool s, bool c)
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{
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string PC = Attr("PC");
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return AddrImplied(s, c) ~
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return AddrIMP(s, c) ~
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PullPC(s, c) ~
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Peek(PC, s, c) ~
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Peek(Attr("PC"), s, c) ~
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IncPC();
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}
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@ -590,22 +703,149 @@ string JumpSub(bool s, bool c)
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{
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string PC = Attr("PC");
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return ReadInto(Local("ushort", "address"), PC ~ "++", c) ~
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return ReadOp(Local("ushort", "address"), c) ~
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Peek("0x0100 + " ~ Attr("S"), s, c) ~
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PushPC(s, c) ~
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PreAccess(c) ~
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"address |= (" ~ ReadRaw(PC ~ "++") ~ " << 8);\n" ~
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PreAccess(c) ~ "address |= (" ~ ReadRaw(PC ~ "++") ~ " << 8);\n" ~
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PC ~ " = address;\n";
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}
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string Jump(int op, string chip, bool s, bool c)
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{
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bool nmos = (chip == "6502");
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string PC = Attr("PC");
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if (op == 0x4c)
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return Address(op, chip, s, c) ~
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Attr("PC") ~ " = address;\n";
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else
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||||
PC ~ " = address;\n";
|
||||
else if (op == 0x6c)
|
||||
return ReadWordOp("ushort", "base", c) ~
|
||||
If!(nmos)(
|
||||
"",
|
||||
Peek(PC, s, c)) ~
|
||||
ReadWordBasic(PC, "base",
|
||||
If!(nmos)(
|
||||
"(base & 0xFF00) | cast(ubyte)(base + 1)",
|
||||
"cast(ushort)(base + 1)"), c);
|
||||
else if (op == 0x7c)
|
||||
return ReadWordOp("ushort", "base", c) ~
|
||||
Peek(PC, s, c) ~
|
||||
ReadWord(PC, "cast(ushort)(base + " ~ Attr("X") ~ ")", c);
|
||||
return "";
|
||||
}
|
||||
|
||||
|
||||
string ReadInto(string var, string action, string addr, bool c)
|
||||
{
|
||||
return PreAccess(c) ~
|
||||
var ~ " " ~ action ~ " " ~ ReadRaw("(" ~ addr ~ ")") ~ ";\n";
|
||||
}
|
||||
|
||||
string ReadInto(string var, string addr, bool c)
|
||||
{
|
||||
return ReadInto(var, "=", addr, c);
|
||||
}
|
||||
|
||||
string ReadOp(string var, bool c)
|
||||
{
|
||||
return ReadInto(var, Attr("PC") ~ "++", c);
|
||||
}
|
||||
|
||||
string ReadRaw(string addr)
|
||||
{
|
||||
return Attr("memory") ~ ".read(" ~ addr ~")";
|
||||
}
|
||||
|
||||
string ReadWordBasic(string type, string var, string addr1, string addr2,
|
||||
bool c)
|
||||
{
|
||||
return PreAccess(c) ~
|
||||
Local(type, var) ~ " = " ~ ReadRaw(addr1) ~ ";\n" ~
|
||||
PreAccess(c) ~
|
||||
var ~ " |= ((" ~ ReadRaw(addr2) ~ ") << 8);\n";
|
||||
}
|
||||
|
||||
string ReadWordBasic(string var, string addr1, string addr2, bool c)
|
||||
{
|
||||
return ReadWordBasic("", var, addr1, addr2, c);
|
||||
}
|
||||
|
||||
string ReadWord(string type, string var, string addr, bool c)
|
||||
{
|
||||
return ReadWordBasic(type, var, addr, "cast(ushort)(" ~ addr ~ " + 1)", c);
|
||||
}
|
||||
|
||||
string ReadWord(string var, string addr, bool c)
|
||||
{
|
||||
return ReadWord("", var, addr, c);
|
||||
}
|
||||
|
||||
string ReadWordZP(string type, string var, string addr, bool c)
|
||||
{
|
||||
return ReadWordBasic(type, var, "cast(ubyte)( " ~ addr ~ ")",
|
||||
"cast(ubyte)(" ~ addr ~ " + 1)", c);
|
||||
}
|
||||
|
||||
string ReadWordZP(string var, string addr, bool c)
|
||||
{
|
||||
return ReadWordZP("", var, addr, c);
|
||||
}
|
||||
|
||||
string ReadWordOp(string type, string var, bool c)
|
||||
{
|
||||
string PC = Attr("PC");
|
||||
|
||||
return ReadWordBasic(type, var, PC ~ "++", PC ~ "++", c);
|
||||
}
|
||||
|
||||
string ReadWordOp(string var, bool c)
|
||||
{
|
||||
return ReadWordOp("", var, c);
|
||||
}
|
||||
|
||||
|
||||
string Local(string type)
|
||||
{
|
||||
version(OpSwitch)
|
||||
return "";
|
||||
else version(OpNestedSwitch)
|
||||
return "";
|
||||
else
|
||||
return type ~ " ";
|
||||
}
|
||||
|
||||
string Local(string type, string var)
|
||||
{
|
||||
version(OpSwitch)
|
||||
return var;
|
||||
else version(OpNestedSwitch)
|
||||
return var;
|
||||
else
|
||||
return type ~ " " ~ var;
|
||||
}
|
||||
|
||||
|
||||
string Transfer(int op, string source, string dest, bool s, bool c)
|
||||
{
|
||||
return AddrIMP(s, c) ~
|
||||
Attr(dest) ~ " = " ~ Attr(source) ~ ";\n" ~
|
||||
((op != 0x9a) ? SetNZ(Attr(dest)) : "");
|
||||
}
|
||||
|
||||
|
||||
string PullReg(string reg, bool s, bool c)
|
||||
{
|
||||
return AddrIMP(s, c) ~
|
||||
PullInto(Attr(reg), s, c) ~
|
||||
SetNZ(Attr(reg));
|
||||
}
|
||||
|
||||
|
||||
string PushReg(string reg, bool s, bool c)
|
||||
{
|
||||
return AddrIMP(s, c) ~
|
||||
Push(Attr(reg), s, c);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -633,10 +873,23 @@ string Compare(int op, string reg, string chip, bool s, bool c)
|
|||
}
|
||||
|
||||
|
||||
string Bit(int op, string chip, bool s, bool c)
|
||||
{
|
||||
bool notImm = (opMode(op, chip) != IMM);
|
||||
|
||||
return Address(op, chip, s, c) ~
|
||||
ReadInto(Local("ubyte", "data"), "address", c) ~
|
||||
If!(notImm)(
|
||||
Attr("N") ~ " = data;\n" ~
|
||||
Attr("V") ~ " = ((data & 0x40) != 0);\n") ~
|
||||
Attr("Z") ~ " = (" ~ Attr("A") ~ " & data);\n";
|
||||
}
|
||||
|
||||
|
||||
string Logic(int op, string action, string chip, bool s, bool c)
|
||||
{
|
||||
return Address(op, chip, s, c) ~
|
||||
ReadInto(Attr("A"), "address", c, action) ~
|
||||
ReadInto(Attr("A"), action, "address", c) ~
|
||||
SetNZ(Attr("A"));
|
||||
}
|
||||
|
||||
|
|
@ -646,9 +899,9 @@ string Add(int op, string chip, bool s, bool c)
|
|||
return Address(op, chip, s, c) ~
|
||||
ReadInto(Local("ubyte", "data"), "address", c) ~
|
||||
"if (" ~ Attr("D") ~ ")\n{\n" ~
|
||||
DecAdd(chip, s, c) ~
|
||||
DecAdd(chip, s, c) ~
|
||||
"}\nelse\n{\n" ~
|
||||
HexAdd(chip, s, c) ~
|
||||
HexAdd(chip, s, c) ~
|
||||
"}\n";
|
||||
}
|
||||
|
||||
|
|
@ -692,9 +945,9 @@ string Sub(int op, string chip, bool s, bool c)
|
|||
return Address(op, chip, s, c) ~
|
||||
ReadInto(Local("ubyte", "data"), "address", c) ~
|
||||
"if (" ~ Attr("D") ~ ")\n{\n" ~
|
||||
DecSub(chip, s, c) ~
|
||||
DecSub(chip, s, c) ~
|
||||
"}\nelse\n{\n" ~
|
||||
HexSub(chip, s, c) ~
|
||||
HexSub(chip, s, c) ~
|
||||
"}\n";
|
||||
}
|
||||
|
||||
|
|
@ -751,22 +1004,50 @@ string DecSubCMOS(bool s, bool c)
|
|||
}
|
||||
|
||||
|
||||
string IncReg(string reg, bool s, bool c)
|
||||
string Inc(string val)
|
||||
{
|
||||
return AddrImplied(s, c) ~
|
||||
Attr(reg) ~ "++;\n" ~
|
||||
SetNZ(Attr(reg));
|
||||
return val ~ "++;\n" ~
|
||||
SetNZ(val);
|
||||
}
|
||||
|
||||
|
||||
string DecReg(string reg, bool s, bool c)
|
||||
string Dec(string val)
|
||||
{
|
||||
return AddrImplied(s, c) ~
|
||||
Attr(reg) ~ "--;\n" ~
|
||||
SetNZ(Attr(reg));
|
||||
return val ~ "--;\n" ~
|
||||
SetNZ(val);
|
||||
}
|
||||
|
||||
|
||||
string ShiftLeft(string val)
|
||||
{
|
||||
return Attr("C") ~ " = (" ~ val ~ " > 0x7F);\n" ~
|
||||
SetNZ(val ~ " = cast(ubyte)(" ~ val ~ " << 1)");
|
||||
}
|
||||
|
||||
string RotateLeft(string val)
|
||||
{
|
||||
string C = Attr("C");
|
||||
|
||||
return "auto oldC = " ~ C ~ ";\n" ~
|
||||
C ~ " = (" ~ val ~ " > 0x7f);\n" ~
|
||||
SetNZ(val ~ " = cast(ubyte)(" ~ val ~ " << 1 | (oldC ? 1 : 0))");
|
||||
}
|
||||
|
||||
string ShiftRight(string val)
|
||||
{
|
||||
return Attr("C") ~ " = ((" ~ val ~ " & 0x01) != 0);\n" ~
|
||||
SetNZ(val ~ " = " ~ val ~ " >> 1");
|
||||
}
|
||||
|
||||
string RotateRight(string val)
|
||||
{
|
||||
string C = Attr("C");
|
||||
|
||||
return "auto oldC = " ~ C ~ ";\n" ~
|
||||
C ~ " = ((" ~ val ~ " & 0x01) != 0);\n" ~
|
||||
SetNZ(val ~ " = (" ~ val ~ " >> 1 | (oldC ? 0x80 : 0))");
|
||||
}
|
||||
|
||||
string RMW(int op, string action, string chip, bool s, bool c)
|
||||
{
|
||||
bool nmos = (chip == "6502");
|
||||
|
|
@ -776,7 +1057,6 @@ string RMW(int op, string action, string chip, bool s, bool c)
|
|||
If!(nmos)(Poke("address", "data", s, c),
|
||||
Peek("address", s, c)) ~
|
||||
action ~
|
||||
SetNZ("data") ~
|
||||
Write("address", "data", c);
|
||||
}
|
||||
|
||||
|
|
@ -789,35 +1069,35 @@ string Address(int op, string chip, bool s, bool c)
|
|||
final switch (opMode(op, chip))
|
||||
{
|
||||
case IMP:
|
||||
return AddrImplied(s, c);
|
||||
return AddrIMP(s, c);
|
||||
case IMM:
|
||||
return AddrImmediate(s, c);
|
||||
return AddrIMM(s, c);
|
||||
case ZP:
|
||||
return Local("ushort", "address") ~ " = 0;";
|
||||
return AddrZP(s, c);
|
||||
case ZPX:
|
||||
return Local("ushort", "address") ~ " = 0;";
|
||||
return AddrZPXY("X", chip, s, c);
|
||||
case ZPY:
|
||||
return Local("ushort", "address") ~ " = 0;";
|
||||
return AddrZPXY("Y", chip, s, c);
|
||||
case IZX:
|
||||
return Local("ushort", "address") ~ " = 0;";
|
||||
return AddrIZX(chip, s, c);
|
||||
case IZY:
|
||||
return Local("ushort", "address") ~ " = 0;";
|
||||
return AddrIZY(op, chip, s, c);
|
||||
case ABS:
|
||||
return ReadWordOpLocal("ushort", "address", c);
|
||||
return AddrABS(s, c);
|
||||
case ABX:
|
||||
return AddrAbsoluteIdx(op, "X", chip, s, c);
|
||||
return AddrABXY(op, "X", chip, s, c);
|
||||
case ABY:
|
||||
return AddrAbsoluteIdx(op, "Y", chip, s, c);
|
||||
return AddrABXY(op, "Y", chip, s, c);
|
||||
case IND:
|
||||
return Local("ushort", "address") ~ " = 0;";
|
||||
case REL:
|
||||
return Local("ushort", "address") ~ " = 0;";
|
||||
case ZPI:
|
||||
return Local("ushort", "address") ~ " = 0;";
|
||||
return AddrZPI(s, c);
|
||||
case ABI:
|
||||
return Local("ushort", "address") ~ " = 0;";
|
||||
case NP1:
|
||||
return Local("ushort", "address") ~ " = 0;";
|
||||
return "";
|
||||
case NP8:
|
||||
return Local("ushort", "address") ~ " = 0;";
|
||||
case KIL:
|
||||
|
|
@ -845,44 +1125,12 @@ string Poke(string addr, string val, bool strict, bool cumulative)
|
|||
Attr("memory") ~ ".write(" ~ addr ~ ", " ~ val ~ ");\n");
|
||||
}
|
||||
|
||||
string ReadInto(string var, string addr, bool c, string action = "=")
|
||||
{
|
||||
return PreAccess(c) ~
|
||||
var ~ " " ~ action ~ " " ~ ReadRaw("(" ~ addr ~ ")") ~ ";\n";
|
||||
}
|
||||
|
||||
string ReadRaw(string addr)
|
||||
{
|
||||
return Attr("memory") ~ ".read(" ~ addr ~")";
|
||||
}
|
||||
|
||||
string Write(string addr, string val, bool cumulative)
|
||||
{
|
||||
return PreAccess(cumulative) ~
|
||||
Attr("memory") ~ ".write(" ~ addr ~ ", " ~ val ~ ");\n";
|
||||
}
|
||||
|
||||
string ReadWord(string var, string addr, bool c)
|
||||
{
|
||||
return PreAccess(c) ~
|
||||
var ~ " = " ~ ReadRaw(addr) ~ ";\n" ~
|
||||
PreAccess(c) ~
|
||||
var ~ " |= (" ~ ReadRaw("cast(ushort)((" ~ addr ~ ") + 1)") ~
|
||||
" << 8);\n";
|
||||
}
|
||||
|
||||
string ReadWordOpLocal(string type, string var, bool c)
|
||||
{
|
||||
string PC = Attr("PC");
|
||||
|
||||
return PreAccess(c) ~
|
||||
Local(type, var) ~ " = " ~ ReadRaw(PC ~ "++") ~ ";\n" ~
|
||||
PreAccess(c) ~
|
||||
var ~ " |= (" ~ ReadRaw(PC ~ "++") ~
|
||||
" << 8);\n";
|
||||
}
|
||||
|
||||
|
||||
string IncPC()
|
||||
{
|
||||
return "++" ~ Attr("PC") ~ ";\n";
|
||||
|
|
@ -973,17 +1221,6 @@ string Attr(string var)
|
|||
}
|
||||
|
||||
|
||||
string Local(string type, string var)
|
||||
{
|
||||
version(OpSwitch)
|
||||
return var;
|
||||
else version(OpNestedSwitch)
|
||||
return var;
|
||||
else
|
||||
return type ~ " " ~ var;
|
||||
}
|
||||
|
||||
|
||||
string HiByte(string var)
|
||||
{
|
||||
return var ~ " >> 8";
|
||||
|
|
@ -1103,6 +1340,9 @@ immutable OP_NAMES_65C02 = [
|
|||
|
||||
// Addressing modes.
|
||||
|
||||
enum { IMP, IMM, ZP, ZPX, ZPY, IZX, IZY, ABS, ABX, ABY, IND, REL,
|
||||
ZPI, ABI, NP1, NP8, KIL }
|
||||
|
||||
immutable ADDR_MODES_6502 = [
|
||||
IMP, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
||||
|
|
@ -1252,6 +1492,10 @@ string Fmt(string f, string[] p ...)
|
|||
}
|
||||
|
||||
|
||||
version(OpFunctions) mixin(OpBodies("6502", vStrict, vCumulative));
|
||||
version(OpFunctions) mixin(OpBodies("65C02", vStrict, vCumulative));
|
||||
|
||||
|
||||
//alias Cpu!("6502", false, false) T1;
|
||||
//alias Cpu!("6502", false, true) T2;
|
||||
//alias Cpu!("6502", true, false) T3;
|
||||
|
|
@ -1265,6 +1509,6 @@ string Fmt(string f, string[] p ...)
|
|||
void main()
|
||||
{
|
||||
import std.stdio;
|
||||
writeln(OpBody(0x9d, "6502", true, false));
|
||||
writeln(OpBody(0x11, "6502", true, false));
|
||||
}
|
||||
+/
|
||||
|
|
|
|||
|
|
@ -46,5 +46,12 @@ void main()
|
|||
0x4c, 0x09, 0x29, 0x49, 0x69, 0xe9, 0xc9, 0xe0, 0xc0, 0xa9,
|
||||
0xa2, 0xa0, 0x1d, 0x19, 0x3d, 0x39, 0x5d, 0x59, 0x7d, 0x79,
|
||||
0xfd, 0xf9, 0xdd, 0xd9, 0xde, 0xfe, 0xbd, 0xb9, 0x9d, 0x99,
|
||||
0xbe, 0xbc]);
|
||||
0xbe, 0xbc, 0x6c, 0x7c, 0xb2, 0x72, 0x32, 0xd2, 0x52, 0x12,
|
||||
0xf2, 0x92, 0xaa, 0x8a, 0xa8, 0x98, 0xba, 0x9a, 0x0a, 0x0e,
|
||||
0x1e, 0x48, 0x2c, 0x05, 0x25, 0x45, 0x65, 0xe5, 0xc5, 0xe4,
|
||||
0xc4, 0xc6, 0xe6, 0x06, 0x26, 0x46, 0x66, 0xa5, 0x85, 0xa6,
|
||||
0x86, 0xa4, 0x84, 0x24, 0x15, 0x35, 0x55, 0x75, 0xf5, 0xd5,
|
||||
0xd6, 0xf6, 0x16, 0x36, 0x56, 0x76, 0xb5, 0x95, 0xb6, 0x96,
|
||||
0xb4, 0x94, 0x01, 0x21, 0x41, 0x61, 0xe1, 0xc1, 0xa1, 0x81,
|
||||
0x11, 0x31, 0x51, 0x71, 0xf1, 0xd1, 0xb1, 0x91]);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue