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opindex interface to memory

This commit is contained in:
edmccard 2012-04-27 13:09:32 -04:00
parent 9691526fc1
commit aa55b972e0
4 changed files with 23 additions and 12 deletions
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8
src/cpu/ctfe_d6502.d
View File

@ -1053,7 +1053,7 @@ string ReadOp(string var)
string ReadRaw(string addr) string ReadRaw(string addr)
{ {
return Attr("memory") ~ ".read(" ~ addr ~")"; return Attr("memory") ~ "[" ~ addr ~"]";
} }
string ReadWordBasic(string type, string var, string addr1, string addr2) string ReadWordBasic(string type, string var, string addr1, string addr2)
@ -1106,20 +1106,20 @@ string Tick()
string Peek(string addr) string Peek(string addr)
{ {
return Tick() ~ return Tick() ~
If!(strict)(Attr("memory") ~ ".read(" ~ addr ~");\n"); If!(strict)(Attr("memory") ~ "[" ~ addr ~ "];\n");
} }
string Poke(string addr, string val) string Poke(string addr, string val)
{ {
return Tick() ~ return Tick() ~
If!(strict)( If!(strict)(
Attr("memory") ~ ".write(" ~ addr ~ ", " ~ val ~ ");\n"); Attr("memory") ~ "[" ~ addr ~ "] = " ~ val ~ ";\n");
} }
string Write(string addr, string val) string Write(string addr, string val)
{ {
return Tick() ~ return Tick() ~
Attr("memory") ~ ".write(" ~ addr ~ ", " ~ val ~ ");\n"; Attr("memory") ~ "[" ~ addr ~ "] = " ~ val ~ ";\n";
} }
string IncPC() string IncPC()

6
src/cpu/d6502.d
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@ -81,8 +81,8 @@ public:
final class Cpu(string chip, MEM, CLK) final class Cpu(string chip, MEM, CLK)
if (__traits(compiles, { if (__traits(compiles, {
MEM m; ubyte val; ushort addr; MEM m; ubyte val; ushort addr;
val = m.read(addr); val = m[addr];
m.write(addr, val); m[addr] = val;
CLK c; int cycles; CLK c; int cycles;
version(Cumulative) c.tick(cycles); version(Cumulative) c.tick(cycles);
else c.tick(); else c.tick();
@ -166,7 +166,7 @@ if (__traits(compiles, {
static if (_chip == "6502") { idelay = ndelay = false; } static if (_chip == "6502") { idelay = ndelay = false; }
version(Cumulative) { cycles = 1; } version(Cumulative) { cycles = 1; }
else { clock.tick(); } else { clock.tick(); }
opcode = memory.read(PC++); opcode = memory[PC++];
mixin(OpExecute(_chip)); mixin(OpExecute(_chip));
} while (keepRunning); } while (keepRunning);
} }

5
test/d6502/benchmark.d
View File

@ -13,7 +13,7 @@ final class BreakRunner
this.mem = &mem; this.mem = &mem;
} }
final ubyte read(ushort addr) final ubyte opIndex(ushort addr)
{ {
if (addr == 0xfffe) if (addr == 0xfffe)
{ {
@ -27,9 +27,10 @@ final class BreakRunner
else return mem.read(addr); else return mem.read(addr);
} }
final void write(ushort addr, ubyte val) final ubyte opIndexAssign(ubyte val, ushort addr)
{ {
mem.write(addr, val); mem.write(addr, val);
return val;
} }
static if (cumulative) { final void tick(int) {} } static if (cumulative) { final void tick(int) {} }

16
test/d6502/cpu.d
View File

@ -35,10 +35,7 @@ template isCMOS(T)
class TestIO class TestIO
{ {
ubyte delegate(ushort) dread; ubyte delegate(ushort) dread;
ubyte read(ushort addr) { return dread(addr); }
void delegate(ushort, ubyte) dwrite; void delegate(ushort, ubyte) dwrite;
void write(ushort addr, ubyte val) { dwrite(addr, val); }
static if (cumulative) static if (cumulative)
{ {
@ -50,6 +47,19 @@ class TestIO
void delegate() dtick; void delegate() dtick;
void tick() { dtick(); } void tick() { dtick(); }
} }
ubyte opIndex(ushort i1) const
{
auto addr = cast(ushort)i1;
return dread(addr);
}
ubyte opIndexAssign(ubyte val, ushort i1)
{
auto addr = cast(ushort)i1;
dwrite(addr, val);
return val;
}
} }