Split ctfe code from cpu code
This commit is contained in:
edmccard
parent
7e5c7131ef
commit
f3ebb822a6
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@ -5,7 +5,7 @@ LINK_OPTS = -L-lpthread -L-lGL -L-ldl -L-lX11 \
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-L-L$(GTKD) -L-lgtkd -L-lgtkdgl \
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-L-L$(DERELICT)/lib -L-lDerelictSDL -L-lDerelictUtil \
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ALL_SRC = $(shell find -name "*.d" \! -name "cpu6502.d")
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ALL_SRC = $(shell find -name "*.d" \! -path "./cpu/*")
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ALL_OBJS = $(ALL_SRC:%.d=%.o)
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all: ${ALL_OBJS}
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@ -1,52 +1,7 @@
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/+
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+ cpu6502.d
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+
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+ Copyright: 2012 Ed McCardell, 2007 Gerald Stocker
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+
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+ This file is part of twoapple-reboot.
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+
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+ twoapple-reboot is free software; you can redistribute it and/or modify
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+ it under the terms of the GNU General Public License as published by
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+ the Free Software Foundation; either version 2 of the License, or
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+ (at your option) any later version.
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+
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+ twoapple-reboot is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ GNU General Public License for more details.
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+
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+ You should have received a copy of the GNU General Public License
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+ along with twoapple-reboot; if not, write to the Free Software
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+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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+/
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module cpu.ctfe_d6502;
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module cpu6502;
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import std.array, std.format;
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enum Strict : bool
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{
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no, yes
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}
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enum Cumulative : bool
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{
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no, yes
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}
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template is6502(T)
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{
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enum is6502 = __traits(getMember, T, "_chip") == "6502";
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}
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template is65C02(T)
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{
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enum is65C02 = __traits(getMember, T, "_chip") == "65C02";
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}
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import cpu.data_d6502;
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// The following versions are mutually exclusive.
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@ -101,112 +56,6 @@ static if (!__traits(compiles, { bool b = opArray; })) enum opArray = 0;
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static assert (versionCheck);
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final class Cpu(string chip, bool strict, bool cumulative)
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{
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static assert(chip == "6502" || chip == "65C02" || chip == "65c02");
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enum _isCpu = true;
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enum _chip = (chip == "6502" ? "6502" : "65C02");
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enum _isStrict = strict;
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enum _isCumulative = cumulative;
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struct _Mem
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{
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// Reads a value from system memory.
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ubyte delegate(ushort addr) read;
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// Writes a value to system memory.
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void delegate(ushort addr, ubyte val) write;
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}
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_Mem memory;
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struct _Clock
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{
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static if (cumulative)
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/*
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* Updates the number of cycles executed. Called just
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* prior to the final read/write action of each opcode.
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*/
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void delegate(int cycles) tick;
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else
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/*
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* Increments the number of cycles executed. Called prior
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* to each read/write action.
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*/
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void delegate() tick;
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}
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_Clock clock;
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ubyte A, X, Y, S;
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ushort PC;
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// The status flags.
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ubyte N, Z;
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bool V, D, I, C;
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static if (opArray) { mixin(OpArrayDef()); }
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// TODO: other methods for stopping cpu
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bool keepRunning;
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this()
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{
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static if (opArray) mixin(OpArrayInit());
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}
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final void statusFromByte(ubyte p)
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{
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N = p;
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V = ((p & 0x40) != 0);
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D = ((p & 0x08) != 0);
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I = ((p & 0x04) != 0);
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Z = ((p & 0x02) ? 0 : 1);
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C = ((p & 0x01) != 0);
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}
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final ubyte statusToByte()
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{
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return (C ? 0x01 : 0) |
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((Z == 0) ? 0x02 : 0) |
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(I ? 0x04 : 0) |
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(D ? 0x08 : 0) |
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0x30 | // break and reserved both set
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(V ? 0x40 : 0) |
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(N & 0x80);
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}
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final void run(bool continuous)
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{
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keepRunning = continuous;
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// TODO debugging info?
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ubyte opcode;
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static if (!opArray)
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{
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static if (cumulative) { int cycles; }
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ubyte op1;
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ushort address, base;
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ubyte data;
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}
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do {
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static if (cumulative && !opArray)
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cycles = 1;
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// XXX figure out final cycle stuff
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static if (!cumulative)
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clock.tick();
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// XXX check signals, NMI/IRQ delays, etc.
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opcode = memory.read(PC++);
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mixin(OpExecute(_chip, strict, cumulative));
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} while (keepRunning);
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}
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version(OpDelegates) mixin (OpBodies(_chip, strict, cumulative));
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}
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enum ushort IRQ_VECTOR = 0xFFFE;
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private:
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string OpArrayDef()
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{
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version(OpDelegates)
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@ -1266,195 +1115,6 @@ int opExCyc(int op, string chip)
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}
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// Opcode names.
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immutable OP_NAMES_6502 = [
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"BRK", "ORA", "KIL", "SLO", "NOP", "ORA", "ASL", "SLO",
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"PHP", "ORA", "ASL", "ANC", "NOP", "ORA", "ASL", "SLO",
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"BPL", "ORA", "KIL", "SLO", "NOP", "ORA", "ASL", "SLO",
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"CLC", "ORA", "NOP", "SLO", "NOP", "ORA", "ASL", "SLO",
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"JSR", "AND", "KIL", "RLA", "BIT", "AND", "ROL", "RLA",
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"PLP", "AND", "ROL", "ANC", "BIT", "AND", "ROL", "RLA",
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"BMI", "AND", "KIL", "RLA", "NOP", "AND", "ROL", "RLA",
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"SEC", "AND", "NOP", "RLA", "NOP", "AND", "ROL", "RLA",
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"RTI", "EOR", "KIL", "SRE", "NOP", "EOR", "LSR", "SRE",
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"PHA", "EOR", "LSR", "ALR", "JMP", "EOR", "LSR", "SRE",
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"BVC", "EOR", "KIL", "SRE", "NOP", "EOR", "LSR", "SRE",
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"CLI", "EOR", "NOP", "SRE", "NOP", "EOR", "LSR", "SRE",
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"RTS", "ADC", "KIL", "RRA", "NOP", "ADC", "ROR", "RRA",
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"PLA", "ADC", "ROR", "ARR", "JMP", "ADC", "ROR", "RRA",
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"BVS", "ADC", "KIL", "RRA", "NOP", "ADC", "ROR", "RRA",
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"SEI", "ADC", "NOP", "RRA", "NOP", "ADC", "ROR", "RRA",
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"NOP", "STA", "NOP", "SAX", "STY", "STA", "STX", "SAX",
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"DEY", "NOP", "TXA", "XAA", "STY", "STA", "STX", "SAX",
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"BCC", "STA", "KIL", "AHX", "STY", "STA", "STX", "SAX",
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"TYA", "STA", "TXS", "TAS", "SHY", "STA", "SHX", "AHX",
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"LDY", "LDA", "LDX", "LAX", "LDY", "LDA", "LDX", "LAX",
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"TAY", "LDA", "TAX", "LAX", "LDY", "LDA", "LDX", "LAX",
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"BCS", "LDA", "KIL", "LAX", "LDY", "LDA", "LDX", "LAX",
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"CLV", "LDA", "TSX", "LAS", "LDY", "LDA", "LDX", "LAX",
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"CPY", "CMP", "NOP", "DCP", "CPY", "CMP", "DEC", "DCP",
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"INY", "CMP", "DEX", "AXS", "CPY", "CMP", "DEC", "DCP",
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"BNE", "CMP", "KIL", "DCP", "NOP", "CMP", "DEC", "DCP",
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"CLD", "CMP", "NOP", "DCP", "NOP", "CMP", "DEC", "DCP",
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"CPX", "SBC", "NOP", "ISC", "CPX", "SBC", "INC", "ISC",
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"INX", "SBC", "NOP", "SBC", "CPX", "SBC", "INC", "ISC",
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"BEQ", "SBC", "KIL", "ISC", "NOP", "SBC", "INC", "ISC",
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"SED", "SBC", "NOP", "ISC", "NOP", "SBC", "INC", "ISC"
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];
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immutable OP_NAMES_65C02 = [
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"BRK", "ORA", "NOP", "NOP", "TSB", "ORA", "ASL", "NOP",
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"PHP", "ORA", "ASL", "NOP", "TSB", "ORA", "ASL", "NOP",
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"BPL", "ORA", "ORA", "NOP", "TRB", "ORA", "ASL", "NOP",
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"CLC", "ORA", "INC", "NOP", "TRB", "ORA", "ASL", "NOP",
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"JSR", "AND", "NOP", "NOP", "BIT", "AND", "ROL", "NOP",
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"PLP", "AND", "ROL", "NOP", "BIT", "AND", "ROL", "NOP",
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"BMI", "AND", "AND", "NOP", "BIT", "AND", "ROL", "NOP",
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"SEC", "AND", "DEC", "NOP", "BIT", "AND", "ROL", "NOP",
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"RTI", "EOR", "NOP", "NOP", "NOP", "EOR", "LSR", "NOP",
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"PHA", "EOR", "LSR", "NOP", "JMP", "EOR", "LSR", "NOP",
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"BVC", "EOR", "EOR", "NOP", "NOP", "EOR", "LSR", "NOP",
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"CLI", "EOR", "PHY", "NOP", "NOP", "EOR", "LSR", "NOP",
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"RTS", "ADC", "NOP", "NOP", "STZ", "ADC", "ROR", "NOP",
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"PLA", "ADC", "ROR", "NOP", "JMP", "ADC", "ROR", "NOP",
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"BVS", "ADC", "ADC", "NOP", "STZ", "ADC", "ROR", "NOP",
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"SEI", "ADC", "PLY", "NOP", "JMP", "ADC", "ROR", "NOP",
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"BRA", "STA", "NOP", "NOP", "STY", "STA", "STX", "NOP",
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"DEY", "BIT", "TXA", "NOP", "STY", "STA", "STX", "NOP",
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"BCC", "STA", "STA", "NOP", "STY", "STA", "STX", "NOP",
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"TYA", "STA", "TXS", "NOP", "STZ", "STA", "STZ", "NOP",
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"LDY", "LDA", "LDX", "NOP", "LDY", "LDA", "LDX", "NOP",
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"TAY", "LDA", "TAX", "NOP", "LDY", "LDA", "LDX", "NOP",
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"BCS", "LDA", "LDA", "NOP", "LDY", "LDA", "LDX", "NOP",
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"CLV", "LDA", "TSX", "NOP", "LDY", "LDA", "LDX", "NOP",
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"CPY", "CMP", "NOP", "NOP", "CPY", "CMP", "DEC", "NOP",
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"INY", "CMP", "DEX", "NOP", "CPY", "CMP", "DEC", "NOP",
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"BNE", "CMP", "CMP", "NOP", "NOP", "CMP", "DEC", "NOP",
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"CLD", "CMP", "PHX", "NOP", "NOP", "CMP", "DEC", "NOP",
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"CPX", "SBC", "NOP", "NOP", "CPX", "SBC", "INC", "NOP",
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"INX", "SBC", "NOP", "NOP", "CPX", "SBC", "INC", "NOP",
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"BEQ", "SBC", "SBC", "NOP", "NOP", "SBC", "INC", "NOP",
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"SED", "SBC", "PLX", "NOP", "NOP", "SBC", "INC", "NOP"
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];
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// Addressing modes.
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enum { IMP, IMM, ZP, ZPX, ZPY, IZX, IZY, ABS, ABX, ABY, IND, REL,
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ZPI, ABI, NP1, NP8, KIL }
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immutable ADDR_MODES_6502 = [
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IMP, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
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IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
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REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
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IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
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ABS, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
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IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
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REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
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IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
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IMP, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
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IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
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REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
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IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
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IMP, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
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IMP, IMM, IMP, IMM, IND, ABS, ABS, ABS,
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REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
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IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
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IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
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IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
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REL, IZY, KIL, IZY, ZPX, ZPX, ZPY, ZPY,
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IMP, ABY, IMP, ABY, ABX, ABX, ABY, ABY,
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IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
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IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
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REL, IZY, KIL, IZY, ZPX, ZPX, ZPY, ZPY,
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IMP, ABY, IMP, ABY, ABX, ABX, ABY, ABY,
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IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
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IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
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REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
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IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
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IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
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IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
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REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
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IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX
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];
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immutable ADDR_MODES_65C02 = [
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IMP, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
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IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
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REL, IZY, ZPI, NP1, ZP, ZPX, ZPX, NP1,
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IMP, ABY, IMP, NP1, ABS, ABX, ABX, NP1,
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ABS, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
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IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
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REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
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IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1,
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IMP, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
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IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
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REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
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IMP, ABY, IMP, NP1, NP8, ABX, ABX, NP1,
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IMP, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
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IMP, IMM, IMP, NP1, IND, ABS, ABS, NP1,
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REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
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IMP, ABY, IMP, NP1, ABI, ABX, ABX, NP1,
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REL, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
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IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
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REL, IZY, ZPI, NP1, ZPX, ZPX, ZPY, NP1,
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IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1,
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IMM, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
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IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
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REL, IZY, ZPI, NP1, ZPX, ZPX, ZPY, NP1,
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IMP, ABY, IMP, NP1, ABX, ABX, ABY, NP1,
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IMM, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
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IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
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REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
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IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1,
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IMM, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
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IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
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REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
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IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1
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];
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// Page-crossing extra cycles.
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immutable EXTRA_CYCLES_6502 = [
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
];
|
||||
|
||||
immutable EXTRA_CYCLES_65C02 = [
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
];
|
||||
|
||||
|
||||
// Custom string formatting.
|
||||
|
||||
enum HEX_DIGITS = "0123456789abcdef";
|
||||
|
|
@ -1490,25 +1150,3 @@ string Fmt(string f, string[] p ...)
|
|||
}
|
||||
return ret ~ f[last..$];
|
||||
}
|
||||
|
||||
|
||||
version(OpFunctions) mixin(OpBodies("6502", vStrict, vCumulative));
|
||||
version(OpFunctions) mixin(OpBodies("65C02", vStrict, vCumulative));
|
||||
|
||||
|
||||
//alias Cpu!("6502", false, false) T1;
|
||||
//alias Cpu!("6502", false, true) T2;
|
||||
//alias Cpu!("6502", true, false) T3;
|
||||
//alias Cpu!("6502", true, true) T4;
|
||||
//alias Cpu!("65C02", false, false) T5;
|
||||
//alias Cpu!("65C02", false, true) T6;
|
||||
//alias Cpu!("65C02", true, false) T7;
|
||||
//alias Cpu!("65C02", true, true) T8;
|
||||
|
||||
/+
|
||||
void main()
|
||||
{
|
||||
import std.stdio;
|
||||
writeln(OpBody(0x11, "6502", true, false));
|
||||
}
|
||||
+/
|
||||
|
|
@ -0,0 +1,179 @@
|
|||
/+
|
||||
+ cpu/d6502.d
|
||||
+
|
||||
+ Copyright: 2012 Ed McCardell, 2007 Gerald Stocker
|
||||
+
|
||||
+ This file is part of twoapple-reboot.
|
||||
+
|
||||
+ twoapple-reboot is free software; you can redistribute it and/or modify
|
||||
+ it under the terms of the GNU General Public License as published by
|
||||
+ the Free Software Foundation; either version 2 of the License, or
|
||||
+ (at your option) any later version.
|
||||
+
|
||||
+ twoapple-reboot is distributed in the hope that it will be useful,
|
||||
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ GNU General Public License for more details.
|
||||
+
|
||||
+ You should have received a copy of the GNU General Public License
|
||||
+ along with twoapple-reboot; if not, write to the Free Software
|
||||
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
+/
|
||||
|
||||
|
||||
module cpu.d6502;
|
||||
|
||||
|
||||
import std.array, std.format;
|
||||
|
||||
import cpu.ctfe_d6502;
|
||||
|
||||
|
||||
enum Strict : bool
|
||||
{
|
||||
no, yes
|
||||
}
|
||||
|
||||
enum Cumulative : bool
|
||||
{
|
||||
no, yes
|
||||
}
|
||||
|
||||
|
||||
template is6502(T)
|
||||
{
|
||||
enum is6502 = __traits(getMember, T, "_chip") == "6502";
|
||||
}
|
||||
|
||||
template is65C02(T)
|
||||
{
|
||||
enum is65C02 = __traits(getMember, T, "_chip") == "65C02";
|
||||
}
|
||||
|
||||
|
||||
final class Cpu(string chip, bool strict, bool cumulative)
|
||||
{
|
||||
static assert(chip == "6502" || chip == "65C02" || chip == "65c02");
|
||||
enum _isCpu = true;
|
||||
enum _chip = (chip == "6502" ? "6502" : "65C02");
|
||||
enum _isStrict = strict;
|
||||
enum _isCumulative = cumulative;
|
||||
|
||||
struct _Mem
|
||||
{
|
||||
// Reads a value from system memory.
|
||||
ubyte delegate(ushort addr) read;
|
||||
|
||||
// Writes a value to system memory.
|
||||
void delegate(ushort addr, ubyte val) write;
|
||||
}
|
||||
_Mem memory;
|
||||
|
||||
struct _Clock
|
||||
{
|
||||
static if (cumulative)
|
||||
/*
|
||||
* Updates the number of cycles executed. Called just
|
||||
* prior to the final read/write action of each opcode.
|
||||
*/
|
||||
void delegate(int cycles) tick;
|
||||
else
|
||||
/*
|
||||
* Increments the number of cycles executed. Called prior
|
||||
* to each read/write action.
|
||||
*/
|
||||
void delegate() tick;
|
||||
}
|
||||
_Clock clock;
|
||||
|
||||
ubyte A, X, Y, S;
|
||||
ushort PC;
|
||||
|
||||
// The status flags.
|
||||
ubyte N, Z;
|
||||
bool V, D, I, C;
|
||||
|
||||
static if (opArray) { mixin(OpArrayDef()); }
|
||||
|
||||
// TODO: other methods for stopping cpu
|
||||
bool keepRunning;
|
||||
|
||||
this()
|
||||
{
|
||||
static if (opArray) mixin(OpArrayInit());
|
||||
}
|
||||
|
||||
final void statusFromByte(ubyte p)
|
||||
{
|
||||
N = p;
|
||||
V = ((p & 0x40) != 0);
|
||||
D = ((p & 0x08) != 0);
|
||||
I = ((p & 0x04) != 0);
|
||||
Z = ((p & 0x02) ? 0 : 1);
|
||||
C = ((p & 0x01) != 0);
|
||||
}
|
||||
|
||||
final ubyte statusToByte()
|
||||
{
|
||||
return (C ? 0x01 : 0) |
|
||||
((Z == 0) ? 0x02 : 0) |
|
||||
(I ? 0x04 : 0) |
|
||||
(D ? 0x08 : 0) |
|
||||
0x30 | // break and reserved both set
|
||||
(V ? 0x40 : 0) |
|
||||
(N & 0x80);
|
||||
}
|
||||
|
||||
final void run(bool continuous)
|
||||
{
|
||||
keepRunning = continuous;
|
||||
// TODO debugging info?
|
||||
ubyte opcode;
|
||||
static if (!opArray)
|
||||
{
|
||||
static if (cumulative) { int cycles; }
|
||||
ubyte op1;
|
||||
ushort address, base;
|
||||
ubyte data;
|
||||
}
|
||||
do {
|
||||
static if (cumulative && !opArray)
|
||||
cycles = 1;
|
||||
// XXX figure out final cycle stuff
|
||||
static if (!cumulative)
|
||||
clock.tick();
|
||||
// XXX check signals, NMI/IRQ delays, etc.
|
||||
opcode = memory.read(PC++);
|
||||
mixin(OpExecute(_chip, strict, cumulative));
|
||||
} while (keepRunning);
|
||||
}
|
||||
|
||||
version(OpDelegates) mixin (OpBodies(_chip, strict, cumulative));
|
||||
}
|
||||
|
||||
|
||||
enum ushort IRQ_VECTOR = 0xFFFE;
|
||||
|
||||
|
||||
private:
|
||||
|
||||
version(OpFunctions) mixin(OpBodies("6502", vStrict, vCumulative));
|
||||
version(OpFunctions) mixin(OpBodies("65C02", vStrict, vCumulative));
|
||||
|
||||
|
||||
//alias Cpu!("6502", false, false) T1;
|
||||
//alias Cpu!("6502", false, true) T2;
|
||||
//alias Cpu!("6502", true, false) T3;
|
||||
//alias Cpu!("6502", true, true) T4;
|
||||
//alias Cpu!("65C02", false, false) T5;
|
||||
//alias Cpu!("65C02", false, true) T6;
|
||||
//alias Cpu!("65C02", true, false) T7;
|
||||
//alias Cpu!("65C02", true, true) T8;
|
||||
|
||||
/+
|
||||
void main()
|
||||
{
|
||||
import std.stdio;
|
||||
writeln(OpBody(0x11, "6502", true, false));
|
||||
}
|
||||
+/
|
||||
|
|
@ -0,0 +1,190 @@
|
|||
module cpu.data_d6502;
|
||||
|
||||
|
||||
// Opcode names.
|
||||
immutable OP_NAMES_6502 = [
|
||||
"BRK", "ORA", "KIL", "SLO", "NOP", "ORA", "ASL", "SLO",
|
||||
"PHP", "ORA", "ASL", "ANC", "NOP", "ORA", "ASL", "SLO",
|
||||
"BPL", "ORA", "KIL", "SLO", "NOP", "ORA", "ASL", "SLO",
|
||||
"CLC", "ORA", "NOP", "SLO", "NOP", "ORA", "ASL", "SLO",
|
||||
"JSR", "AND", "KIL", "RLA", "BIT", "AND", "ROL", "RLA",
|
||||
"PLP", "AND", "ROL", "ANC", "BIT", "AND", "ROL", "RLA",
|
||||
"BMI", "AND", "KIL", "RLA", "NOP", "AND", "ROL", "RLA",
|
||||
"SEC", "AND", "NOP", "RLA", "NOP", "AND", "ROL", "RLA",
|
||||
"RTI", "EOR", "KIL", "SRE", "NOP", "EOR", "LSR", "SRE",
|
||||
"PHA", "EOR", "LSR", "ALR", "JMP", "EOR", "LSR", "SRE",
|
||||
"BVC", "EOR", "KIL", "SRE", "NOP", "EOR", "LSR", "SRE",
|
||||
"CLI", "EOR", "NOP", "SRE", "NOP", "EOR", "LSR", "SRE",
|
||||
"RTS", "ADC", "KIL", "RRA", "NOP", "ADC", "ROR", "RRA",
|
||||
"PLA", "ADC", "ROR", "ARR", "JMP", "ADC", "ROR", "RRA",
|
||||
"BVS", "ADC", "KIL", "RRA", "NOP", "ADC", "ROR", "RRA",
|
||||
"SEI", "ADC", "NOP", "RRA", "NOP", "ADC", "ROR", "RRA",
|
||||
"NOP", "STA", "NOP", "SAX", "STY", "STA", "STX", "SAX",
|
||||
"DEY", "NOP", "TXA", "XAA", "STY", "STA", "STX", "SAX",
|
||||
"BCC", "STA", "KIL", "AHX", "STY", "STA", "STX", "SAX",
|
||||
"TYA", "STA", "TXS", "TAS", "SHY", "STA", "SHX", "AHX",
|
||||
"LDY", "LDA", "LDX", "LAX", "LDY", "LDA", "LDX", "LAX",
|
||||
"TAY", "LDA", "TAX", "LAX", "LDY", "LDA", "LDX", "LAX",
|
||||
"BCS", "LDA", "KIL", "LAX", "LDY", "LDA", "LDX", "LAX",
|
||||
"CLV", "LDA", "TSX", "LAS", "LDY", "LDA", "LDX", "LAX",
|
||||
"CPY", "CMP", "NOP", "DCP", "CPY", "CMP", "DEC", "DCP",
|
||||
"INY", "CMP", "DEX", "AXS", "CPY", "CMP", "DEC", "DCP",
|
||||
"BNE", "CMP", "KIL", "DCP", "NOP", "CMP", "DEC", "DCP",
|
||||
"CLD", "CMP", "NOP", "DCP", "NOP", "CMP", "DEC", "DCP",
|
||||
"CPX", "SBC", "NOP", "ISC", "CPX", "SBC", "INC", "ISC",
|
||||
"INX", "SBC", "NOP", "SBC", "CPX", "SBC", "INC", "ISC",
|
||||
"BEQ", "SBC", "KIL", "ISC", "NOP", "SBC", "INC", "ISC",
|
||||
"SED", "SBC", "NOP", "ISC", "NOP", "SBC", "INC", "ISC"
|
||||
];
|
||||
|
||||
immutable OP_NAMES_65C02 = [
|
||||
"BRK", "ORA", "NOP", "NOP", "TSB", "ORA", "ASL", "NOP",
|
||||
"PHP", "ORA", "ASL", "NOP", "TSB", "ORA", "ASL", "NOP",
|
||||
"BPL", "ORA", "ORA", "NOP", "TRB", "ORA", "ASL", "NOP",
|
||||
"CLC", "ORA", "INC", "NOP", "TRB", "ORA", "ASL", "NOP",
|
||||
"JSR", "AND", "NOP", "NOP", "BIT", "AND", "ROL", "NOP",
|
||||
"PLP", "AND", "ROL", "NOP", "BIT", "AND", "ROL", "NOP",
|
||||
"BMI", "AND", "AND", "NOP", "BIT", "AND", "ROL", "NOP",
|
||||
"SEC", "AND", "DEC", "NOP", "BIT", "AND", "ROL", "NOP",
|
||||
"RTI", "EOR", "NOP", "NOP", "NOP", "EOR", "LSR", "NOP",
|
||||
"PHA", "EOR", "LSR", "NOP", "JMP", "EOR", "LSR", "NOP",
|
||||
"BVC", "EOR", "EOR", "NOP", "NOP", "EOR", "LSR", "NOP",
|
||||
"CLI", "EOR", "PHY", "NOP", "NOP", "EOR", "LSR", "NOP",
|
||||
"RTS", "ADC", "NOP", "NOP", "STZ", "ADC", "ROR", "NOP",
|
||||
"PLA", "ADC", "ROR", "NOP", "JMP", "ADC", "ROR", "NOP",
|
||||
"BVS", "ADC", "ADC", "NOP", "STZ", "ADC", "ROR", "NOP",
|
||||
"SEI", "ADC", "PLY", "NOP", "JMP", "ADC", "ROR", "NOP",
|
||||
"BRA", "STA", "NOP", "NOP", "STY", "STA", "STX", "NOP",
|
||||
"DEY", "BIT", "TXA", "NOP", "STY", "STA", "STX", "NOP",
|
||||
"BCC", "STA", "STA", "NOP", "STY", "STA", "STX", "NOP",
|
||||
"TYA", "STA", "TXS", "NOP", "STZ", "STA", "STZ", "NOP",
|
||||
"LDY", "LDA", "LDX", "NOP", "LDY", "LDA", "LDX", "NOP",
|
||||
"TAY", "LDA", "TAX", "NOP", "LDY", "LDA", "LDX", "NOP",
|
||||
"BCS", "LDA", "LDA", "NOP", "LDY", "LDA", "LDX", "NOP",
|
||||
"CLV", "LDA", "TSX", "NOP", "LDY", "LDA", "LDX", "NOP",
|
||||
"CPY", "CMP", "NOP", "NOP", "CPY", "CMP", "DEC", "NOP",
|
||||
"INY", "CMP", "DEX", "NOP", "CPY", "CMP", "DEC", "NOP",
|
||||
"BNE", "CMP", "CMP", "NOP", "NOP", "CMP", "DEC", "NOP",
|
||||
"CLD", "CMP", "PHX", "NOP", "NOP", "CMP", "DEC", "NOP",
|
||||
"CPX", "SBC", "NOP", "NOP", "CPX", "SBC", "INC", "NOP",
|
||||
"INX", "SBC", "NOP", "NOP", "CPX", "SBC", "INC", "NOP",
|
||||
"BEQ", "SBC", "SBC", "NOP", "NOP", "SBC", "INC", "NOP",
|
||||
"SED", "SBC", "PLX", "NOP", "NOP", "SBC", "INC", "NOP"
|
||||
];
|
||||
|
||||
|
||||
// Addressing modes.
|
||||
|
||||
enum { IMP, IMM, ZP, ZPX, ZPY, IZX, IZY, ABS, ABX, ABY, IND, REL,
|
||||
ZPI, ABI, NP1, NP8, KIL }
|
||||
|
||||
immutable ADDR_MODES_6502 = [
|
||||
IMP, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
|
||||
ABS, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
|
||||
IMP, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
|
||||
IMP, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, IND, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
|
||||
IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPY, ZPY,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABY, ABY,
|
||||
IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPY, ZPY,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABY, ABY,
|
||||
IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
|
||||
IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
|
||||
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
||||
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
||||
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX
|
||||
];
|
||||
|
||||
immutable ADDR_MODES_65C02 = [
|
||||
IMP, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZP, ZPX, ZPX, NP1,
|
||||
IMP, ABY, IMP, NP1, ABS, ABX, ABX, NP1,
|
||||
ABS, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
|
||||
IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1,
|
||||
IMP, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
|
||||
IMP, ABY, IMP, NP1, NP8, ABX, ABX, NP1,
|
||||
IMP, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, IND, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
|
||||
IMP, ABY, IMP, NP1, ABI, ABX, ABX, NP1,
|
||||
REL, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPY, NP1,
|
||||
IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1,
|
||||
IMM, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPY, NP1,
|
||||
IMP, ABY, IMP, NP1, ABX, ABX, ABY, NP1,
|
||||
IMM, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
|
||||
IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1,
|
||||
IMM, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
||||
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
||||
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
|
||||
IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1
|
||||
];
|
||||
|
||||
|
||||
// Page-crossing extra cycles.
|
||||
|
||||
immutable EXTRA_CYCLES_6502 = [
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
];
|
||||
|
||||
immutable EXTRA_CYCLES_65C02 = [
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
];
|
||||
|
|
@ -8,7 +8,7 @@ module test.cpu;
|
|||
|
||||
import std.conv, std.exception, std.random, std.string, std.traits;
|
||||
|
||||
public import cpu6502 : Cpu, is6502, is65C02;
|
||||
public import cpu.d6502 : Cpu, is6502, is65C02;
|
||||
|
||||
|
||||
// True if T is the type of a cpu.
|
||||
|
|
|
|||
Loading…
Reference in New Issue