431 lines
9.7 KiB
D
431 lines
9.7 KiB
D
/+
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+ peripheral/langcard.d
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+
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+ Copyright: 2007 Gerald Stocker
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+
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+ This file is part of Twoapple.
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+
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+ Twoapple is free software; you can redistribute it and/or modify
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+ it under the terms of the GNU General Public License as published by
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+ the Free Software Foundation; either version 2 of the License, or
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+ (at your option) any later version.
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+
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+ Twoapple is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ GNU General Public License for more details.
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+
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+ You should have received a copy of the GNU General Public License
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+ along with Twoapple; if not, write to the Free Software
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+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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+/
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module peripheral.langcard;
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import peripheral.base;
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import device.base;
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import memory;
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private:
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string MakeRAMSwitches(bool isIIe)
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{
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string ramSwitches;
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for (int sw = 0xC080; sw <= 0xC08F; ++sw)
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{
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ramSwitches ~= "void read" ~ hex4Digits(sw) ~ "()\n{\n" ~
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MakeRAMSwitch(sw, false, isIIe) ~ "}\n";
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ramSwitches ~= "void write" ~ hex4Digits(sw) ~ "()\n{\n" ~
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MakeRAMSwitch(sw, true, isIIe) ~ "}\n";
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}
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return ramSwitches;
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}
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string MakeRAMSwitch(int sw, bool write, bool isIIe)
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{
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string ramSwitch;
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ramSwitch ~= CallRAMFunction(isIIe, "setBank(" ~
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hex4Digits((sw & 0b1000) >> 3 ) ~ ")") ~ "\n";
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if (((sw & 0b11) == 0b11) || ((sw & 0b11) == 0b00))
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ramSwitch ~= CallRAMFunction(isIIe, "enableRead()") ~ "\n";
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else
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ramSwitch ~= CallRAMFunction(isIIe, "disableRead()") ~ "\n";
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if ((sw & 0b1) == 0b0)
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ramSwitch ~= CallRAMFunction(isIIe, "clearPreWrite()") ~ "\n" ~
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CallRAMFunction(isIIe, "disableWrite()") ~ "\n";
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else
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{
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if (write)
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ramSwitch ~= CallRAMFunction(isIIe, "clearPreWrite()") ~ "\n";
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else
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ramSwitch ~= CallRAMFunction(isIIe, "checkEnableWrite()") ~ "\n";
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}
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return ramSwitch;
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}
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string CallRAMFunction(bool isIIe, string func)
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{
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if (!isIIe)
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{
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return "implementation." ~ func ~ ";";
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}
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else
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{
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return "onboard." ~ func ~ ";\n" ~
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"if (auxslot !is null) auxslot." ~ func ~ ";";
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}
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}
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static const string[][] langcardSwitches = [
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mixin(MakeSwitch([0xC080], "R0", "readC080")),
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mixin(MakeSwitch([0xC081], "R0", "readC081")),
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mixin(MakeSwitch([0xC082], "R0", "readC082")),
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mixin(MakeSwitch([0xC083], "R0", "readC083")),
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mixin(MakeSwitch([0xC084], "R0", "readC084")),
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mixin(MakeSwitch([0xC085], "R0", "readC085")),
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mixin(MakeSwitch([0xC086], "R0", "readC086")),
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mixin(MakeSwitch([0xC087], "R0", "readC087")),
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mixin(MakeSwitch([0xC088], "R0", "readC088")),
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mixin(MakeSwitch([0xC089], "R0", "readC089")),
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mixin(MakeSwitch([0xC08A], "R0", "readC08A")),
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mixin(MakeSwitch([0xC08B], "R0", "readC08B")),
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mixin(MakeSwitch([0xC08C], "R0", "readC08C")),
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mixin(MakeSwitch([0xC08D], "R0", "readC08D")),
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mixin(MakeSwitch([0xC08E], "R0", "readC08E")),
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mixin(MakeSwitch([0xC08F], "R0", "readC08F")),
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mixin(MakeSwitch([0xC080], "W", "writeC080")),
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mixin(MakeSwitch([0xC081], "W", "writeC081")),
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mixin(MakeSwitch([0xC082], "W", "writeC082")),
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mixin(MakeSwitch([0xC083], "W", "writeC083")),
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mixin(MakeSwitch([0xC084], "W", "writeC084")),
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mixin(MakeSwitch([0xC085], "W", "writeC085")),
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mixin(MakeSwitch([0xC086], "W", "writeC086")),
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mixin(MakeSwitch([0xC087], "W", "writeC087")),
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mixin(MakeSwitch([0xC088], "W", "writeC088")),
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mixin(MakeSwitch([0xC089], "W", "writeC089")),
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mixin(MakeSwitch([0xC08A], "W", "writeC08A")),
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mixin(MakeSwitch([0xC08B], "W", "writeC08B")),
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mixin(MakeSwitch([0xC08C], "W", "writeC08C")),
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mixin(MakeSwitch([0xC08D], "W", "writeC08D")),
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mixin(MakeSwitch([0xC08E], "W", "writeC08E")),
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mixin(MakeSwitch([0xC08F], "W", "writeC08F"))
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];
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public:
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class HighRam
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{
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AddressDecoder decoder;
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ReadFunc origRead;
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WriteFunc origWrite;
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Memory lowerChunk, upperChunk;
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bool preWrite;
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bool readEn, writeEn;
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bool enabled;
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int current4KBank;
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this()
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{
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initMemory();
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}
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abstract void initMemory();
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void init(AddressDecoder addrDecode, ReadFunc read, WriteFunc write)
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{
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decoder = addrDecode;
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origRead = read;
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origWrite = write;
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}
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void reboot()
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{
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preWrite = false;
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lowerChunk.reboot();
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upperChunk.reboot();
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current4KBank = 0;
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forceReadDisable();
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forceWriteEnable();
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}
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void clearPreWrite()
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{
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preWrite = false;
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}
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void forceReadDisable()
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{
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readEn = true;
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disableRead();
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}
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void forceReadEnable()
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{
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readEn = false;
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enableRead();
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}
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void forceWriteEnable()
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{
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writeEn = false;
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enableWrite();
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}
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void enableRead()
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{
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if ((!readEn) && enabled)
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{
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decoder.installRead(lowerChunk);
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decoder.installRead(upperChunk);
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}
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readEn = true;
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}
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void disableRead()
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{
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if (readEn && enabled)
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{
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decoder.readPages[0xD0..0x100] = origRead;
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}
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readEn = false;
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}
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void checkEnableWrite()
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{
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if (preWrite) enableWrite();
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preWrite = true;
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}
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void enableWrite()
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{
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if ((!writeEn) && enabled)
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{
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decoder.installWrite(lowerChunk);
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decoder.installWrite(upperChunk);
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}
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writeEn = true;
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}
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void disableWrite()
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{
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if (writeEn && enabled)
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{
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decoder.writePages[0xD0..0x100] = origWrite;
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}
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writeEn = false;
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}
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abstract void setLowerBank(int bank);
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void setBank(int bank)
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{
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setLowerBank(bank);
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current4KBank = bank;
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}
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}
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class HighRam_II : HighRam
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{
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PrimaryMem e000ffff;
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BankMem d000dfff;
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this()
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{
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super();
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enabled = true;
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}
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void initMemory()
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{
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d000dfff = new BankMem(0xD000, 0x1000, 2);
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e000ffff = new PrimaryMem(0xE000, 0x2000);
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lowerChunk = d000dfff;
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upperChunk = e000ffff;
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}
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void setDebugName(string name)
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{
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e000ffff.debugName = name;
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d000dfff.setDebugNames(name);
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}
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void setLowerBank(int bank)
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{
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d000dfff.setBank(bank);
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}
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}
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class HighRam_IIe : HighRam
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{
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bool isOnboard;
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int numBanks;
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SubBankMem d000dfff;
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BankMem e000ffff;
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this(bool isOnboard_, int banks)
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{
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numBanks = banks;
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super();
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isOnboard = isOnboard_;
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}
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void initMemory()
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{
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d000dfff = new SubBankMem(0xD000, 0x1000, numBanks, 2);
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e000ffff = new BankMem(0xE000, 0x2000, numBanks);
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lowerChunk = d000dfff;
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upperChunk = e000ffff;
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}
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void setLowerBank(int bank)
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{
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d000dfff.setSubBank(bank);
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}
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void resetBanks()
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{
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e000ffff.setBank(0);
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d000dfff.setPrimaryBank(0);
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d000dfff.setSubBank(0);
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}
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void enable(bool newState)
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{
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if (enabled == newState) return;
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enabled = newState;
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if (newState)
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{
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if (writeEn) forceWriteEnable();
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if (readEn) forceReadEnable();
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}
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}
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void setDebugName(string name)
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{
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string[] names;
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names.length = numBanks;
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if (numBanks > 1)
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{
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for (int b = 0; b < numBanks; ++b)
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names[b] = name ~ " " ~ std.string.toString(b);
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}
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else
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{
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names[0] = name;
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}
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e000ffff.setDebugNames(name);
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d000dfff.setDebugNames(names);
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}
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void reboot()
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{
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enabled = isOnboard;
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super.reboot();
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}
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void reset()
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{
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enabled = isOnboard;
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preWrite = false;
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resetBanks();
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current4KBank = 0;
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disableRead();
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enableWrite();
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}
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}
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class HighRam_Null : HighRam_IIe
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{
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this()
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{
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super(false, 0);
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}
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void initMemory()
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{
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lowerChunk = new ZeroMem(0xD000, 0x1000);
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upperChunk = new ZeroMem(0xE000, 0x2000);
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}
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void setLowerBank(int bank) {}
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void resetBanks() {}
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}
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class LanguageCard : Peripheral
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{
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HighRam_II implementation;
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mixin(MakeRAMSwitches(false));
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mixin(InitSwitches("", langcardSwitches));
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this()
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{
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implementation = new HighRam_II();
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implementation.setDebugName("Language card");
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}
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void reboot()
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{
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implementation.reboot();
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}
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}
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class LanguageCard_IIe
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{
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HighRam_IIe onboard, auxslot;
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ubyte delegate() kbdLatch;
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mixin(MakeRAMSwitches(true));
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mixin(InitSwitches("", langcardSwitches ~ [
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mixin(MakeSwitch([0xC011], "R", "readBank2Switch")),
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mixin(MakeSwitch([0xC012], "R", "readReadSwitch"))
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]));
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this()
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{
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onboard = new HighRam_IIe(true, 1);
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onboard.setDebugName("High RAM");
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}
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void init(AddressDecoder addrDecode, ReadFunc read, WriteFunc write)
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{
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onboard.init(addrDecode, read, write);
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auxslot.init(addrDecode, read, write);
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}
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void reboot()
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{
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onboard.reboot();
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auxslot.reboot();
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}
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void reset()
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{
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onboard.reset();
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auxslot.reset();
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}
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void enableAuxSlot(bool isAuxSlot)
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{
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onboard.enable(!isAuxSlot);
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auxslot.enable(isAuxSlot);
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}
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ubyte readBank2Switch()
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{
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return kbdLatch() | ((onboard.current4KBank == 0) ? 0x80 : 0x00);
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}
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ubyte readReadSwitch()
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{
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return kbdLatch() | (onboard.readEn ? 0x80 : 0x00);
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}
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}
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