645 lines
13 KiB
D
645 lines
13 KiB
D
/*
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* Test functionality that either depends on a specific cpu
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* implementation, or that may be useful to any test which requires a
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* cpu (as opposed to testing the cpu itself).
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*/
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module test.d6502.cpu;
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import std.conv, std.exception, std.random, std.string, std.traits;
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public import cpu.d6502 : Cpu, is6502, is65C02;
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import test.d6502.base : strict, cumulative;
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// True if T is the type of a cpu.
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template isCpu(T)
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{
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enum isCpu = __traits(hasMember, T, "_isCpu");
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}
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// True if the cpu type T represents a 6502.
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template isNMOS(T)
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{
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enum isNMOS = is6502!T;
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}
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// True if the cpu type T represents a 65C02.
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template isCMOS(T)
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{
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enum isCMOS = is65C02!T;
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}
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class TestIO
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{
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ubyte delegate(ushort) dread;
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void delegate(ushort, ubyte) dwrite;
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static if (cumulative)
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{
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void delegate(int) dtick;
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void tick(int cycles) { dtick(cycles); }
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}
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else
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{
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void delegate() dtick;
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void tick() { dtick(); }
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}
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ubyte opIndex(ushort i1) const
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{
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auto addr = cast(ushort)i1;
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return dread(addr);
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}
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ubyte opIndexAssign(ubyte val, ushort i1)
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{
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auto addr = cast(ushort)i1;
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dwrite(addr, val);
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return val;
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}
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}
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/*
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* The type of a cpu, based on its architecture (6502 or 65C02).
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*/
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template CPU(string arch, M = TestIO, C = TestIO)
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{
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alias Cpu!(arch, M, C) CPU;
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}
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auto makeCpu(T)(CpuInfo info = CpuInfo())
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if (isCpu!T)
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{
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auto tio = new TestIO();
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auto cpu = new T(tio, tio);
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cpu.PC = info.PC;
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cpu.S = info.SP;
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cpu.statusFromByte(info.S);
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cpu.A = info.A;
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cpu.X = info.X;
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cpu.Y = info.Y;
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return cpu;
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}
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// Connects test memory to a cpu.
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void connectMem(T, S)(T cpu, ref S mem)
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if (isCpu!T)
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{
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static if (cumulative)
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void tick(int cycles) {}
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else
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void tick() {}
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cpu.memory.dread = &mem.read;
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cpu.memory.dwrite = &mem.write;
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cpu.clock.dtick = &tick;
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}
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/*
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* Sets up a cpu to record the number of cycles executed.
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*
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* For example:
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*
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* auto cycles = recordCycles(cpu);
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* // run a test
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* if (cycles != expected) ...
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*/
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auto recordCycles(T)(T cpu)
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if (isCpu!T)
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{
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auto cycles = new int;
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auto wrappedTick = cpu.clock.dtick;
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static if (cumulative)
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{
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void tick(int cyc)
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{
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(*cycles) += cyc;
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wrappedTick(cyc);
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}
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}
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else
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{
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void tick()
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{
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(*cycles)++;
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wrappedTick();
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}
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}
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cpu.clock.dtick = &tick;
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return constRef(cycles);
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}
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struct Ref(T)
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if (isPointer!T)
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{
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private const(T) data;
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this(T ptr) { data = ptr; }
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auto deref() { return *data; }
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alias deref this;
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string toString () const { return format("%s", *data); }
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}
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auto constRef(T)(T ptr)
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if (isPointer!T)
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{
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return Ref!(const(T))(ptr);
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}
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/*
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* Sets up a cpu to record bus accesses during execution.
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*
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* For example:
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*
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* auto accesses = recordBus(cpu);
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* // run a test
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* if (accesses != expected) ...
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*/
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const(Bus[]) recordBus(T)(T cpu, int actions = 8)
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if (isCpu!T)
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{
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auto record = new Bus[actions];
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int c;
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enforce(cpu.memory.dread !is null && cpu.memory.dwrite !is null);
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auto wrappedRead = cpu.memory.dread;
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auto wrappedWrite = cpu.memory.dwrite;
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ubyte read(ushort addr)
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{
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if (c == actions)
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throw new TestException(
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format("cannot record more than %d actions", actions));
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record[c++] = Bus(Action.READ, addr);
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return wrappedRead(addr);
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}
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void write(ushort addr, ubyte val)
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{
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if (c == actions)
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throw new TestException(
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format("cannot record more than %d actions", actions));
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record[c++] = Bus(Action.WRITE, addr);
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wrappedWrite(addr, val);
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}
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cpu.memory.dread = &read;
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cpu.memory.dwrite = &write;
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return record;
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}
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// A record of a bus access with its type and address.
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struct Bus
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{
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Action action;
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ushort addr;
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this(Action action, int addr)
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{
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this.action = action; this.addr = cast(ushort)addr;
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}
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string toString() const
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{
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return format("Bus(%s, %0.4X)", to!string(action), addr);
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}
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}
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// Types of bus accesses.
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enum Action : ushort { NONE, READ, WRITE }
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// Runs the cpu until a BRK instruction.
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void runUntilBRK(T)(T cpu)
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if (isCpu!T)
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{
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assert(cpu.memory.dread !is null);
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auto wrappedRead = cpu.memory.dread;
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ubyte read(ushort addr)
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{
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if (addr == 0xFFFE) throw new StopException("BRK");
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return wrappedRead(addr);
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}
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cpu.memory.dread = &read;
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try { cpu.run(true); } catch (StopException e) {}
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}
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class StopException : Exception { this(string msg) { super(msg); } }
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// Runs the cpu for one opcode.
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void runOneOpcode(T)(T cpu)
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if (isCpu!T)
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{
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cpu.run(false);
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}
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struct CpuInfo
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{
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ushort PC;
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ubyte SP = 0xFF;
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ubyte A, X, Y;
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ubyte S = 0x30;
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string toString() const
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{
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return format("PC %0.4X SP %0.2X S %0.8b A %0.2X X %0.2X Y %0.2X",
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PC, SP, S, A, X, Y);
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}
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static CpuInfo fromCpu(T)(T cpu)
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{
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CpuInfo info;
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info.PC = cpu.PC;
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info.SP = cpu.S;
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info.A = cpu.A;
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info.X = cpu.X;
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info.Y = cpu.Y;
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info.S = cpu.statusToByte();
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return info;
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}
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}
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// Sets the program counter.
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void setPC(T)(ref T cpu, int addr)
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if (isCpu!T || is(T == CpuInfo))
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{
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cpu.PC = cast(ushort)addr;
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}
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void incPC(T : CpuInfo)(ref T cpu, int amt = 1)
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{
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cpu.PC = pageCrossAdd(cpu.PC, amt);
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}
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// Returns the program counter.
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ushort getPC(T)(ref T cpu)
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if (isCpu!T || is(T == CpuInfo))
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{
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return cpu.PC;
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}
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/*
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* Sets the stack pointer.
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*
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* Can be called with either an offset (e.g., 0xFE) or an absolute
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* stack address (e.g., 0x01FE).
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*/
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void setSP(T)(T cpu, int val)
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if (isCpu!T)
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{
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assert(val < 0x0200);
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cpu.S = cast(ubyte)val;
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}
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void setSP(T : CpuInfo)(ref T cpu, int val)
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{
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assert(val < 0x0200);
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cpu.SP = cast(ubyte)val;
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}
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void incSP(T : CpuInfo)(ref T cpu, int amt = 1)
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{
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cpu.SP = cast(ubyte)pageWrapAdd(cpu.SP, amt);
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}
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void decSP(T : CpuInfo)(ref T cpu, int amt = -1)
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{
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cpu.SP = cast(ubyte)pageWrapAdd(cpu.SP, amt);
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}
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/*
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* Returns the stack address (in the range 0x0100-0x01FF) represented
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* by the stack pointer.
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*/
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ushort getSP(T)(T cpu)
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if (isCpu!T)
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{
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return 0x100 | cpu.S;
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}
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ushort getSP(T : CpuInfo)(ref T cpu)
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{
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return 0x0100 | cpu.SP;
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}
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// The names of the registers.
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enum Reg
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{
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A, X, Y
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}
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// Sets a register.
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void setReg(T)(ref T cpu, Reg reg, int val)
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if (isCpu!T || is(T == CpuInfo))
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{
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final switch (reg)
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{
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case Reg.A: setA(cpu, val); break;
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case Reg.X: setX(cpu, val); break;
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case Reg.Y: setY(cpu, val); break;
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}
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}
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// Returns a register
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ubyte getReg(T)(ref T cpu, Reg reg)
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if (isCpu!T || is(T == CpuInfo))
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{
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final switch (reg)
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{
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case Reg.A: return getA(cpu);
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case Reg.X: return getX(cpu);
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case Reg.Y: return getY(cpu);
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}
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}
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// Sets the A register.
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void setA(T)(ref T cpu, int val)
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if (isCpu!T || is(T == CpuInfo))
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{
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cpu.A = cast(ubyte)val;
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}
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// Returns the A register.
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ubyte getA(T)(ref T cpu)
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if (isCpu!T || is(T == CpuInfo))
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{
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return cpu.A;
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}
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// Sets the X register.
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void setX(T)(ref T cpu, int val)
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if (isCpu!T || is(T == CpuInfo))
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{
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cpu.X = cast(ubyte)val;
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}
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// Returns the X register.
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ubyte getX(T)(ref T cpu)
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if (isCpu!T || is(T == CpuInfo))
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{
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return cpu.X;
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}
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// Sets the Y register.
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void setY(T)(ref T cpu, int val)
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if (isCpu!T || is(T == CpuInfo))
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{
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cpu.Y = cast(ubyte)val;
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}
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// Returns the Y register.
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ubyte getY(T)(ref T cpu)
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if (isCpu!T || is(T == CpuInfo))
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{
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return cpu.Y;
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}
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// The names of the status flags.
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enum Flag : ubyte
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{
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C = 0x01,
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Z = 0x02,
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I = 0x04,
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D = 0x08,
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V = 0x40,
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N = 0x80
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}
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string flagToString(Flag f)
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{
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switch (f)
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{
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case Flag.C: return "C";
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case Flag.Z: return "Z";
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case Flag.I: return "I";
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case Flag.D: return "D";
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case Flag.V: return "V";
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case Flag.N: return "N";
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default: return "?";
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}
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}
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// Sets one or more status flags.
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void setFlag(T)(T cpu, Flag[] flags...)
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if (isCpu!T)
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{
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auto reg = cpu.statusToByte();
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foreach (flag; flags) reg |= flag;
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cpu.statusFromByte(reg);
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}
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void setFlag(T : CpuInfo)(ref T cpu, Flag[] flags...)
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{
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foreach (flag; flags) cpu.S |= flag;
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}
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// Clears one or more status flags.
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void clearFlag(T)(T cpu, Flag[] flags...)
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if (isCpu!T)
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{
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auto reg = cpu.statusToByte();
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foreach (flag; flags) reg &= ~flag;
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cpu.statusFromByte(reg);
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}
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void clearFlag(T : CpuInfo)(ref T cpu, Flag[] flags...)
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{
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foreach (flag; flags) cpu.S &= ~flag;
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}
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// Returns a status flag.
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bool getFlag(T)(T cpu, Flag f)
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if (isCpu!T)
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{
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return (cpu.statusToByte() & f) != 0;
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return false;
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}
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bool getFlag(T : CpuInfo)(ref T cpu, Flag f)
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{
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return (cpu.S & f) != 0;
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}
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// Sets the status register from a byte.
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void setStatus(T)(T cpu, int val)
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if (isCpu!T)
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{
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cpu.statusFromByte(cast(ubyte)val);
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}
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void setStatus(T : CpuInfo)(ref T cpu, int val)
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{
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cpu.S = cast(ubyte)val | 0x30;
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}
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// Returns the status register as a byte.
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ubyte getStatus(T)(T cpu)
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if (isCpu!T)
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{
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return cpu.statusToByte();
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return 0;
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}
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ubyte getStatus(T : CpuInfo)(ref T cpu)
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{
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return cpu.S | 0x30;
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}
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// Sets or clears a single status flag.
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void updateFlag(T)(ref T cpu, Flag f, bool val)
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if (isCpu!T || is(T == CpuInfo))
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{
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if (val)
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setFlag(cpu, f);
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else
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clearFlag(cpu, f);
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}
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void setNZ(T : CpuInfo)(ref T cpu, ubyte val)
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{
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updateFlag(cpu, Flag.Z, (val == 0));
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updateFlag(cpu, Flag.N, (val >= 0x80));
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}
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// Sets or clears the flag required for a given opcode to branch.
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void expectBranch(T)(ref T cpu, ubyte opcode)
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if (isCpu!T || is(T == CpuInfo))
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{
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switch (opcode)
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{
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case /*BPL*/ 0x10: clearFlag(cpu, Flag.N); break;
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case /*BMI*/ 0x30: setFlag(cpu, Flag.N); break;
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case /*BVC*/ 0x50: clearFlag(cpu, Flag.V); break;
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case /*BVS*/ 0x70: setFlag(cpu, Flag.V); break;
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case /*BRA*/ 0x80: break;
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case /*BCC*/ 0x90: clearFlag(cpu, Flag.C); break;
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case /*BCS*/ 0xB0: setFlag(cpu, Flag.C); break;
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case /*BNE*/ 0xD0: clearFlag(cpu, Flag.Z); break;
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case /*BEQ*/ 0xF0: setFlag(cpu, Flag.Z); break;
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default:
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enforce(0, format("not a branching opcpde %0.2X", opcode));
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}
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}
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// Returns whether an opcode would branch if executed.
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bool wouldBranch(T)(ref T cpu, ubyte opcode)
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if (isCpu!T || is(T == CpuInfo))
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{
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switch (opcode)
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{
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case /*BPL*/ 0x10: return !getFlag(cpu, Flag.N);
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case /*BMI*/ 0x30: return getFlag(cpu, Flag.N);
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case /*BVC*/ 0x50: return !getFlag(cpu, Flag.V);
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case /*BVS*/ 0x70: return getFlag(cpu, Flag.V);
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case /*BRA*/ 0x80: return true;
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case /*BCC*/ 0x90: return !getFlag(cpu, Flag.C);
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case /*BCS*/ 0xB0: return getFlag(cpu, Flag.C);
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case /*BNE*/ 0xD0: return !getFlag(cpu, Flag.Z);
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case /*BEQ*/ 0xF0: return getFlag(cpu, Flag.Z);
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default:
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assert(0, format("not a branching opcpde %0.2X", opcode));
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}
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}
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// Sets or clears the flag required for a given opcode to not branch.
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void expectNoBranch(T)(ref T cpu, ubyte opcode)
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if (isCpu!T || is(T == CpuInfo))
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{
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switch (opcode)
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{
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case /*BPL*/ 0x10: setFlag(cpu, Flag.N); break;
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case /*BMI*/ 0x30: clearFlag(cpu, Flag.N); break;
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case /*BVC*/ 0x50: setFlag(cpu, Flag.V); break;
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case /*BVS*/ 0x70: clearFlag(cpu, Flag.V); break;
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case /*BCC*/ 0x90: setFlag(cpu, Flag.C); break;
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case /*BCS*/ 0xB0: clearFlag(cpu, Flag.C); break;
|
|
case /*BNE*/ 0xD0: setFlag(cpu, Flag.Z); break;
|
|
case /*BEQ*/ 0xF0: clearFlag(cpu, Flag.Z); break;
|
|
default:
|
|
enforce(0, format("not a branching opcpde %0.2X", opcode));
|
|
}
|
|
}
|
|
|
|
|
|
// Constructs an address from its low and high bytes.
|
|
ushort address(ubyte l, ubyte h)
|
|
{
|
|
return cast(ushort)((h << 8) | l);
|
|
}
|
|
|
|
|
|
ubyte addrLo(ushort addr)
|
|
{
|
|
return cast(ubyte)(addr & 0xFF);
|
|
}
|
|
|
|
ubyte addrHi(ushort addr)
|
|
{
|
|
return cast(ubyte)(addr >> 8);
|
|
}
|
|
|
|
|
|
/*
|
|
* Adds an offset to an address, resulting in an address in the same
|
|
* page.
|
|
*/
|
|
ushort pageWrapAdd(ushort base, int offset)
|
|
{
|
|
return (base & 0xFF00) + cast(ubyte)((base & 0xFF) + offset);
|
|
}
|
|
|
|
|
|
/*
|
|
* Adds an offset to an address, possibly resulting in an address in a
|
|
* different page.
|
|
*/
|
|
ushort pageCrossAdd(ushort base, int offset)
|
|
{
|
|
return cast(ushort)(base + offset);
|
|
}
|
|
|
|
|
|
// A random value to use for "uninitialized" memory.
|
|
ubyte XX()
|
|
{
|
|
return cast(ubyte)uniform(0, 256);
|
|
}
|
|
|
|
// A number different from some other number.
|
|
ubyte notXX(ubyte val)
|
|
{
|
|
return cast(ubyte)~val;
|
|
}
|
|
|
|
|
|
class TestException : Exception { this(string msg) { super(msg); } }
|