1271 lines
35 KiB
D
1271 lines
35 KiB
D
module cpu6502;
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import std.array, std.format;
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enum Strict : bool
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{
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no, yes
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}
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enum Cumulative : bool
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{
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no, yes
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}
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template is6502(T)
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{
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enum is6502 = __traits(getMember, T, "_chip") == "6502";
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}
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template is65C02(T)
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{
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enum is65C02 = __traits(getMember, T, "_chip") == "65C02";
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}
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// The following versions are mutually exclusive.
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// OpDelegates: each opcode is a method of the Cpu class.
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version(OpDelegates)
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{
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enum versionCheck = 1;
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enum opArray = true;
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}
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// OpFunctions: each opcode is a free function with a Cpu argument.
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version(OpFunctions)
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{
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enum versionCheck = 2;
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enum opArray = true;
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// With free functions, strict and cumulative need to be set by
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// version.
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version(Strict)
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enum vStrict = true;
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else
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enum vStrict = false;
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version(Cumulative)
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enum vCumulative = true;
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else
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enum vCumulative = false;
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}
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// OpSwitch: each opcode is inlined in a 256-case switch.
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version(OpSwitch)
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{
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enum versionCheck = 3;
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enum opArray = false;
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}
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/*
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* OpNestedSwitch: each opcode is inlined in a nested switch.
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*
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* (The outer one switches on the high byte, with each case switching
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* on the low byte.)
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*/
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version(OpNestedSwitch)
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{
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enum versionCheck = 4;
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enum opArray = false;
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}
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// At least one of the previous versions must be specified.
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static if (!__traits(compiles, { bool b = opArray; })) enum opArray = 0;
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static assert (versionCheck);
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// This needs to be before any mixins which call any CTFE functions
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// that make use of these constants.
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enum { IMP, IMM, ZP, ZPX, ZPY, IZX, IZY, ABS, ABX, ABY, IND, REL,
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ZPI, ABI, NP1, NP8, KIL }
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final class Cpu(string chip, bool strict, bool cumulative)
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{
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static assert(chip == "6502" || chip == "65C02" || chip == "65c02");
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enum _isCpu = true;
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enum _chip = (chip == "6502" ? "6502" : "65C02");
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enum _isStrict = strict;
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enum _isCumulative = cumulative;
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struct _Mem
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{
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// Reads a value from system memory.
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ubyte delegate(ushort addr) read;
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// Writes a value to system memory.
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void delegate(ushort addr, ubyte val) write;
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}
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_Mem memory;
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struct _Clock
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{
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static if (cumulative)
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/*
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* Updates the number of cycles executed. Called just
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* prior to the final read/write action of each opcode.
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*/
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void delegate(int cycles) tick;
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else
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/*
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* Increments the number of cycles executed. Called prior
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* to each read/write action.
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*/
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void delegate() tick;
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}
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_Clock clock;
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ubyte A, X, Y, S;
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ushort PC;
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ubyte N, Z;
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bool V, D, I, C;
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static if (opArray)
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{
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mixin(OpArrayDef());
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}
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// TODO: other methods for stopping cpu
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bool keepRunning;
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this()
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{
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static if (opArray) mixin(OpArrayInit());
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}
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final void statusFromByte(ubyte p)
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{
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N = p;
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V = ((p & 0x40) != 0);
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D = ((p & 0x08) != 0);
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I = ((p & 0x04) != 0);
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Z = ((p & 0x02) ? 0 : 1);
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C = ((p & 0x01) != 0);
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}
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final ubyte statusToByte()
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{
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return (C ? 0x01 : 0) |
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((Z == 0) ? 0x02 : 0) |
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(I ? 0x04 : 0) |
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(D ? 0x08 : 0) |
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0x30 | // break and reserved both set
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(V ? 0x40 : 0) |
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(N & 0x80);
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}
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final void run(bool continuous)
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{
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keepRunning = continuous;
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// TODO debugging info?
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ubyte opcode;
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static if (!opArray)
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{
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static if (cumulative) { int cycles; }
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ubyte op1;
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ushort address, base;
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ubyte data;
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}
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do {
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static if (cumulative && !opArray)
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cycles = 1;
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// XXX figure out final cycle stuff
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static if (!cumulative)
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clock.tick();
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// XXX check signals, NMI/IRQ delays, etc.
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opcode = memory.read(PC++);
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mixin(OpExecute(_chip, strict, cumulative));
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} while (keepRunning);
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}
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version(OpDelegates) mixin (OpBodies(_chip, strict, cumulative));
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}
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enum ushort IRQ_VECTOR = 0xFFFE;
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private:
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version(OpFunctions) mixin(OpBodies("6502", vStrict, vCumulative));
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version(OpFunctions) mixin(OpBodies("65C02", vStrict, vCumulative));
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string OpArrayDef()
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{
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version(OpDelegates)
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return q{void delegate()[256] opcodes;};
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else version(OpFunctions)
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return q{void function(typeof(this))[256] opcodes;};
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else
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return "";
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}
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string OpArrayInit()
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{
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static if (!opArray) return "";
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else
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{
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string ret;
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foreach (op; 0..256)
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{
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version(OpDelegates)
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ret ~= Fmt("opcodes[0x#] = &opcode_#;\n",
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Hex2(op), Hex2(op));
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version(OpFunctions)
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ret ~= Fmt("opcodes[0x#] = &opcode_#!(typeof(this));\n",
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Hex2(op), Hex2(op));
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}
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return ret;
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}
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}
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string OpBodies(string chip, bool strict, bool cumulative)
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{
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static if (!opArray) return "";
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else
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{
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string ret;
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foreach (op; 0..256)
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{
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version(OpDelegates)
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ret ~= "final void opcode_" ~ Hex2(op) ~ "()\n{\n" ~
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If!(cumulative)("int cycles = 1;\n") ~
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OpBody(op, chip, strict, cumulative) ~ "}\n";
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version(OpFunctions)
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ret ~= "void opcode_" ~ Hex2(op) ~
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"(T)(T cpu) if (is" ~ chip ~ "!T)\n{\n" ~
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If!(cumulative)("int cycles = 1;\n") ~
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OpBody(op, chip, strict, cumulative) ~ "}\n";
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}
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return ret;
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}
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}
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string OpExecute(string chip, bool strict, bool cumulative)
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{
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version(OpDelegates)
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return q{opcodes[opcode]();};
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version(OpFunctions)
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return q{opcodes[opcode](this);};
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version(OpSwitch)
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return Switch256(chip, strict, cumulative);
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version(OpNestedSwitch)
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return Switch16x16(chip, strict, cumulative);
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}
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string Switch256(string chip, bool strict, bool cumulative)
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{
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string ret = "final switch (opcode)\n{\n";
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foreach (op; 0..256)
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ret ~= "case 0x" ~ Hex2(op) ~ ":\n" ~
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OpBody(op, chip, strict, cumulative) ~ "break;\n";
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return ret ~ "}\n";
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}
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string Switch16x16(string chip, bool strict, bool cumulative)
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{
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string ret = "final switch (opcode & 0xF0)\n{\n";
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foreach (opHi; 0..16)
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{
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ret ~= "case 0x" ~ Hex1(opHi) ~ "0:\n" ~
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"final switch(opcode & 0x0F)\n{\n";
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foreach (opLo; 0..16)
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{
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int op = opLo | (opHi << 4);
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ret ~= "case 0x0" ~ Hex1(opLo) ~ ":\n" ~
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OpBody(op, chip, strict, cumulative) ~
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"break;\n";
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}
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ret ~= "}\nbreak;\n";
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}
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return ret ~ "}\n";
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}
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string OpBody(int op, string chip, bool s, bool c)
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{
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bool nmos = (chip == "6502");
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final switch (opName(op, chip))
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{
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case "BRK":
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return Break(s, c) ~
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Done(c);
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case "RTI":
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return "";
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case "JSR":
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return JumpSub(s, c) ~
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Done(c);
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case "RTS":
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return RetSub(s, c) ~
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Done(c);
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case "JMP":
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return Jump(op, chip, s, c) ~
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Done(c);
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case "KIL":
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return "";
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case "BPL":
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return Branch("!(" ~ Attr("N") ~ " & 0x80)", nmos, s, c) ~
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Done(c);
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case "BMI":
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return Branch("(" ~ Attr("N") ~ " & 0x80)", nmos, s, c) ~
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Done(c);
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case "BVC":
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return Branch("!" ~ Attr("V"), nmos, s, c) ~
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Done(c);
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case "BVS":
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return Branch(Attr("V"), nmos, s, c) ~
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Done(c);
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case "BRA":
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return Branch("true", nmos, s, c) ~
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Done(c);
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case "BCC":
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return Branch("!" ~ Attr("C"), nmos, s, c) ~
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Done(c);
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case "BCS":
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return Branch(Attr("C"), nmos, s, c) ~
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Done(c);
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case "BNE":
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return Branch(Attr("Z"), nmos, s, c) ~
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Done(c);
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case "BEQ":
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return Branch("!" ~ Attr("Z"), nmos, s, c) ~
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Done(c);
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case "CLC":
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return AddrImplied(s, c) ~
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ClearFlag("C") ~
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Done(c);
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case "SEC":
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return AddrImplied(s, c) ~
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SetFlag("C") ~
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Done(c);
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case "CLI":
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return AddrImplied(s, c) ~
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ClearFlag("I") ~
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Done(c);
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case "SEI":
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return AddrImplied(s, c) ~
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SetFlag("I") ~
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Done(c);
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case "CLV":
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return AddrImplied(s, c) ~
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ClearFlag("V") ~
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Done(c);
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case "CLD":
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return AddrImplied(s, c) ~
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ClearFlag("D") ~
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Done(c);
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case "SED":
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return AddrImplied(s, c) ~
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SetFlag("D") ~
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Done(c);
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case "NOP":
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return ""; // address modes
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case "TAX":
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return "";
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case "TXA":
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return "";
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case "TAY":
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return "";
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case "TYA":
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return "";
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case "TSX":
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return "";
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case "TXS":
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return "";
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case "DEX":
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return DecReg("X", s, c) ~
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Done(c);
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case "DEY":
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return DecReg("Y", s, c) ~
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Done(c);
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case "INX":
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return IncReg("X", s, c) ~
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Done(c);
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case "INY":
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return IncReg("Y", s, c) ~
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Done(c);
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case "PHP":
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return AddrImplied(s, c) ~
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Push(Attr("statusToByte()"), s, c) ~
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Done(c);
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case "PLP":
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return AddrImplied(s, c) ~
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PullStatus(s, c) ~
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Done(c);
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case "PLA":
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return AddrImplied(s, c) ~
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PullInto(Attr("A"), s, c) ~
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SetNZ(Attr("A")) ~
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Done(c);
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case "PLX":
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return "";
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case "PLY":
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return "";
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case "PHA":
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return "";
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case "PHX":
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return "";
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case "PHY":
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return "";
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case "LDA":
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return Load(op, "A", chip, s, c) ~
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Done(c);
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case "LDX":
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return Load(op, "X", chip, s, c) ~
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Done(c);
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case "LDY":
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return Load(op, "Y", chip, s, c) ~
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Done(c);
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case "STA":
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return Store(op, "A", chip, s, c) ~
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Done(c);
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case "STX":
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return Store(op, "X", chip, s, c) ~
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Done(c);
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case "STY":
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return Store(op, "Y", chip, s, c) ~
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Done(c);
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case "STZ":
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return "";
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case "BIT":
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return ""; // address modes
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case "CMP":
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return Compare(op, "A", chip, s, c) ~
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Done(c);
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case "CPX":
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return Compare(op, "X", chip, s, c) ~
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Done(c);
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case "CPY":
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return Compare(op, "Y", chip, s, c) ~
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Done(c);
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case "ORA":
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return Logic(op, "|=", chip, s, c) ~
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Done(c);
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case "AND":
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return Logic(op, "&=", chip, s, c) ~
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Done(c);
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case "EOR":
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return Logic(op, "^=", chip, s, c) ~
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Done(c);
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case "ADC":
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return Add(op, chip, s, c) ~
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Done(c);
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case "SBC":
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return Sub(op, chip, s, c) ~
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Done(c);
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case "ASL":
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return ""; // n/c (op, cyc)
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case "ROL":
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return ""; // n/c (op, cyc)
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case "LSR":
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return ""; // n/c (op, cyc)
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case "ROR":
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return ""; // n/c (op, cyc)
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case "INC":
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if (op == 0x1a)
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return IncReg("A", s, c) ~ Done(c);
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else
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return RMW(op, "data++;\n", chip, s, c) ~ Done(c);
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case "DEC":
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if (op == 0x3a)
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return DecReg("A", s, c) ~ Done(c);
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else
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return RMW(op, "data--;\n", chip, s, c) ~ Done(c);
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case "TRB":
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return "";
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case "TSB":
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return "";
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case "LAS":
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return "";
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case "LAX":
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return ""; // address modes
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case "SAX":
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return "";
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case "ANC":
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return "";
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case "ALR":
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return "";
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case "ARR":
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return "";
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case "AXS":
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return "";
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case "AHX":
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return "";
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case "SHY":
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return "";
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case "SHX":
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return "";
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case "TAS":
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return "";
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case "XAA":
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return "";
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case "SLO":
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return "";
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case "RLA":
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return "";
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case "SRE":
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return "";
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case "RRA":
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return "";
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case "DCP":
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return "";
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case "ISC":
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return "";
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}
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}
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string AddrImmediate(bool s, bool c)
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{
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return Local("ushort", "address") ~ " = " ~ Attr("PC") ~ "++;\n";
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}
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string AddrImplied(bool s, bool c)
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{
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return Peek(Attr("PC"), s, c);
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}
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string AddrAbsoluteIdx(int op, string reg, string chip, bool s, bool c)
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{
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bool nmos = (chip == "6502");
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int exCyc = opExCyc(op, chip);
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string IDX = Attr(reg);
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return ReadWordOpLocal("ushort", "base", c) ~
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Local("ushort","address")~" = cast(ushort)(base + " ~ IDX ~ ");\n" ~
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"ushort guess = (base & 0xFF00) | cast(ubyte)address;\n" ~
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"if (guess != address)\n{\n" ~
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If!(nmos)(Peek("guess", s, c), Peek(Attr("PC"), s, c)) ~
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"}\n" ~
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If!(exCyc)("else\n{\n" ~ Peek("address", s, c) ~ "}\n");
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}
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string Branch(string check, bool nmos, bool s, bool c)
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{
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string PC = Attr("PC");
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return ReadInto(Local("ubyte", "op1"), PC, c) ~
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IncPC() ~
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"if (" ~ check ~ ")\n{\n" ~
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Peek(PC, s, c) ~
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Local("ushort", "base") ~ " = " ~ PC ~ ";\n" ~
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PC ~ " = cast(ushort)(" ~ PC ~ " + cast(byte)op1);\n" ~
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"ushort guess = (base & 0xFF00) | cast(ubyte)" ~ PC ~ ";\n" ~
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"if (guess != " ~ PC ~ ")\n{\n" ~
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If!(nmos)(Peek("guess", s, c), Peek("base", s, c)) ~
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"}\n}\n";
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}
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string Break(bool s, bool c)
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{
|
|
return AddrImplied(s, c) ~
|
|
IncPC() ~
|
|
PushPC(s, c) ~
|
|
Push(Attr("statusToByte()"), s, c) ~
|
|
SetFlag("I") ~
|
|
ReadWord(Attr("PC"), "IRQ_VECTOR", c);
|
|
}
|
|
|
|
|
|
string RetSub(bool s, bool c)
|
|
{
|
|
string PC = Attr("PC");
|
|
|
|
return AddrImplied(s, c) ~
|
|
PullPC(s, c) ~
|
|
Peek(PC, s, c) ~
|
|
IncPC();
|
|
}
|
|
|
|
|
|
string JumpSub(bool s, bool c)
|
|
{
|
|
string PC = Attr("PC");
|
|
|
|
return ReadInto(Local("ushort", "address"), PC ~ "++", c) ~
|
|
Peek("0x0100 + " ~ Attr("S"), s, c) ~
|
|
PushPC(s, c) ~
|
|
PreAccess(c) ~
|
|
"address |= (" ~ ReadRaw(PC ~ "++") ~ " << 8);\n" ~
|
|
PC ~ " = address;\n";
|
|
}
|
|
|
|
|
|
string Jump(int op, string chip, bool s, bool c)
|
|
{
|
|
if (op == 0x4c)
|
|
return Address(op, chip, s, c) ~
|
|
Attr("PC") ~ " = address;\n";
|
|
else
|
|
return "";
|
|
}
|
|
|
|
|
|
string Load(int op, string reg, string chip, bool s, bool c)
|
|
{
|
|
return Address(op, chip, s, c) ~
|
|
ReadInto(Attr(reg), "address", c) ~
|
|
SetNZ(Attr(reg));
|
|
}
|
|
|
|
|
|
string Store(int op, string reg, string chip, bool s, bool c)
|
|
{
|
|
return Address(op, chip, s, c) ~
|
|
Write("address", Attr(reg), c);
|
|
}
|
|
|
|
|
|
string Compare(int op, string reg, string chip, bool s, bool c)
|
|
{
|
|
return Address(op, chip, s, c) ~
|
|
ReadInto(Local("ubyte", "data"), "address", c) ~
|
|
UpdateFlag("C", Attr(reg) ~ " >= data") ~
|
|
SetNZ("cast(ubyte)(" ~ Attr(reg) ~ " - data)");
|
|
}
|
|
|
|
|
|
string Logic(int op, string action, string chip, bool s, bool c)
|
|
{
|
|
return Address(op, chip, s, c) ~
|
|
ReadInto(Attr("A"), "address", c, action) ~
|
|
SetNZ(Attr("A"));
|
|
}
|
|
|
|
|
|
string Add(int op, string chip, bool s, bool c)
|
|
{
|
|
return Address(op, chip, s, c) ~
|
|
ReadInto(Local("ubyte", "data"), "address", c) ~
|
|
"if (" ~ Attr("D") ~ ")\n{\n" ~
|
|
DecAdd(chip, s, c) ~
|
|
"}\nelse\n{\n" ~
|
|
HexAdd(chip, s, c) ~
|
|
"}\n";
|
|
}
|
|
|
|
string HexAdd(string chip, bool s, bool c)
|
|
{
|
|
string A = Attr("A"), C = Attr("C");
|
|
|
|
return "uint sum = " ~ A ~ " + data + " ~ C ~ ";\n" ~
|
|
Attr("V") ~
|
|
" = (!((" ~ A ~ " ^ data) & 0x80)) && ((data ^ sum) & 0x80);\n" ~
|
|
C ~ " = (sum > 0xFF);\n" ~
|
|
SetNZ(A ~ " = cast(ubyte)sum");
|
|
}
|
|
|
|
string DecAdd(string chip, bool s, bool c)
|
|
{
|
|
bool cmos = (chip != "6502");
|
|
string A = Attr("A"), C = Attr("C");
|
|
|
|
return "int a = " ~ A ~ ";\n" ~
|
|
"int al = (a & 0x0F) + (data & 0x0F) + " ~ C ~ ";\n" ~
|
|
"if (al >= 0x0A)\n" ~
|
|
"al = ((al + 0x06) & 0x0F) + 0x10;\n" ~
|
|
"a = (a & 0xF0) + (data & 0xF0) + al;\n" ~
|
|
If!(cmos)("",
|
|
Attr("N") ~ " = cast(ubyte)a;\n" ~
|
|
Attr("Z") ~ " = cast(ubyte)(" ~ A ~ " + data + " ~ C ~ ");\n") ~
|
|
Attr("V") ~
|
|
" = (!((" ~ A ~ " ^ data) & 0x80)) && ((data ^ a) & 0x80);\n" ~
|
|
"if (a >= 0xA0)\n" ~
|
|
"a = a + 0x60;\n" ~
|
|
C ~ " = (a >= 0x100);\n" ~
|
|
If!(cmos)(
|
|
SetNZ(A ~ " = cast(ubyte)a") ~ Peek(Attr("PC"), s, c),
|
|
A ~ " = cast(ubyte)a;\n");
|
|
}
|
|
|
|
|
|
string Sub(int op, string chip, bool s, bool c)
|
|
{
|
|
return Address(op, chip, s, c) ~
|
|
ReadInto(Local("ubyte", "data"), "address", c) ~
|
|
"if (" ~ Attr("D") ~ ")\n{\n" ~
|
|
DecSub(chip, s, c) ~
|
|
"}\nelse\n{\n" ~
|
|
HexSub(chip, s, c) ~
|
|
"}\n";
|
|
}
|
|
|
|
string HexSub(string chip, bool s, bool c)
|
|
{
|
|
string A = Attr("A"), C = Attr("C");
|
|
|
|
return "uint diff = " ~ A ~ " - data - !" ~ C ~ ";\n" ~
|
|
Attr("V") ~
|
|
" = ((" ~ A ~ " ^ diff) & 0x80) && ((" ~ A ~ " ^ data) & 0x80);\n" ~
|
|
C ~ " = (diff < 0x100);\n" ~
|
|
SetNZ(A ~ " = cast(ubyte)diff");
|
|
}
|
|
|
|
string DecSub(string chip, bool s, bool c)
|
|
{
|
|
return (chip == "6502" ? DecSubNMOS(s, c) : DecSubCMOS(s, c));
|
|
}
|
|
|
|
string DecSubNMOS(bool s, bool c)
|
|
{
|
|
string A = Attr("A"), C = Attr("C");
|
|
|
|
return "int a = " ~ A ~ ";\n" ~
|
|
"int al = (a & 0x0F) - (data & 0x0F) - !" ~ C ~ ";\n" ~
|
|
"if (al < 0)\n" ~
|
|
"al = ((al - 0x06) & 0x0F) - 0x10;\n" ~
|
|
"a = (a & 0xF0) - (data & 0xF0) + al;\n" ~
|
|
"if (a < 0)\n" ~
|
|
"a = a - 0x60;\n" ~
|
|
"uint diff = " ~ A ~ " - data - !" ~ C ~ ";\n" ~
|
|
Attr("V") ~
|
|
" = ((" ~ A ~ " ^ diff) & 0x80) && ((" ~ A ~ " ^ data) & 0x80);\n" ~
|
|
C ~ " = (diff < 0x100);\n" ~
|
|
SetNZ("cast(ubyte)diff") ~
|
|
A ~ " = cast(ubyte)a;\n";
|
|
}
|
|
|
|
string DecSubCMOS(bool s, bool c)
|
|
{
|
|
string A = Attr("A"), C = Attr("C");
|
|
|
|
return "int a = " ~ A ~ ";\n" ~
|
|
"int al = (a & 0x0F) - (data & 0x0F) - !" ~ C ~ ";\n" ~
|
|
"a = a - data - !" ~ C ~ ";\n" ~
|
|
"if (a < 0) a = a - 0x60;\n" ~
|
|
"if (al < 0) a = a - 0x06;\n" ~
|
|
"uint diff = " ~ A ~ " - data - !" ~ C ~ ";\n" ~
|
|
Attr("V") ~
|
|
" = ((" ~ A ~ " ^ diff) & 0x80) && ((" ~ A ~ " ^ data) & 0x80);\n" ~
|
|
C ~ " = (diff < 0x100);\n" ~
|
|
Peek(Attr("PC"), s, c) ~
|
|
SetNZ(A ~ " = cast(ubyte)a");
|
|
}
|
|
|
|
|
|
string IncReg(string reg, bool s, bool c)
|
|
{
|
|
return AddrImplied(s, c) ~
|
|
Attr(reg) ~ "++;\n" ~
|
|
SetNZ(Attr(reg));
|
|
}
|
|
|
|
|
|
string DecReg(string reg, bool s, bool c)
|
|
{
|
|
return AddrImplied(s, c) ~
|
|
Attr(reg) ~ "--;\n" ~
|
|
SetNZ(Attr(reg));
|
|
}
|
|
|
|
|
|
string RMW(int op, string action, string chip, bool s, bool c)
|
|
{
|
|
bool nmos = (chip == "6502");
|
|
|
|
return Address(op, chip, s, c) ~
|
|
ReadInto(Local("ubyte", "data"), "address", c) ~
|
|
If!(nmos)(Poke("address", "data", s, c),
|
|
Peek("address", s, c)) ~
|
|
action ~
|
|
SetNZ("data") ~
|
|
Write("address", "data", c);
|
|
}
|
|
|
|
|
|
string Address(int op, string chip, bool s, bool c)
|
|
{
|
|
auto EXTRA_CYCLE = opExCyc(op, chip);
|
|
auto PC = Attr("PC");
|
|
|
|
final switch (opMode(op, chip))
|
|
{
|
|
case IMP:
|
|
return AddrImplied(s, c);
|
|
case IMM:
|
|
return AddrImmediate(s, c);
|
|
case ZP:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
case ZPX:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
case ZPY:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
case IZX:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
case IZY:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
case ABS:
|
|
return ReadWordOpLocal("ushort", "address", c);
|
|
case ABX:
|
|
return AddrAbsoluteIdx(op, "X", chip, s, c);
|
|
case ABY:
|
|
return AddrAbsoluteIdx(op, "Y", chip, s, c);
|
|
case IND:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
case REL:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
case ZPI:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
case ABI:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
case NP1:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
case NP8:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
case KIL:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
}
|
|
return "";
|
|
}
|
|
|
|
|
|
string PreAccess(bool cumulative)
|
|
{
|
|
return If!(cumulative)("++cycles;\n", Attr("clock") ~ ".tick();\n");
|
|
}
|
|
|
|
string Peek(string addr, bool strict, bool cumulative)
|
|
{
|
|
return PreAccess(cumulative) ~
|
|
If!(strict)(Attr("memory") ~ ".read(" ~ addr ~");\n");
|
|
}
|
|
|
|
string Poke(string addr, string val, bool strict, bool cumulative)
|
|
{
|
|
return PreAccess(cumulative) ~
|
|
If!(strict)(
|
|
Attr("memory") ~ ".write(" ~ addr ~ ", " ~ val ~ ");\n");
|
|
}
|
|
|
|
string ReadInto(string var, string addr, bool c, string action = "=")
|
|
{
|
|
return PreAccess(c) ~
|
|
var ~ " " ~ action ~ " " ~ ReadRaw("(" ~ addr ~ ")") ~ ";\n";
|
|
}
|
|
|
|
string ReadRaw(string addr)
|
|
{
|
|
return Attr("memory") ~ ".read(" ~ addr ~")";
|
|
}
|
|
|
|
string Write(string addr, string val, bool cumulative)
|
|
{
|
|
return PreAccess(cumulative) ~
|
|
Attr("memory") ~ ".write(" ~ addr ~ ", " ~ val ~ ");\n";
|
|
}
|
|
|
|
string ReadWord(string var, string addr, bool c)
|
|
{
|
|
return PreAccess(c) ~
|
|
var ~ " = " ~ ReadRaw(addr) ~ ";\n" ~
|
|
PreAccess(c) ~
|
|
var ~ " |= (" ~ ReadRaw("cast(ushort)((" ~ addr ~ ") + 1)") ~
|
|
" << 8);\n";
|
|
}
|
|
|
|
string ReadWordOpLocal(string type, string var, bool c)
|
|
{
|
|
string PC = Attr("PC");
|
|
|
|
return PreAccess(c) ~
|
|
Local(type, var) ~ " = " ~ ReadRaw(PC ~ "++") ~ ";\n" ~
|
|
PreAccess(c) ~
|
|
var ~ " |= (" ~ ReadRaw(PC ~ "++") ~
|
|
" << 8);\n";
|
|
}
|
|
|
|
|
|
string IncPC()
|
|
{
|
|
return "++" ~ Attr("PC") ~ ";\n";
|
|
}
|
|
|
|
|
|
string IncSP()
|
|
{
|
|
return "++" ~ Attr("S") ~ ";\n";
|
|
}
|
|
|
|
string DecSP()
|
|
{
|
|
return "--" ~ Attr("S") ~ ";\n";
|
|
}
|
|
|
|
string PullStatus(bool s, bool c)
|
|
{
|
|
return Peek("0x0100 + " ~ Attr("S"), s, c) ~
|
|
IncSP() ~
|
|
PreAccess(c) ~
|
|
Attr("statusFromByte") ~ "(" ~
|
|
ReadRaw("0x0100 + " ~ Attr("S")) ~ ");\n";
|
|
}
|
|
|
|
string PullInto(string var, bool s, bool c)
|
|
{
|
|
return Peek("0x0100 + " ~ Attr("S"), s, c) ~
|
|
IncSP() ~
|
|
ReadInto(var, "0x0100 + " ~ Attr("S"), c);
|
|
}
|
|
|
|
string Push(string val, bool s, bool c)
|
|
{
|
|
return Write("0x0100 + " ~ Attr("S"), val, c) ~
|
|
DecSP();
|
|
}
|
|
|
|
string PushPC(bool s, bool c)
|
|
{
|
|
return Push(HiByte(Attr("PC")), s, c) ~
|
|
Push(LoByte(Attr("PC")), s, c);
|
|
}
|
|
|
|
|
|
string PullPC(bool s, bool c)
|
|
{
|
|
string PC = Attr("PC");
|
|
|
|
return PullInto(PC, s, c) ~
|
|
PreAccess(c) ~
|
|
IncSP() ~
|
|
PC ~ " |= (" ~ ReadRaw("0x0100 + " ~ Attr("S")) ~ " << 8);\n";
|
|
}
|
|
|
|
string SetFlag(string flag)
|
|
{
|
|
return Attr(flag) ~ " = true;\n";
|
|
}
|
|
|
|
string ClearFlag(string flag)
|
|
{
|
|
return Attr(flag) ~ " = false;\n";
|
|
}
|
|
|
|
string UpdateFlag(string flag, string val)
|
|
{
|
|
return Attr(flag) ~ " = (" ~ val ~ ");\n";
|
|
}
|
|
|
|
string SetNZ(string var)
|
|
{
|
|
return Attr("N") ~ " = " ~ Attr("Z") ~ " = (" ~ var ~ ");\n";
|
|
}
|
|
|
|
string Done(bool cumulative)
|
|
{
|
|
return If!(cumulative)(Attr("clock") ~ ".tick(cycles);\n");
|
|
}
|
|
|
|
|
|
string Attr(string var)
|
|
{
|
|
version(OpFunctions)
|
|
return "cpu." ~ var;
|
|
else
|
|
return var;
|
|
}
|
|
|
|
|
|
string Local(string type, string var)
|
|
{
|
|
version(OpSwitch)
|
|
return var;
|
|
else version(OpNestedSwitch)
|
|
return var;
|
|
else
|
|
return type ~ " " ~ var;
|
|
}
|
|
|
|
|
|
string HiByte(string var)
|
|
{
|
|
return var ~ " >> 8";
|
|
}
|
|
|
|
string LoByte(string var)
|
|
{
|
|
return var ~ " & 0xff";
|
|
}
|
|
|
|
|
|
string If(alias cond)(string yes, string no = "")
|
|
{
|
|
if (cond)
|
|
return yes;
|
|
else
|
|
return no;
|
|
}
|
|
|
|
|
|
string opName(int op, string chip)
|
|
{
|
|
if (chip == "6502")
|
|
return OP_NAMES_6502[op];
|
|
else
|
|
return OP_NAMES_65C02[op];
|
|
}
|
|
|
|
int opMode(int op, string chip)
|
|
{
|
|
if (chip == "6502")
|
|
return ADDR_MODES_6502[op];
|
|
else
|
|
return ADDR_MODES_65C02[op];
|
|
}
|
|
|
|
int opExCyc(int op, string chip)
|
|
{
|
|
if (chip == "6502")
|
|
return EXTRA_CYCLES_6502[op];
|
|
else
|
|
return EXTRA_CYCLES_65C02[op];
|
|
}
|
|
|
|
|
|
// Opcode names.
|
|
immutable OP_NAMES_6502 = [
|
|
"BRK", "ORA", "KIL", "SLO", "NOP", "ORA", "ASL", "SLO",
|
|
"PHP", "ORA", "ASL", "ANC", "NOP", "ORA", "ASL", "SLO",
|
|
"BPL", "ORA", "KIL", "SLO", "NOP", "ORA", "ASL", "SLO",
|
|
"CLC", "ORA", "NOP", "SLO", "NOP", "ORA", "ASL", "SLO",
|
|
"JSR", "AND", "KIL", "RLA", "BIT", "AND", "ROL", "RLA",
|
|
"PLP", "AND", "ROL", "ANC", "BIT", "AND", "ROL", "RLA",
|
|
"BMI", "AND", "KIL", "RLA", "NOP", "AND", "ROL", "RLA",
|
|
"SEC", "AND", "NOP", "RLA", "NOP", "AND", "ROL", "RLA",
|
|
"RTI", "EOR", "KIL", "SRE", "NOP", "EOR", "LSR", "SRE",
|
|
"PHA", "EOR", "LSR", "ALR", "JMP", "EOR", "LSR", "SRE",
|
|
"BVC", "EOR", "KIL", "SRE", "NOP", "EOR", "LSR", "SRE",
|
|
"CLI", "EOR", "NOP", "SRE", "NOP", "EOR", "LSR", "SRE",
|
|
"RTS", "ADC", "KIL", "RRA", "NOP", "ADC", "ROR", "RRA",
|
|
"PLA", "ADC", "ROR", "ARR", "JMP", "ADC", "ROR", "RRA",
|
|
"BVS", "ADC", "KIL", "RRA", "NOP", "ADC", "ROR", "RRA",
|
|
"SEI", "ADC", "NOP", "RRA", "NOP", "ADC", "ROR", "RRA",
|
|
"NOP", "STA", "NOP", "SAX", "STY", "STA", "STX", "SAX",
|
|
"DEY", "NOP", "TXA", "XAA", "STY", "STA", "STX", "SAX",
|
|
"BCC", "STA", "KIL", "AHX", "STY", "STA", "STX", "SAX",
|
|
"TYA", "STA", "TXS", "TAS", "SHY", "STA", "SHX", "AHX",
|
|
"LDY", "LDA", "LDX", "LAX", "LDY", "LDA", "LDX", "LAX",
|
|
"TAY", "LDA", "TAX", "LAX", "LDY", "LDA", "LDX", "LAX",
|
|
"BCS", "LDA", "KIL", "LAX", "LDY", "LDA", "LDX", "LAX",
|
|
"CLV", "LDA", "TSX", "LAS", "LDY", "LDA", "LDX", "LAX",
|
|
"CPY", "CMP", "NOP", "DCP", "CPY", "CMP", "DEC", "DCP",
|
|
"INY", "CMP", "DEX", "AXS", "CPY", "CMP", "DEC", "DCP",
|
|
"BNE", "CMP", "KIL", "DCP", "NOP", "CMP", "DEC", "DCP",
|
|
"CLD", "CMP", "NOP", "DCP", "NOP", "CMP", "DEC", "DCP",
|
|
"CPX", "SBC", "NOP", "ISC", "CPX", "SBC", "INC", "ISC",
|
|
"INX", "SBC", "NOP", "SBC", "CPX", "SBC", "INC", "ISC",
|
|
"BEQ", "SBC", "KIL", "ISC", "NOP", "SBC", "INC", "ISC",
|
|
"SED", "SBC", "NOP", "ISC", "NOP", "SBC", "INC", "ISC"
|
|
];
|
|
|
|
immutable OP_NAMES_65C02 = [
|
|
"BRK", "ORA", "NOP", "NOP", "TSB", "ORA", "ASL", "NOP",
|
|
"PHP", "ORA", "ASL", "NOP", "TSB", "ORA", "ASL", "NOP",
|
|
"BPL", "ORA", "ORA", "NOP", "TRB", "ORA", "ASL", "NOP",
|
|
"CLC", "ORA", "INC", "NOP", "TRB", "ORA", "ASL", "NOP",
|
|
"JSR", "AND", "NOP", "NOP", "BIT", "AND", "ROL", "NOP",
|
|
"PLP", "AND", "ROL", "NOP", "BIT", "AND", "ROL", "NOP",
|
|
"BMI", "AND", "AND", "NOP", "BIT", "AND", "ROL", "NOP",
|
|
"SEC", "AND", "DEC", "NOP", "BIT", "AND", "ROL", "NOP",
|
|
"RTI", "EOR", "NOP", "NOP", "NOP", "EOR", "LSR", "NOP",
|
|
"PHA", "EOR", "LSR", "NOP", "JMP", "EOR", "LSR", "NOP",
|
|
"BVC", "EOR", "EOR", "NOP", "NOP", "EOR", "LSR", "NOP",
|
|
"CLI", "EOR", "PHY", "NOP", "NOP", "EOR", "LSR", "NOP",
|
|
"RTS", "ADC", "NOP", "NOP", "STZ", "ADC", "ROR", "NOP",
|
|
"PLA", "ADC", "ROR", "NOP", "JMP", "ADC", "ROR", "NOP",
|
|
"BVS", "ADC", "ADC", "NOP", "STZ", "ADC", "ROR", "NOP",
|
|
"SEI", "ADC", "PLY", "NOP", "JMP", "ADC", "ROR", "NOP",
|
|
"BRA", "STA", "NOP", "NOP", "STY", "STA", "STX", "NOP",
|
|
"DEY", "BIT", "TXA", "NOP", "STY", "STA", "STX", "NOP",
|
|
"BCC", "STA", "STA", "NOP", "STY", "STA", "STX", "NOP",
|
|
"TYA", "STA", "TXS", "NOP", "STZ", "STA", "STZ", "NOP",
|
|
"LDY", "LDA", "LDX", "NOP", "LDY", "LDA", "LDX", "NOP",
|
|
"TAY", "LDA", "TAX", "NOP", "LDY", "LDA", "LDX", "NOP",
|
|
"BCS", "LDA", "LDA", "NOP", "LDY", "LDA", "LDX", "NOP",
|
|
"CLV", "LDA", "TSX", "NOP", "LDY", "LDA", "LDX", "NOP",
|
|
"CPY", "CMP", "NOP", "NOP", "CPY", "CMP", "DEC", "NOP",
|
|
"INY", "CMP", "DEX", "NOP", "CPY", "CMP", "DEC", "NOP",
|
|
"BNE", "CMP", "CMP", "NOP", "NOP", "CMP", "DEC", "NOP",
|
|
"CLD", "CMP", "PHX", "NOP", "NOP", "CMP", "DEC", "NOP",
|
|
"CPX", "SBC", "NOP", "NOP", "CPX", "SBC", "INC", "NOP",
|
|
"INX", "SBC", "NOP", "NOP", "CPX", "SBC", "INC", "NOP",
|
|
"BEQ", "SBC", "SBC", "NOP", "NOP", "SBC", "INC", "NOP",
|
|
"SED", "SBC", "PLX", "NOP", "NOP", "SBC", "INC", "NOP"
|
|
];
|
|
|
|
|
|
// Addressing modes.
|
|
|
|
immutable ADDR_MODES_6502 = [
|
|
IMP, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
|
|
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
|
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
|
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
|
|
ABS, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
|
|
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
|
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
|
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
|
|
IMP, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
|
|
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
|
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
|
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
|
|
IMP, IZX, KIL, IZX, ZP, ZP, ZP, ZP,
|
|
IMP, IMM, IMP, IMM, IND, ABS, ABS, ABS,
|
|
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
|
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
|
|
IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
|
|
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
|
REL, IZY, KIL, IZY, ZPX, ZPX, ZPY, ZPY,
|
|
IMP, ABY, IMP, ABY, ABX, ABX, ABY, ABY,
|
|
IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
|
|
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
|
REL, IZY, KIL, IZY, ZPX, ZPX, ZPY, ZPY,
|
|
IMP, ABY, IMP, ABY, ABX, ABX, ABY, ABY,
|
|
IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
|
|
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
|
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
|
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX,
|
|
IMM, IZX, IMM, IZX, ZP, ZP, ZP, ZP,
|
|
IMP, IMM, IMP, IMM, ABS, ABS, ABS, ABS,
|
|
REL, IZY, KIL, IZY, ZPX, ZPX, ZPX, ZPX,
|
|
IMP, ABY, IMP, ABY, ABX, ABX, ABX, ABX
|
|
];
|
|
|
|
immutable ADDR_MODES_65C02 = [
|
|
IMP, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
|
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
|
REL, IZY, ZPI, NP1, ZP, ZPX, ZPX, NP1,
|
|
IMP, ABY, IMP, NP1, ABS, ABX, ABX, NP1,
|
|
ABS, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
|
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
|
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
|
|
IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1,
|
|
IMP, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
|
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
|
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
|
|
IMP, ABY, IMP, NP1, NP8, ABX, ABX, NP1,
|
|
IMP, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
|
IMP, IMM, IMP, NP1, IND, ABS, ABS, NP1,
|
|
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
|
|
IMP, ABY, IMP, NP1, ABI, ABX, ABX, NP1,
|
|
REL, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
|
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
|
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPY, NP1,
|
|
IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1,
|
|
IMM, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
|
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
|
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPY, NP1,
|
|
IMP, ABY, IMP, NP1, ABX, ABX, ABY, NP1,
|
|
IMM, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
|
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
|
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
|
|
IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1,
|
|
IMM, IZX, IMM, NP1, ZP, ZP, ZP, NP1,
|
|
IMP, IMM, IMP, NP1, ABS, ABS, ABS, NP1,
|
|
REL, IZY, ZPI, NP1, ZPX, ZPX, ZPX, NP1,
|
|
IMP, ABY, IMP, NP1, ABX, ABX, ABX, NP1
|
|
];
|
|
|
|
|
|
// Page-crossing extra cycles.
|
|
|
|
immutable EXTRA_CYCLES_6502 = [
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
|
];
|
|
|
|
immutable EXTRA_CYCLES_65C02 = [
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
|
];
|
|
|
|
|
|
// Custom string formatting.
|
|
|
|
enum HEX_DIGITS = "0123456789abcdef";
|
|
|
|
string Hex1(int dec)
|
|
{
|
|
return HEX_DIGITS[dec..dec+1];
|
|
}
|
|
|
|
string Hex2(int dec)
|
|
{
|
|
int highNybble = (dec & 0xF0) >> 4;
|
|
int lowNybble = dec & 0x0F;
|
|
|
|
return HEX_DIGITS[highNybble..highNybble+1] ~
|
|
HEX_DIGITS[lowNybble..lowNybble+1];
|
|
}
|
|
|
|
string Fmt(string f, string[] p ...)
|
|
{
|
|
if (!p.length) return "ERROR";
|
|
string ret;
|
|
size_t last;
|
|
size_t other;
|
|
for (size_t i = 0; i < f.length; i++)
|
|
{
|
|
if (f[i] == '#')
|
|
{
|
|
if (other == p.length) return "ERROR";
|
|
ret ~= f[last..i] ~ p[other++];
|
|
last = i + 1;
|
|
}
|
|
}
|
|
return ret ~ f[last..$];
|
|
}
|
|
|
|
|
|
//alias Cpu!("6502", false, false) T1;
|
|
//alias Cpu!("6502", false, true) T2;
|
|
//alias Cpu!("6502", true, false) T3;
|
|
//alias Cpu!("6502", true, true) T4;
|
|
//alias Cpu!("65C02", false, false) T5;
|
|
//alias Cpu!("65C02", false, true) T6;
|
|
//alias Cpu!("65C02", true, false) T7;
|
|
//alias Cpu!("65C02", true, true) T8;
|
|
|
|
/+
|
|
void main()
|
|
{
|
|
import std.stdio;
|
|
writeln(OpBody(0x9d, "6502", true, false));
|
|
}
|
|
+/
|