372 lines
10 KiB
D
372 lines
10 KiB
D
import std.stdio, std.string, std.exception;
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import test.d6502.base, test.d6502.cpu;
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auto setup_vectors(T)(bool res, bool nmi, bool irq)
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{
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auto setup(ubyte opcode, CpuInfo cpu, Block[] data, OpInfo info,
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string msg, TestSetup* next)
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{
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mixin testCallNext;
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setPC(cpu, 0xfd00);
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auto ndata = [Block(0xfd00, [0xea, 0xea]),
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Block(0xfe35, [0xea, 0xea])];
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if (res)
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callNext("RESET ", ndata ~
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[Block(0xfffa, [0x00, 0xff, 0x35, 0xfe, 0x80, 0xff])]);
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else if (nmi)
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callNext("NMI ", ndata ~
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[Block(0xfffa, [0x35, 0xfe, 0x40, 0xff, 0x80, 0xff])]);
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else if (irq && !getFlag(cpu, Flag.I))
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callNext("IRQ ", ndata ~
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[Block(0xfffa, [0x00, 0xff, 0x40, 0xff, 0x35, 0xfe])]);
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else
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callNext("NOP ", ndata);
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}
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return connect(setup_mask_flags(), setup_flag(Flag.I), TestSetup(&setup));
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}
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auto accesses_reset(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto sp = getSP(cpu);
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auto sp1 = pageWrapAdd(sp, -1);
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auto sp2 = pageWrapAdd(sp, -2);
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cycles = 7;
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return If!(strict)(
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[Bus(Action.READ, pc),
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Bus(Action.READ, pc),
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Bus(Action.READ, sp),
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Bus(Action.READ, sp1),
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Bus(Action.READ, sp2)]) ~
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[Bus(Action.READ, 0xfffc),
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Bus(Action.READ, 0xfffd)];
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}
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auto accesses_nmi(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto sp = getSP(cpu);
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auto sp1 = pageWrapAdd(sp, -1);
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auto sp2 = pageWrapAdd(sp, -2);
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cycles = 7;
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return If!(strict)(
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[Bus(Action.READ, pc),
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Bus(Action.READ, pc)]) ~
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[Bus(Action.WRITE, sp),
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Bus(Action.WRITE, sp1),
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Bus(Action.WRITE, sp2),
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Bus(Action.READ, 0xfffa),
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Bus(Action.READ, 0xfffb)];
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}
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auto accesses_irq(T)(T cpu, ref TestMemory mem, out int cycles)
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if (isCpu!T)
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{
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auto pc = getPC(cpu);
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auto sp = getSP(cpu);
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auto sp1 = pageWrapAdd(sp, -1);
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auto sp2 = pageWrapAdd(sp, -2);
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cycles = 7;
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return If!(strict)(
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[Bus(Action.READ, pc),
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Bus(Action.READ, pc)]) ~
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[Bus(Action.WRITE, sp),
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Bus(Action.WRITE, sp1),
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Bus(Action.WRITE, sp2),
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Bus(Action.READ, 0xfffe),
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Bus(Action.READ, 0xffff)];
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}
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auto check_signal_timing(T)(bool res, bool nmi, bool irq, busreport report)
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{
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auto setup(ubyte opcode, CpuInfo cpu, Block[] data, OpInfo info,
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string msg, TestSetup* next)
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{
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mixin testCallNext;
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auto testcpu = makeCpu!T(cpu);
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auto mem = TestMemory(data);
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if (res) testcpu.signals.triggerReset();
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if (nmi) testcpu.signals.triggerNMI();
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if (irq) testcpu.signals.assertIRQ();
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int expCycles, dummy;
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Bus[] expBus;
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auto accesses_after = [Bus(Action.READ, 0xfe35)] ~
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If!(strict)([Bus(Action.READ, 0xfe36)]);
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if (res)
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expBus = accesses_reset(testcpu, mem, expCycles) ~
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accesses_after;
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else if (nmi)
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expBus = accesses_nmi(testcpu, mem, expCycles) ~
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accesses_after;
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else if (irq && !getFlag(testcpu, Flag.I))
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expBus = accesses_irq(testcpu, mem, expCycles) ~
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accesses_after;
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else
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expBus = accesses_reg(testcpu, mem, dummy);
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expCycles += 2;
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expBus = expBus ~ new Bus[9 - expBus.length];
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connectMem(testcpu, mem);
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auto actualBus = recordBus(testcpu, 9);
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auto actualCycles = recordCycles(testcpu);
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runOneOpcode(testcpu);
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report(actualCycles, actualBus, expCycles, expBus,
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opcode, T.stringof ~ " | " ~ msg);
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callNext();
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}
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return TestSetup(&setup);
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}
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auto expect_int(T)(bool res, bool nmi, bool irq)
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{
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void expect(ref Expected expected, const OpInfo info)
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{
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with(expected)
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{
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if (res || nmi || (irq && !getFlag(cpu, Flag.I)))
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{
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ushort ret = cast(ushort)(getPC(cpu));
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if (!res)
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mem[getSP(cpu)] = addrHi(ret);
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decSP(cpu);
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if (!res)
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mem[getSP(cpu)] = addrLo(ret);
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decSP(cpu);
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if (!res)
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mem[getSP(cpu)] = getStatus(cpu) & ~0x10;
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decSP(cpu);
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setPC(cpu, 0xfe36);
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setFlag(cpu, Flag.I);
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if (isCMOS!T) clearFlag(cpu, Flag.D);
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}
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else
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{
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setPC(cpu, 0xfd01);
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}
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}
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}
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return &expect;
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}
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auto check_signal(T)(bool res, bool nmi, bool irq, testreport report)
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{
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auto setup(ubyte opcode, CpuInfo cpu, Block[] data, OpInfo info,
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string msg, TestSetup* next)
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{
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mixin testCallNext;
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auto testcpu = makeCpu!T(cpu);
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auto mem = TestMemory(data);
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auto expected = Expected(cpu, mem);
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expect_int!T(res, nmi, irq)(expected, info);
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connectMem(testcpu, mem);
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if (res) testcpu.signals.triggerReset();
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if (nmi) testcpu.signals.triggerNMI();
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if (irq) testcpu.signals.assertIRQ();
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runOneOpcode(testcpu);
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auto cpuResult = CpuInfo.fromCpu(testcpu);
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report(opcode, expected, cpuResult, mem, T.stringof ~ " | " ~ msg);
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callNext();
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}
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return TestSetup(&setup);
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}
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void test_signals(T)()
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{
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void foo(T)(bool res, bool nmi, bool irq)
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{
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auto run = connect(setup_vectors!T(res, nmi, irq),
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check_signal_timing!T(res, nmi, irq, report_timing_debug()));
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run.run(0xea);
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}
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void bar(T)(bool res, bool nmi, bool irq)
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{
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auto run = connect(setup_vectors!T(res, nmi, irq),
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check_signal!T(res, nmi, irq, report_debug()));
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run.run(0xea);
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}
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foreach (res; [false, true])
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{
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foreach (nmi; [false, true])
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{
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foreach (irq; [false, true])
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{
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foo!T(res, nmi, irq);
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bar!T(res, nmi, irq);
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}
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}
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}
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}
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void test_cli_delay(T)()
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{
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void run_test(ubyte opcode2, ushort delayPC, string name)
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{
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auto mem = TestMemory(Block(0xfd00, [0x58, opcode2, 0xea]),
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Block(0xfe35, [0xea, 0xea, 0xea]),
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Block(0xfffe, [0x35, 0xfe]));
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auto cpu = makeCpu!T();
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setPC(cpu, 0xfd00);
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setFlag(cpu, Flag.I);
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cpu.signals.assertIRQ();
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connectMem(cpu, mem);
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runOneOpcode(cpu);
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runOneOpcode(cpu);
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runOneOpcode(cpu);
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static if (isCMOS!T) { auto expPC = 0xfe37; }
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else { auto expPC = delayPC; }
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if (getPC(cpu) != expPC)
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{
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writeln(format(name ~ " expected pc $%0.4x got $%0.4x",
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expPC, getPC(cpu)));
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throw new TestException("cli_delay_1");
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}
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}
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run_test(0xea, 0xfe36, "CLI-delay");
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run_test(0x78, 0xfd03, "CLI-delay-allows-SEI");
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run_test(0x58, 0xfe36, "multiple-CLI");
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}
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void test_plp_delay(T)()
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{
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void run_test(ubyte opcode2, ushort delayPC, string name)
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{
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auto mem = TestMemory(Block(0x1fe, [0x00, 0x00]),
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Block(0xfd00, [0x28, opcode2, 0xea]),
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Block(0xfe35, [0xea, 0xea, 0xea]),
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Block(0xfffe, [0x35, 0xfe]));
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auto cpu = makeCpu!T();
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setPC(cpu, 0xfd00);
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setSP(cpu, 0x01fd);
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setFlag(cpu, Flag.I);
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cpu.signals.assertIRQ();
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connectMem(cpu, mem);
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runOneOpcode(cpu);
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runOneOpcode(cpu);
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runOneOpcode(cpu);
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static if (isCMOS!T) { auto expPC = 0xfe37; }
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else { auto expPC = delayPC; }
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if (getPC(cpu) != expPC)
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{
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writeln(format(name ~ " expected pc $%0.4x got $%0.4x",
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expPC, getPC(cpu)));
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throw new TestException("cli_delay_1");
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}
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}
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run_test(0xea, 0xfe36, "PLP-delay");
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run_test(0x78, 0xfd03, "PLP-delay-allows-SEI");
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run_test(0x28, 0xfe36, "multiple-PLP");
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}
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void test_sei_interruptable(T)()
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{
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auto mem = TestMemory(Block(0xfd00, [0x78, 0xea, 0xea]),
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Block(0xfe35, [0xea, 0xea, 0xea]),
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Block(0xfffe, [0x35, 0xfe]));
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auto cpu = makeCpu!T();
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setPC(cpu, 0xfd00);
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clearFlag(cpu, Flag.I);
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cpu.signals.assertIRQ();
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connectMem(cpu, mem);
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runOneOpcode(cpu);
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if (getPC(cpu) != 0xfe36)
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{
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writeln(format("SEI expected pc $fe36 got $%0.4x", getPC(cpu)));
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throw new TestException("cli_delay_1");
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}
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}
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void test_nmi_brk(T)()
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{
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class RunTest
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{
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uint ticks, nmiTick;
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T cpu;
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void tick()
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{
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if (ticks == nmiTick) cpu.signals.triggerNMI();
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ticks++;
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}
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this(uint nmiTick)
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{
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this.nmiTick = nmiTick;
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auto mem = TestMemory(Block(0xfd00, [0x00, 0xea]),
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Block(0xfe35, [0xea]),
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Block(0xff45, [0xea]),
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Block(0xfffa, [0x45, 0xff]),
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Block(0xfffe, [0x35, 0xfe]));
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cpu = makeCpu!T();
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setPC(cpu, 0xfd00);
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connectMem(cpu, mem);
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cpu.clock.dtick = &tick;
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runOneOpcode(cpu);
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ushort expPC;
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if (nmiTick < 5 && isNMOS!T)
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expPC = 0xff45;
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else
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expPC = 0xfe35;
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if (getPC(cpu) != expPC)
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{
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writeln(format("nmi-brk tick %d expected $%0.4x got $%0.4x",
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nmiTick, expPC, getPC(cpu)));
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throw new TestException("nmi-brk");
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}
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}
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}
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foreach (t; 0..6)
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{
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auto dummy = new RunTest(t);
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}
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}
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void main()
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{
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alias CPU!("6502") T1;
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writeln("Testing signals, 6502");
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test_signals!T1();
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test_cli_delay!T1();
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test_plp_delay!T1();
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test_sei_interruptable!T1();
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version(Cumulative) {}
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else { test_nmi_brk!T1(); }
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alias CPU!("65C02") T2;
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writeln("Testing signals, 65C02");
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test_signals!T2();
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test_cli_delay!T2();
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test_plp_delay!T2();
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test_sei_interruptable!T2();
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version(Cumulative) {}
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else { test_nmi_brk!T2(); }
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}
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