mirror of
https://github.com/edmccard/twoapple-reboot.git
synced 2024-05-28 20:41:28 +00:00
1153 lines
29 KiB
D
1153 lines
29 KiB
D
module cpu.ctfe_d6502;
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import cpu.data_d6502;
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// The following versions are mutually exclusive.
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// OpDelegates: each opcode is a method of the Cpu class.
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version(OpDelegates)
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{
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enum versionCheck = 1;
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enum opArray = true;
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}
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// OpFunctions: each opcode is a free function with a Cpu argument.
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version(OpFunctions)
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{
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enum versionCheck = 2;
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enum opArray = true;
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// With free functions, strict and cumulative need to be set by
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// version.
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version(Strict)
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enum vStrict = true;
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else
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enum vStrict = false;
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version(Cumulative)
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enum vCumulative = true;
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else
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enum vCumulative = false;
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}
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// OpSwitch: each opcode is inlined in a 256-case switch.
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version(OpSwitch)
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{
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enum versionCheck = 3;
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enum opArray = false;
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}
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/*
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* OpNestedSwitch: each opcode is inlined in a nested switch.
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*
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* (The outer one switches on the high byte, with each case switching
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* on the low byte.)
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*/
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version(OpNestedSwitch)
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{
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enum versionCheck = 4;
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enum opArray = false;
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}
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// At least one of the previous versions must be specified.
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static if (!__traits(compiles, { bool b = opArray; })) enum opArray = 0;
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static assert (versionCheck);
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string OpArrayDef()
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{
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version(OpDelegates)
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return q{void delegate()[256] opcodes;};
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else version(OpFunctions)
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return q{void function(typeof(this))[256] opcodes;};
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else
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return "";
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}
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string OpArrayInit()
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{
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static if (!opArray) return "";
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else
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{
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string ret;
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foreach (op; 0..256)
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{
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version(OpDelegates)
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ret ~= Fmt("opcodes[0x#] = &opcode_#;\n",
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Hex2(op), Hex2(op));
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version(OpFunctions)
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ret ~= Fmt("opcodes[0x#] = &opcode_#!(typeof(this));\n",
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Hex2(op), Hex2(op));
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}
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return ret;
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}
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}
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string OpBodies(string chip, bool strict, bool cumulative)
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{
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static if (!opArray) return "";
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else
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{
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string ret;
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foreach (op; 0..256)
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{
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version(OpDelegates)
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ret ~= "final void opcode_" ~ Hex2(op) ~ "()\n{\n" ~
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If!(cumulative)("int cycles = 1;\n") ~
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OpBody(op, chip, strict, cumulative) ~ "}\n";
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version(OpFunctions)
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ret ~= "void opcode_" ~ Hex2(op) ~
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"(T)(T cpu) if (is" ~ chip ~ "!T)\n{\n" ~
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If!(cumulative)("int cycles = 1;\n") ~
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OpBody(op, chip, strict, cumulative) ~ "}\n";
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}
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/+
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foreach (op; 13..256)
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version(OpDelegates)
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ret ~= "final void opcode_" ~ Hex2(op) ~ "()\n{\n" ~
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If!(cumulative)("int cycles = 1;\n") ~
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"" ~ "}\n";
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version(OpFunctions)
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ret ~= "void opcode_" ~ Hex2(op) ~
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"(T)(T cpu) if (is" ~ chip ~ "!T)\n{\n" ~
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If!(cumulative)("int cycles = 1;\n") ~
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"" ~ "}\n";
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+/
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return ret;
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}
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}
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string OpExecute(string chip, bool strict, bool cumulative)
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{
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version(OpDelegates)
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return q{opcodes[opcode]();};
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version(OpFunctions)
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return q{opcodes[opcode](this);};
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version(OpSwitch)
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return Switch256(chip, strict, cumulative);
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version(OpNestedSwitch)
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return Switch16x16(chip, strict, cumulative);
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}
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string Switch256(string chip, bool strict, bool cumulative)
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{
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string ret = "final switch (opcode)\n{\n";
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foreach (op; 0..256)
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ret ~= "case 0x" ~ Hex2(op) ~ ":\n" ~
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OpBody(op, chip, strict, cumulative) ~ "break;\n";
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return ret ~ "}\n";
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}
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string Switch16x16(string chip, bool strict, bool cumulative)
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{
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string ret = "final switch (opcode & 0xF0)\n{\n";
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foreach (opHi; 0..16)
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{
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ret ~= "case 0x" ~ Hex1(opHi) ~ "0:\n" ~
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"final switch(opcode & 0x0F)\n{\n";
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foreach (opLo; 0..16)
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{
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int op = opLo | (opHi << 4);
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ret ~= "case 0x0" ~ Hex1(opLo) ~ ":\n" ~
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OpBody(op, chip, strict, cumulative) ~
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"break;\n";
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}
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ret ~= "}\nbreak;\n";
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}
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return ret ~ "}\n";
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}
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string OpBody(int op, string chip, bool s, bool c)
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{
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bool nmos = (chip == "6502");
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final switch (opName(op, chip))
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{
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case "BRK":
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return Break(s, c) ~
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Done(c);
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case "RTI":
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return "";
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case "JSR":
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return JumpSub(s, c) ~
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Done(c);
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case "RTS":
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return RetSub(s, c) ~
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Done(c);
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case "JMP":
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return Jump(op, chip, s, c) ~
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Done(c);
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case "KIL":
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return Attr("PC") ~ "--;\n" ~
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Done(c);
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case "BPL":
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return Branch("!(" ~ Attr("N") ~ " & 0x80)", nmos, s, c) ~
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Done(c);
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case "BMI":
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return Branch("(" ~ Attr("N") ~ " & 0x80)", nmos, s, c) ~
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Done(c);
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case "BVC":
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return Branch("!" ~ Attr("V"), nmos, s, c) ~
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Done(c);
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case "BVS":
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return Branch(Attr("V"), nmos, s, c) ~
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Done(c);
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case "BRA":
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return Branch("true", nmos, s, c) ~
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Done(c);
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case "BCC":
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return Branch("!" ~ Attr("C"), nmos, s, c) ~
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Done(c);
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case "BCS":
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return Branch(Attr("C"), nmos, s, c) ~
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Done(c);
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case "BNE":
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return Branch(Attr("Z"), nmos, s, c) ~
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Done(c);
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case "BEQ":
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return Branch("!" ~ Attr("Z"), nmos, s, c) ~
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Done(c);
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case "CLC":
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return AddrIMP(s, c) ~
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ClearFlag("C") ~
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Done(c);
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case "SEC":
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return AddrIMP(s, c) ~
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SetFlag("C") ~
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Done(c);
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case "CLI":
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return AddrIMP(s, c) ~
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ClearFlag("I") ~
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Done(c);
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case "SEI":
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return AddrIMP(s, c) ~
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SetFlag("I") ~
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Done(c);
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case "CLV":
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return AddrIMP(s, c) ~
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ClearFlag("V") ~
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Done(c);
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case "CLD":
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return AddrIMP(s, c) ~
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ClearFlag("D") ~
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Done(c);
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case "SED":
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return AddrIMP(s, c) ~
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SetFlag("D") ~
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Done(c);
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case "NOP":
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return Nop(op, chip, s, c) ~
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Done(c);
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case "TAX":
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return Transfer(op, "A", "X", s, c) ~
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Done(c);
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case "TXA":
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return Transfer(op, "X", "A", s, c) ~
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Done(c);
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case "TAY":
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return Transfer(op, "A", "Y", s, c) ~
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Done(c);
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case "TYA":
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return Transfer(op, "Y", "A", s, c) ~
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Done(c);
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case "TSX":
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return Transfer(op, "S", "X", s, c) ~
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Done(c);
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case "TXS":
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return Transfer(op, "X", "S", s, c) ~
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Done(c);
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case "DEX":
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return AddrIMP(s, c) ~
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Dec(Attr("X")) ~
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Done(c);
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case "DEY":
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return AddrIMP(s, c) ~
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Dec(Attr("Y")) ~
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Done(c);
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case "INX":
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return AddrIMP(s, c) ~
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Inc(Attr("X")) ~
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Done(c);
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case "INY":
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return AddrIMP(s, c) ~
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Inc(Attr("Y")) ~
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Done(c);
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case "PHP":
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return AddrIMP(s, c) ~
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Push(Attr("statusToByte()"), s, c) ~
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Done(c);
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case "PLP":
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return AddrIMP(s, c) ~
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PullStatus(s, c) ~
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Done(c);
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case "PLA":
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return PullReg("A", s, c) ~
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Done(c);
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case "PLX":
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return PullReg("X", s, c) ~
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Done(c);
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case "PLY":
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return PullReg("Y", s, c) ~
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Done(c);
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case "PHA":
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return PushReg("A", s, c) ~
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Done(c);
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case "PHX":
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return PushReg("X", s, c) ~
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Done(c);
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case "PHY":
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return PushReg("Y", s, c) ~
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Done(c);
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case "LDA":
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return Load(op, "A", chip, s, c) ~
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Done(c);
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case "LDX":
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return Load(op, "X", chip, s, c) ~
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Done(c);
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case "LDY":
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return Load(op, "Y", chip, s, c) ~
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Done(c);
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case "STA":
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return Store(op, "A", chip, s, c) ~
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Done(c);
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case "STX":
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return Store(op, "X", chip, s, c) ~
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Done(c);
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case "STY":
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return Store(op, "Y", chip, s, c) ~
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Done(c);
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case "STZ":
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return "";
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case "BIT":
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return Bit(op, chip, s, c) ~
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Done(c);
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case "CMP":
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return Compare(op, "A", chip, s, c) ~
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Done(c);
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case "CPX":
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return Compare(op, "X", chip, s, c) ~
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Done(c);
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case "CPY":
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return Compare(op, "Y", chip, s, c) ~
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Done(c);
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case "ORA":
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return Logic(op, "|=", chip, s, c) ~
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Done(c);
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case "AND":
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return Logic(op, "&=", chip, s, c) ~
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Done(c);
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case "EOR":
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return Logic(op, "^=", chip, s, c) ~
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Done(c);
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case "ADC":
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return Add(op, chip, s, c) ~
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Done(c);
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case "SBC":
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return Sub(op, chip, s, c) ~
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Done(c);
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case "ASL":
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if (op == 0x0a)
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return AddrIMP(s, c) ~ ShiftLeft(Attr("A")) ~ Done(c);
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else
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return RMW(op, ShiftLeft("data"), chip, s, c) ~ Done(c);
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case "ROL":
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if (op == 0x2a)
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return AddrIMP(s, c) ~ RotateLeft(Attr("A")) ~ Done(c);
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else
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return RMW(op, RotateLeft("data"), chip, s, c) ~ Done(c);
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case "LSR":
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if (op == 0x4a)
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return AddrIMP(s, c) ~ ShiftRight(Attr("A")) ~ Done(c);
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else
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return RMW(op, ShiftRight("data"), chip, s, c) ~ Done(c);
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case "ROR":
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if (op == 0x6a)
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return AddrIMP(s, c) ~ ShiftRight(Attr("A")) ~ Done(c);
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else
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return RMW(op, RotateRight("data"), chip, s, c) ~ Done(c);
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case "INC":
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if (op == 0x1a)
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return AddrIMP(s, c) ~ Inc(Attr("A")) ~ Done(c);
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else
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return RMW(op, Inc("data"), chip, s, c) ~ Done(c);
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case "DEC":
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if (op == 0x3a)
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return AddrIMP(s, c) ~ Dec(Attr("A")) ~ Done(c);
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else
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return RMW(op, Dec("data"), chip, s, c) ~ Done(c);
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case "TRB":
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return "";
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case "TSB":
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return "";
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case "LAS":
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return "";
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case "LAX":
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return ""; // address modes
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case "SAX":
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return "";
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case "ANC":
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return "";
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case "ALR":
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return "";
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case "ARR":
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return "";
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case "AXS":
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return "";
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case "AHX":
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return "";
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case "SHY":
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return "";
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case "SHX":
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return "";
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case "TAS":
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return "";
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case "XAA":
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return "";
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case "SLO":
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return "";
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case "RLA":
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return "";
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case "SRE":
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return "";
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case "RRA":
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return "";
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case "DCP":
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return "";
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case "ISC":
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return "";
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}
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}
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string AddrIMM(bool s, bool c)
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{
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return Local("ushort") ~ "address = " ~ Attr("PC") ~ "++;\n";
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}
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string AddrIMP(bool s, bool c)
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{
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return Peek(Attr("PC"), s, c);
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}
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string AddrZP(bool s, bool c)
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{
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return ReadOp(Local("ushort", "address"), c);
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}
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string AddrZPXY(string reg, string chip, bool s, bool c)
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{
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bool nmos = (chip == "6502");
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return ReadOp(Local("ushort", "base"), c) ~
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If!(nmos)(
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Peek("base", s, c),
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Peek(Attr("PC"), s, c)) ~
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Local("ushort") ~
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"address = cast(ubyte)(base + " ~ Attr(reg) ~ ");\n";
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}
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string AddrIZX(string chip, bool s, bool c)
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{
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bool nmos = (chip == "6502");
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return ReadOp(Local("ushort", "base"), c) ~
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If!(nmos)(
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Peek("base", s, c),
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Peek(Attr("PC"), s, c)) ~
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ReadWordZP("ushort", "address", "base + " ~ Attr("X"), c);
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}
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string AddrIZY(int op, string chip, bool s, bool c)
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{
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int exCyc = opExCyc(op, chip);
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bool nmos = (chip == "6502");
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return ReadOp("ubyte vector", c) ~
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ReadWordZP("ushort", "base", "vector", c) ~
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Local("ushort") ~
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"address = cast(ushort)(base + " ~ Attr("Y") ~ ");\n" ~
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CheckShortcut("address", Attr("PC"),
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exCyc, nmos, s, c);
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}
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string AddrABS(bool s, bool c)
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{
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return ReadWordOp("ushort", "address", c);
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}
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string AddrABXY(int op, string reg, string chip, bool s, bool c)
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{
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bool nmos = (chip == "6502");
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int exCyc = opExCyc(op, chip);
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string IDX = Attr(reg);
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return ReadWordOp("ushort", "base", c) ~
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Local("ushort") ~ "address = cast(ushort)(base + " ~ IDX ~ ");\n" ~
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CheckShortcut("address", Attr("PC"), exCyc, nmos, s, c);
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}
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string AddrZPI(bool s, bool c)
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{
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return ReadOp(Local("ushort", "base"), c) ~
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ReadWordZP("ushort", "address", "base", c);
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}
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string Branch(string check, bool nmos, bool s, bool c)
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{
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string PC = Attr("PC");
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return ReadOp(Local("ubyte", "op1"), c) ~
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"if (" ~ check ~ ")\n{\n" ~
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Peek(PC, s, c) ~
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Local("ushort", "base") ~ " = " ~ PC ~ ";\n" ~
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PC ~ " = cast(ushort)(" ~ PC ~ " + cast(byte)op1);\n" ~
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CheckShortcut(Attr("PC"), "base", 0, nmos, s, c) ~
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"}\n";
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}
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string CheckShortcut(string addr, string pc, int exCyc, bool nmos, bool s,
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bool c)
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{
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return "ushort guess = (base & 0xFF00) | cast(ubyte)" ~ addr ~ ";\n" ~
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"if (guess != " ~ addr ~ ")\n{\n" ~
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If!(nmos)(Peek("guess", s, c),
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Peek(pc, s, c)) ~
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"}\n" ~
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If!(exCyc)("else\n{\n" ~ Peek("address", s, c) ~ "}\n");
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}
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string Nop(int op, string chip, bool s, bool c)
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{
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auto mode = opMode(op, chip);
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if (mode == IMP || mode == NP1 || mode == NP8)
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return Address(op, chip, s, c);
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else
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return Address(op, chip, s, c) ~
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Peek("address", true, c);
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}
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string Break(bool s, bool c)
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{
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return AddrIMP(s, c) ~
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IncPC() ~
|
|
PushPC(s, c) ~
|
|
Push(Attr("statusToByte()"), s, c) ~
|
|
SetFlag("I") ~
|
|
ReadWord(Attr("PC"), "IRQ_VECTOR", c);
|
|
}
|
|
|
|
|
|
string RetSub(bool s, bool c)
|
|
{
|
|
return AddrIMP(s, c) ~
|
|
PullPC(s, c) ~
|
|
Peek(Attr("PC"), s, c) ~
|
|
IncPC();
|
|
}
|
|
|
|
|
|
string JumpSub(bool s, bool c)
|
|
{
|
|
string PC = Attr("PC");
|
|
|
|
return ReadOp(Local("ushort", "address"), c) ~
|
|
Peek("0x0100 + " ~ Attr("S"), s, c) ~
|
|
PushPC(s, c) ~
|
|
PreAccess(c) ~ "address |= (" ~ ReadRaw(PC ~ "++") ~ " << 8);\n" ~
|
|
PC ~ " = address;\n";
|
|
}
|
|
|
|
|
|
string Jump(int op, string chip, bool s, bool c)
|
|
{
|
|
bool nmos = (chip == "6502");
|
|
string PC = Attr("PC");
|
|
|
|
if (op == 0x4c)
|
|
return Address(op, chip, s, c) ~
|
|
PC ~ " = address;\n";
|
|
else if (op == 0x6c)
|
|
return ReadWordOp("ushort", "base", c) ~
|
|
If!(nmos)(
|
|
"",
|
|
Peek(PC, s, c)) ~
|
|
ReadWordBasic(PC, "base",
|
|
If!(nmos)(
|
|
"(base & 0xFF00) | cast(ubyte)(base + 1)",
|
|
"cast(ushort)(base + 1)"), c);
|
|
else if (op == 0x7c)
|
|
return ReadWordOp("ushort", "base", c) ~
|
|
Peek(PC, s, c) ~
|
|
ReadWord(PC, "cast(ushort)(base + " ~ Attr("X") ~ ")", c);
|
|
return "";
|
|
}
|
|
|
|
|
|
string ReadInto(string var, string action, string addr, bool c)
|
|
{
|
|
return PreAccess(c) ~
|
|
var ~ " " ~ action ~ " " ~ ReadRaw("(" ~ addr ~ ")") ~ ";\n";
|
|
}
|
|
|
|
string ReadInto(string var, string addr, bool c)
|
|
{
|
|
return ReadInto(var, "=", addr, c);
|
|
}
|
|
|
|
string ReadOp(string var, bool c)
|
|
{
|
|
return ReadInto(var, Attr("PC") ~ "++", c);
|
|
}
|
|
|
|
string ReadRaw(string addr)
|
|
{
|
|
return Attr("memory") ~ ".read(" ~ addr ~")";
|
|
}
|
|
|
|
string ReadWordBasic(string type, string var, string addr1, string addr2,
|
|
bool c)
|
|
{
|
|
return PreAccess(c) ~
|
|
Local(type, var) ~ " = " ~ ReadRaw(addr1) ~ ";\n" ~
|
|
PreAccess(c) ~
|
|
var ~ " |= ((" ~ ReadRaw(addr2) ~ ") << 8);\n";
|
|
}
|
|
|
|
string ReadWordBasic(string var, string addr1, string addr2, bool c)
|
|
{
|
|
return ReadWordBasic("", var, addr1, addr2, c);
|
|
}
|
|
|
|
string ReadWord(string type, string var, string addr, bool c)
|
|
{
|
|
return ReadWordBasic(type, var, addr, "cast(ushort)(" ~ addr ~ " + 1)", c);
|
|
}
|
|
|
|
string ReadWord(string var, string addr, bool c)
|
|
{
|
|
return ReadWord("", var, addr, c);
|
|
}
|
|
|
|
string ReadWordZP(string type, string var, string addr, bool c)
|
|
{
|
|
return ReadWordBasic(type, var, "cast(ubyte)( " ~ addr ~ ")",
|
|
"cast(ubyte)(" ~ addr ~ " + 1)", c);
|
|
}
|
|
|
|
string ReadWordZP(string var, string addr, bool c)
|
|
{
|
|
return ReadWordZP("", var, addr, c);
|
|
}
|
|
|
|
string ReadWordOp(string type, string var, bool c)
|
|
{
|
|
string PC = Attr("PC");
|
|
|
|
return ReadWordBasic(type, var, PC ~ "++", PC ~ "++", c);
|
|
}
|
|
|
|
string ReadWordOp(string var, bool c)
|
|
{
|
|
return ReadWordOp("", var, c);
|
|
}
|
|
|
|
|
|
string Local(string type)
|
|
{
|
|
version(OpSwitch)
|
|
return "";
|
|
else version(OpNestedSwitch)
|
|
return "";
|
|
else
|
|
return type ~ " ";
|
|
}
|
|
|
|
string Local(string type, string var)
|
|
{
|
|
version(OpSwitch)
|
|
return var;
|
|
else version(OpNestedSwitch)
|
|
return var;
|
|
else
|
|
return type ~ " " ~ var;
|
|
}
|
|
|
|
|
|
string Transfer(int op, string source, string dest, bool s, bool c)
|
|
{
|
|
return AddrIMP(s, c) ~
|
|
Attr(dest) ~ " = " ~ Attr(source) ~ ";\n" ~
|
|
((op != 0x9a) ? SetNZ(Attr(dest)) : "");
|
|
}
|
|
|
|
|
|
string PullReg(string reg, bool s, bool c)
|
|
{
|
|
return AddrIMP(s, c) ~
|
|
PullInto(Attr(reg), s, c) ~
|
|
SetNZ(Attr(reg));
|
|
}
|
|
|
|
|
|
string PushReg(string reg, bool s, bool c)
|
|
{
|
|
return AddrIMP(s, c) ~
|
|
Push(Attr(reg), s, c);
|
|
}
|
|
|
|
|
|
string Load(int op, string reg, string chip, bool s, bool c)
|
|
{
|
|
return Address(op, chip, s, c) ~
|
|
ReadInto(Attr(reg), "address", c) ~
|
|
SetNZ(Attr(reg));
|
|
}
|
|
|
|
|
|
string Store(int op, string reg, string chip, bool s, bool c)
|
|
{
|
|
return Address(op, chip, s, c) ~
|
|
Write("address", Attr(reg), c);
|
|
}
|
|
|
|
|
|
string Compare(int op, string reg, string chip, bool s, bool c)
|
|
{
|
|
return Address(op, chip, s, c) ~
|
|
ReadInto(Local("ubyte", "data"), "address", c) ~
|
|
UpdateFlag("C", Attr(reg) ~ " >= data") ~
|
|
SetNZ("cast(ubyte)(" ~ Attr(reg) ~ " - data)");
|
|
}
|
|
|
|
|
|
string Bit(int op, string chip, bool s, bool c)
|
|
{
|
|
bool notImm = (opMode(op, chip) != IMM);
|
|
|
|
return Address(op, chip, s, c) ~
|
|
ReadInto(Local("ubyte", "data"), "address", c) ~
|
|
If!(notImm)(
|
|
Attr("N") ~ " = data;\n" ~
|
|
Attr("V") ~ " = ((data & 0x40) != 0);\n") ~
|
|
Attr("Z") ~ " = (" ~ Attr("A") ~ " & data);\n";
|
|
}
|
|
|
|
|
|
string Logic(int op, string action, string chip, bool s, bool c)
|
|
{
|
|
return Address(op, chip, s, c) ~
|
|
ReadInto(Attr("A"), action, "address", c) ~
|
|
SetNZ(Attr("A"));
|
|
}
|
|
|
|
|
|
string Add(int op, string chip, bool s, bool c)
|
|
{
|
|
return Address(op, chip, s, c) ~
|
|
ReadInto(Local("ubyte", "data"), "address", c) ~
|
|
"if (" ~ Attr("D") ~ ")\n{\n" ~
|
|
DecAdd(chip, s, c) ~
|
|
"}\nelse\n{\n" ~
|
|
HexAdd(chip, s, c) ~
|
|
"}\n";
|
|
}
|
|
|
|
string HexAdd(string chip, bool s, bool c)
|
|
{
|
|
string A = Attr("A"), C = Attr("C");
|
|
|
|
return "uint sum = " ~ A ~ " + data + " ~ C ~ ";\n" ~
|
|
Attr("V") ~
|
|
" = (!((" ~ A ~ " ^ data) & 0x80)) && ((data ^ sum) & 0x80);\n" ~
|
|
C ~ " = (sum > 0xFF);\n" ~
|
|
SetNZ(A ~ " = cast(ubyte)sum");
|
|
}
|
|
|
|
string DecAdd(string chip, bool s, bool c)
|
|
{
|
|
bool cmos = (chip != "6502");
|
|
string A = Attr("A"), C = Attr("C");
|
|
|
|
return "int a = " ~ A ~ ";\n" ~
|
|
"int al = (a & 0x0F) + (data & 0x0F) + " ~ C ~ ";\n" ~
|
|
"if (al >= 0x0A)\n" ~
|
|
"al = ((al + 0x06) & 0x0F) + 0x10;\n" ~
|
|
"a = (a & 0xF0) + (data & 0xF0) + al;\n" ~
|
|
If!(cmos)("",
|
|
Attr("N") ~ " = cast(ubyte)a;\n" ~
|
|
Attr("Z") ~ " = cast(ubyte)(" ~ A ~ " + data + " ~ C ~ ");\n") ~
|
|
Attr("V") ~
|
|
" = (!((" ~ A ~ " ^ data) & 0x80)) && ((data ^ a) & 0x80);\n" ~
|
|
"if (a >= 0xA0)\n" ~
|
|
"a = a + 0x60;\n" ~
|
|
C ~ " = (a >= 0x100);\n" ~
|
|
If!(cmos)(
|
|
SetNZ(A ~ " = cast(ubyte)a") ~ Peek(Attr("PC"), s, c),
|
|
A ~ " = cast(ubyte)a;\n");
|
|
}
|
|
|
|
|
|
string Sub(int op, string chip, bool s, bool c)
|
|
{
|
|
return Address(op, chip, s, c) ~
|
|
ReadInto(Local("ubyte", "data"), "address", c) ~
|
|
"if (" ~ Attr("D") ~ ")\n{\n" ~
|
|
DecSub(chip, s, c) ~
|
|
"}\nelse\n{\n" ~
|
|
HexSub(chip, s, c) ~
|
|
"}\n";
|
|
}
|
|
|
|
string HexSub(string chip, bool s, bool c)
|
|
{
|
|
string A = Attr("A"), C = Attr("C");
|
|
|
|
return "uint diff = " ~ A ~ " - data - !" ~ C ~ ";\n" ~
|
|
Attr("V") ~
|
|
" = ((" ~ A ~ " ^ diff) & 0x80) && ((" ~ A ~ " ^ data) & 0x80);\n" ~
|
|
C ~ " = (diff < 0x100);\n" ~
|
|
SetNZ(A ~ " = cast(ubyte)diff");
|
|
}
|
|
|
|
string DecSub(string chip, bool s, bool c)
|
|
{
|
|
return (chip == "6502" ? DecSubNMOS(s, c) : DecSubCMOS(s, c));
|
|
}
|
|
|
|
string DecSubNMOS(bool s, bool c)
|
|
{
|
|
string A = Attr("A"), C = Attr("C");
|
|
|
|
return "int a = " ~ A ~ ";\n" ~
|
|
"int al = (a & 0x0F) - (data & 0x0F) - !" ~ C ~ ";\n" ~
|
|
"if (al < 0)\n" ~
|
|
"al = ((al - 0x06) & 0x0F) - 0x10;\n" ~
|
|
"a = (a & 0xF0) - (data & 0xF0) + al;\n" ~
|
|
"if (a < 0)\n" ~
|
|
"a = a - 0x60;\n" ~
|
|
"uint diff = " ~ A ~ " - data - !" ~ C ~ ";\n" ~
|
|
Attr("V") ~
|
|
" = ((" ~ A ~ " ^ diff) & 0x80) && ((" ~ A ~ " ^ data) & 0x80);\n" ~
|
|
C ~ " = (diff < 0x100);\n" ~
|
|
SetNZ("cast(ubyte)diff") ~
|
|
A ~ " = cast(ubyte)a;\n";
|
|
}
|
|
|
|
string DecSubCMOS(bool s, bool c)
|
|
{
|
|
string A = Attr("A"), C = Attr("C");
|
|
|
|
return "int a = " ~ A ~ ";\n" ~
|
|
"int al = (a & 0x0F) - (data & 0x0F) - !" ~ C ~ ";\n" ~
|
|
"a = a - data - !" ~ C ~ ";\n" ~
|
|
"if (a < 0) a = a - 0x60;\n" ~
|
|
"if (al < 0) a = a - 0x06;\n" ~
|
|
"uint diff = " ~ A ~ " - data - !" ~ C ~ ";\n" ~
|
|
Attr("V") ~
|
|
" = ((" ~ A ~ " ^ diff) & 0x80) && ((" ~ A ~ " ^ data) & 0x80);\n" ~
|
|
C ~ " = (diff < 0x100);\n" ~
|
|
Peek(Attr("PC"), s, c) ~
|
|
SetNZ(A ~ " = cast(ubyte)a");
|
|
}
|
|
|
|
|
|
string Inc(string val)
|
|
{
|
|
return val ~ "++;\n" ~
|
|
SetNZ(val);
|
|
}
|
|
|
|
|
|
string Dec(string val)
|
|
{
|
|
return val ~ "--;\n" ~
|
|
SetNZ(val);
|
|
}
|
|
|
|
|
|
string ShiftLeft(string val)
|
|
{
|
|
return Attr("C") ~ " = (" ~ val ~ " > 0x7F);\n" ~
|
|
SetNZ(val ~ " = cast(ubyte)(" ~ val ~ " << 1)");
|
|
}
|
|
|
|
string RotateLeft(string val)
|
|
{
|
|
string C = Attr("C");
|
|
|
|
return "auto oldC = " ~ C ~ ";\n" ~
|
|
C ~ " = (" ~ val ~ " > 0x7f);\n" ~
|
|
SetNZ(val ~ " = cast(ubyte)(" ~ val ~ " << 1 | (oldC ? 1 : 0))");
|
|
}
|
|
|
|
string ShiftRight(string val)
|
|
{
|
|
return Attr("C") ~ " = ((" ~ val ~ " & 0x01) != 0);\n" ~
|
|
SetNZ(val ~ " = " ~ val ~ " >> 1");
|
|
}
|
|
|
|
string RotateRight(string val)
|
|
{
|
|
string C = Attr("C");
|
|
|
|
return "auto oldC = " ~ C ~ ";\n" ~
|
|
C ~ " = ((" ~ val ~ " & 0x01) != 0);\n" ~
|
|
SetNZ(val ~ " = (" ~ val ~ " >> 1 | (oldC ? 0x80 : 0))");
|
|
}
|
|
|
|
string RMW(int op, string action, string chip, bool s, bool c)
|
|
{
|
|
bool nmos = (chip == "6502");
|
|
|
|
return Address(op, chip, s, c) ~
|
|
ReadInto(Local("ubyte", "data"), "address", c) ~
|
|
If!(nmos)(Poke("address", "data", s, c),
|
|
Peek("address", s, c)) ~
|
|
action ~
|
|
Write("address", "data", c);
|
|
}
|
|
|
|
|
|
string Address(int op, string chip, bool s, bool c)
|
|
{
|
|
auto EXTRA_CYCLE = opExCyc(op, chip);
|
|
auto PC = Attr("PC");
|
|
|
|
final switch (opMode(op, chip))
|
|
{
|
|
case IMP:
|
|
return AddrIMP(s, c);
|
|
case IMM:
|
|
return AddrIMM(s, c);
|
|
case ZP:
|
|
return AddrZP(s, c);
|
|
case ZPX:
|
|
return AddrZPXY("X", chip, s, c);
|
|
case ZPY:
|
|
return AddrZPXY("Y", chip, s, c);
|
|
case IZX:
|
|
return AddrIZX(chip, s, c);
|
|
case IZY:
|
|
return AddrIZY(op, chip, s, c);
|
|
case ABS:
|
|
return AddrABS(s, c);
|
|
case ABX:
|
|
return AddrABXY(op, "X", chip, s, c);
|
|
case ABY:
|
|
return AddrABXY(op, "Y", chip, s, c);
|
|
case IND:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
case REL:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
case ZPI:
|
|
return AddrZPI(s, c);
|
|
case ABI:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
case NP1:
|
|
return "";
|
|
case NP8:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
case KIL:
|
|
return Local("ushort", "address") ~ " = 0;";
|
|
}
|
|
return "";
|
|
}
|
|
|
|
|
|
string PreAccess(bool cumulative)
|
|
{
|
|
return If!(cumulative)("++cycles;\n", Attr("clock") ~ ".tick();\n");
|
|
}
|
|
|
|
string Peek(string addr, bool strict, bool cumulative)
|
|
{
|
|
return PreAccess(cumulative) ~
|
|
If!(strict)(Attr("memory") ~ ".read(" ~ addr ~");\n");
|
|
}
|
|
|
|
string Poke(string addr, string val, bool strict, bool cumulative)
|
|
{
|
|
return PreAccess(cumulative) ~
|
|
If!(strict)(
|
|
Attr("memory") ~ ".write(" ~ addr ~ ", " ~ val ~ ");\n");
|
|
}
|
|
|
|
string Write(string addr, string val, bool cumulative)
|
|
{
|
|
return PreAccess(cumulative) ~
|
|
Attr("memory") ~ ".write(" ~ addr ~ ", " ~ val ~ ");\n";
|
|
}
|
|
|
|
string IncPC()
|
|
{
|
|
return "++" ~ Attr("PC") ~ ";\n";
|
|
}
|
|
|
|
|
|
string IncSP()
|
|
{
|
|
return "++" ~ Attr("S") ~ ";\n";
|
|
}
|
|
|
|
string DecSP()
|
|
{
|
|
return "--" ~ Attr("S") ~ ";\n";
|
|
}
|
|
|
|
string PullStatus(bool s, bool c)
|
|
{
|
|
return Peek("0x0100 + " ~ Attr("S"), s, c) ~
|
|
IncSP() ~
|
|
PreAccess(c) ~
|
|
Attr("statusFromByte") ~ "(" ~
|
|
ReadRaw("0x0100 + " ~ Attr("S")) ~ ");\n";
|
|
}
|
|
|
|
string PullInto(string var, bool s, bool c)
|
|
{
|
|
return Peek("0x0100 + " ~ Attr("S"), s, c) ~
|
|
IncSP() ~
|
|
ReadInto(var, "0x0100 + " ~ Attr("S"), c);
|
|
}
|
|
|
|
string Push(string val, bool s, bool c)
|
|
{
|
|
return Write("0x0100 + " ~ Attr("S"), val, c) ~
|
|
DecSP();
|
|
}
|
|
|
|
string PushPC(bool s, bool c)
|
|
{
|
|
return Push(HiByte(Attr("PC")), s, c) ~
|
|
Push(LoByte(Attr("PC")), s, c);
|
|
}
|
|
|
|
|
|
string PullPC(bool s, bool c)
|
|
{
|
|
string PC = Attr("PC");
|
|
|
|
return PullInto(PC, s, c) ~
|
|
PreAccess(c) ~
|
|
IncSP() ~
|
|
PC ~ " |= (" ~ ReadRaw("0x0100 + " ~ Attr("S")) ~ " << 8);\n";
|
|
}
|
|
|
|
string SetFlag(string flag)
|
|
{
|
|
return Attr(flag) ~ " = true;\n";
|
|
}
|
|
|
|
string ClearFlag(string flag)
|
|
{
|
|
return Attr(flag) ~ " = false;\n";
|
|
}
|
|
|
|
string UpdateFlag(string flag, string val)
|
|
{
|
|
return Attr(flag) ~ " = (" ~ val ~ ");\n";
|
|
}
|
|
|
|
string SetNZ(string var)
|
|
{
|
|
return Attr("N") ~ " = " ~ Attr("Z") ~ " = (" ~ var ~ ");\n";
|
|
}
|
|
|
|
string Done(bool cumulative)
|
|
{
|
|
return If!(cumulative)(Attr("clock") ~ ".tick(cycles);\n");
|
|
}
|
|
|
|
|
|
string Attr(string var)
|
|
{
|
|
version(OpFunctions)
|
|
return "cpu." ~ var;
|
|
else
|
|
return var;
|
|
}
|
|
|
|
|
|
string HiByte(string var)
|
|
{
|
|
return var ~ " >> 8";
|
|
}
|
|
|
|
string LoByte(string var)
|
|
{
|
|
return var ~ " & 0xff";
|
|
}
|
|
|
|
|
|
string If(alias cond)(string yes, string no = "")
|
|
{
|
|
if (cond)
|
|
return yes;
|
|
else
|
|
return no;
|
|
}
|
|
|
|
|
|
string opName(int op, string chip)
|
|
{
|
|
if (chip == "6502")
|
|
return OP_NAMES_6502[op];
|
|
else
|
|
return OP_NAMES_65C02[op];
|
|
}
|
|
|
|
int opMode(int op, string chip)
|
|
{
|
|
if (chip == "6502")
|
|
return ADDR_MODES_6502[op];
|
|
else
|
|
return ADDR_MODES_65C02[op];
|
|
}
|
|
|
|
int opExCyc(int op, string chip)
|
|
{
|
|
if (chip == "6502")
|
|
return EXTRA_CYCLES_6502[op];
|
|
else
|
|
return EXTRA_CYCLES_65C02[op];
|
|
}
|
|
|
|
|
|
// Custom string formatting.
|
|
|
|
enum HEX_DIGITS = "0123456789abcdef";
|
|
|
|
string Hex1(int dec)
|
|
{
|
|
return HEX_DIGITS[dec..dec+1];
|
|
}
|
|
|
|
string Hex2(int dec)
|
|
{
|
|
int highNybble = (dec & 0xF0) >> 4;
|
|
int lowNybble = dec & 0x0F;
|
|
|
|
return HEX_DIGITS[highNybble..highNybble+1] ~
|
|
HEX_DIGITS[lowNybble..lowNybble+1];
|
|
}
|
|
|
|
string Fmt(string f, string[] p ...)
|
|
{
|
|
if (!p.length) return "ERROR";
|
|
string ret;
|
|
size_t last;
|
|
size_t other;
|
|
for (size_t i = 0; i < f.length; i++)
|
|
{
|
|
if (f[i] == '#')
|
|
{
|
|
if (other == p.length) return "ERROR";
|
|
ret ~= f[last..i] ~ p[other++];
|
|
last = i + 1;
|
|
}
|
|
}
|
|
return ret ~ f[last..$];
|
|
}
|