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https://github.com/byteworksinc/ORCA-C.git
synced 2024-06-15 23:29:44 +00:00
Implement 64-bit division and remainder, signed and unsigned.
These operations rely on new library routines in ORCALib (~CDIV8 and ~UDIV8).
This commit is contained in:
parent
08cf7a0181
commit
05868667b2
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@ -275,12 +275,16 @@
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{ pc_udi - unsigned integer divide }
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{ pc_udi - unsigned integer divide }
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{ pc_dvl - long integer divide }
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{ pc_dvl - long integer divide }
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{ pc_udl - unsigned long divide }
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{ pc_udl - unsigned long divide }
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{ pc_dvq - long long integer divide }
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{ pc_udq - unsigned long long divide }
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{ pc_dvr - real divide }
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{ pc_dvr - real divide }
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{ }
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{ }
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{ Gen0(pc_dvi) cgByte,cgWord }
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{ Gen0(pc_dvi) cgByte,cgWord }
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{ Gen0(pc_udi) cgUByte,cgUWord }
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{ Gen0(pc_udi) cgUByte,cgUWord }
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{ Gen0(pc_dvl) cgLong }
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{ Gen0(pc_dvl) cgLong }
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{ Gen0(pc_udl) cgULong }
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{ Gen0(pc_udl) cgULong }
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{ Gen0(pc_dvq) cgQuad }
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{ Gen0(pc_udq) cgUQuad }
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{ Gen0(pc_dvr) cgReal,cgDouble,cgComp,cgExtended }
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{ Gen0(pc_dvr) cgReal,cgDouble,cgComp,cgExtended }
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{ }
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{ }
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{ The two values on the top of the evaluation stack are }
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{ The two values on the top of the evaluation stack are }
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@ -464,11 +468,15 @@
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{ pc_uim - unsigned integer modulus/remainder }
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{ pc_uim - unsigned integer modulus/remainder }
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{ pc_mdl - long remainder }
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{ pc_mdl - long remainder }
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{ pc_ulm - unsigned long modulus/remainder }
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{ pc_ulm - unsigned long modulus/remainder }
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{ pc_mdq - long long remainder }
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{ pc_uqm - unsigned long long modulus/remainder }
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{ }
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{ }
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{ Gen0(pc_mod) cgByte,cgWord }
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{ Gen0(pc_mod) cgByte,cgWord }
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{ Gen0(pc_uim) cgUByte,cgUWord }
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{ Gen0(pc_uim) cgUByte,cgUWord }
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{ Gen0(pc_mdl) cgLong }
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{ Gen0(pc_mdl) cgLong }
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{ Gen0(pc_ulm) cgULong }
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{ Gen0(pc_ulm) cgULong }
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{ Gen0(pc_mdq) cgQuad }
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{ Gen0(pc_uqm) cgUQuad }
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{ }
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{ }
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{ The two values on the top of the evaluation stack are }
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{ The two values on the top of the evaluation stack are }
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{ removed and the remainder after division is calculated. }
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{ removed and the remainder after division is calculated. }
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@ -123,6 +123,10 @@ opt[pc_bnq] := 'bnq';
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opt[pc_ngq] := 'ngq';
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opt[pc_ngq] := 'ngq';
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opt[pc_mpq] := 'mpq';
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opt[pc_mpq] := 'mpq';
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opt[pc_umq] := 'umq';
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opt[pc_umq] := 'umq';
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opt[pc_dvq] := 'dvq';
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opt[pc_udq] := 'udq';
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opt[pc_mdq] := 'mdq';
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opt[pc_uqm] := 'uqm';
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end; {InitWriteCode}
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end; {InitWriteCode}
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3
CGI.pas
3
CGI.pas
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@ -229,7 +229,8 @@ type
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dc_sym,pc_lnd,pc_lor,pc_vsr,pc_uml,pc_udl,pc_ulm,pc_pop,pc_gil,
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dc_sym,pc_lnd,pc_lor,pc_vsr,pc_uml,pc_udl,pc_ulm,pc_pop,pc_gil,
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pc_gli,pc_gdl,pc_gld,pc_cpi,pc_tri,pc_lbu,pc_lbf,pc_sbf,pc_cbf,dc_cns,
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pc_gli,pc_gdl,pc_gld,pc_cpi,pc_tri,pc_lbu,pc_lbf,pc_sbf,pc_cbf,dc_cns,
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dc_prm,pc_nat,pc_bno,pc_nop,pc_psh,pc_ili,pc_iil,pc_ild,pc_idl,
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dc_prm,pc_nat,pc_bno,pc_nop,pc_psh,pc_ili,pc_iil,pc_ild,pc_idl,
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pc_bqr,pc_bqx,pc_baq,pc_bnq,pc_ngq,pc_adq,pc_sbq,pc_mpq,pc_umq);
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pc_bqr,pc_bqx,pc_baq,pc_bnq,pc_ngq,pc_adq,pc_sbq,pc_mpq,pc_umq,pc_dvq,
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pc_udq,pc_mdq,pc_uqm);
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{intermediate code}
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{intermediate code}
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{-----------------}
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{-----------------}
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7
DAG.pas
7
DAG.pas
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@ -2267,7 +2267,8 @@ case op^.opcode of
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pc_udl, pc_ulm, pc_uml, pc_vsr:
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pc_udl, pc_ulm, pc_uml, pc_vsr:
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TypeOf := cgULong;
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TypeOf := cgULong;
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pc_bnq, pc_ngq, pc_bqr, pc_bqx, pc_baq, pc_adq, pc_sbq, pc_mpq, pc_umq:
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pc_bnq, pc_ngq, pc_bqr, pc_bqx, pc_baq, pc_adq, pc_sbq, pc_mpq,
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pc_umq, pc_dvq, pc_udq, pc_mdq, pc_uqm:
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TypeOf := cgQuad;
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TypeOf := cgQuad;
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pc_ngr, pc_adr, pc_dvr, pc_mpr, pc_sbr:
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pc_ngr, pc_adr, pc_dvr, pc_mpr, pc_sbr:
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@ -4064,7 +4065,7 @@ var
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pc_ngl,pc_ngr,pc_not,pc_pop,pc_sbi,pc_sbl,pc_sbr,
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pc_ngl,pc_ngr,pc_not,pc_pop,pc_sbi,pc_sbl,pc_sbr,
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pc_shl,pc_sll,pc_shr,pc_usr,pc_slr,pc_vsr,pc_tri,
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pc_shl,pc_sll,pc_shr,pc_usr,pc_slr,pc_vsr,pc_tri,
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pc_bqr,pc_bqx,pc_baq,pc_bnq,pc_ngq,pc_adq,pc_sbq,
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pc_bqr,pc_bqx,pc_baq,pc_bnq,pc_ngq,pc_adq,pc_sbq,
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pc_mpq,pc_umq]
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pc_mpq,pc_umq,pc_dvq,pc_udq,pc_mdq,pc_uqm]
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then begin
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then begin
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op^.parents := icount;
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op^.parents := icount;
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icount := icount+1;
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icount := icount+1;
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@ -4945,7 +4946,7 @@ case code^.opcode of
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pc_ulm, pc_mpi, pc_umi, pc_mpl, pc_uml, pc_mpr, pc_psh, pc_sbi,
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pc_ulm, pc_mpi, pc_umi, pc_mpl, pc_uml, pc_mpr, pc_psh, pc_sbi,
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pc_sbl, pc_sbr, pc_shl, pc_sll, pc_shr, pc_usr, pc_slr, pc_vsr,
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pc_sbl, pc_sbr, pc_shl, pc_sll, pc_shr, pc_usr, pc_slr, pc_vsr,
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pc_tri, pc_sbf, pc_sto, pc_cui, pc_bqr, pc_bqx, pc_baq, pc_adq,
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pc_tri, pc_sbf, pc_sto, pc_cui, pc_bqr, pc_bqx, pc_baq, pc_adq,
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pc_sbq, pc_mpq, pc_umq:
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pc_sbq, pc_mpq, pc_umq, pc_dvq, pc_udq, pc_mdq, pc_uqm:
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begin
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begin
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code^.right := Pop;
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code^.right := Pop;
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code^.left := Pop;
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code^.left := Pop;
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@ -3160,6 +3160,10 @@ case tree^.token.kind of
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Gen0(pc_dvl)
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Gen0(pc_dvl)
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else if et = cgULong then
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else if et = cgULong then
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Gen0(pc_udl)
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Gen0(pc_udl)
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else if et = cgQuad then
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Gen0(pc_dvq)
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else if et = cgUQuad then
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Gen0(pc_udq)
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else if et = cgExtended then
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else if et = cgExtended then
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Gen0(pc_dvr)
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Gen0(pc_dvr)
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else
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else
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@ -3174,6 +3178,10 @@ case tree^.token.kind of
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Gen0(pc_mdl)
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Gen0(pc_mdl)
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else if et = cgULong then
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else if et = cgULong then
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Gen0(pc_ulm)
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Gen0(pc_ulm)
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else if et = cgQuad then
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Gen0(pc_mdq)
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else if et = cgUQuad then
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Gen0(pc_uqm)
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else
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else
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Error(66);
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Error(66);
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@ -3586,6 +3594,10 @@ case tree^.token.kind of
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Gen0(pc_dvl);
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Gen0(pc_dvl);
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cgULong:
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cgULong:
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Gen0(pc_udl);
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Gen0(pc_udl);
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cgQuad:
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Gen0(pc_dvq);
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cgUQuad:
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Gen0(pc_udq);
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cgExtended:
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cgExtended:
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Gen0(pc_dvr);
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Gen0(pc_dvr);
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otherwise:
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otherwise:
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@ -3610,6 +3622,10 @@ case tree^.token.kind of
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Gen0(pc_mdl);
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Gen0(pc_mdl);
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cgULong:
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cgULong:
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Gen0(pc_ulm);
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Gen0(pc_ulm);
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cgQuad:
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Gen0(pc_mdq);
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cgUQuad:
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Gen0(pc_uqm);
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otherwise:
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otherwise:
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error(66);
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error(66);
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end; {case}
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end; {case}
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46
Gen.pas
46
Gen.pas
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@ -4493,7 +4493,8 @@ procedure GenTree {op: icptr};
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procedure GenBinQuad (op: icptr);
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procedure GenBinQuad (op: icptr);
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{ generate one of: pc_bqr, pc_bqx, pc_baq }
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{ generate one of: pc_bqr, pc_bqx, pc_baq, pc_mpq, pc_umq, }
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{ pc_dvq, pc_udq, pc_mdq, pc_uqm }
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procedure GenOp (ops: integer);
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procedure GenOp (ops: integer);
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@ -4529,6 +4530,46 @@ procedure GenTree {op: icptr};
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pc_umq: GenCall(80);
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pc_umq: GenCall(80);
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pc_dvq: begin
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GenCall(81); {do division}
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GenImplied(m_pla); {get quotient, discarding remainder}
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GenNative(m_sta_s, direct, 7, nil, 0);
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GenImplied(m_pla);
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GenNative(m_sta_s, direct, 7, nil, 0);
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GenImplied(m_pla);
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GenNative(m_sta_s, direct, 7, nil, 0);
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GenImplied(m_pla);
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GenNative(m_sta_s, direct, 7, nil, 0);
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end;
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pc_udq: begin
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GenCall(82); {do division}
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GenImplied(m_pla); {get quotient, discarding remainder}
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GenNative(m_sta_s, direct, 7, nil, 0);
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GenImplied(m_pla);
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GenNative(m_sta_s, direct, 7, nil, 0);
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GenImplied(m_pla);
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GenNative(m_sta_s, direct, 7, nil, 0);
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GenImplied(m_pla);
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GenNative(m_sta_s, direct, 7, nil, 0);
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end;
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pc_mdq: begin
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GenCall(81); {do division}
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GenImplied(m_tsc); {discard quotient, leaving remainder}
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GenImplied(m_clc);
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GenNative(m_adc_imm, immediate, 8, nil, 0);
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GenImplied(m_tcs);
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end;
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pc_uqm: begin
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GenCall(82); {do division}
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GenImplied(m_tsc); {discard quotient, leaving remainder}
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GenImplied(m_clc);
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GenNative(m_adc_imm, immediate, 8, nil, 0);
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GenImplied(m_tcs);
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end;
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otherwise: Error(cge1);
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otherwise: Error(cge1);
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end; {case}
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end; {case}
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end; {GenBinQuad}
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end; {GenBinQuad}
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@ -6133,7 +6174,8 @@ case op^.opcode of
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pc_and,pc_bnd,pc_bor,pc_bxr,pc_ior: GenLogic(op);
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pc_and,pc_bnd,pc_bor,pc_bxr,pc_ior: GenLogic(op);
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pc_blr,pc_blx,pc_bal,pc_dvl,pc_mdl,pc_mpl,pc_sll,pc_slr,pc_udl,pc_ulm,
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pc_blr,pc_blx,pc_bal,pc_dvl,pc_mdl,pc_mpl,pc_sll,pc_slr,pc_udl,pc_ulm,
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pc_uml,pc_vsr: GenBinLong(op);
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pc_uml,pc_vsr: GenBinLong(op);
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pc_bqr,pc_bqx,pc_baq,pc_mpq,pc_umq: GenBinQuad(op);
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pc_bqr,pc_bqx,pc_baq,pc_mpq,pc_umq,pc_dvq,pc_udq,pc_mdq,pc_uqm:
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GenBinQuad(op);
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pc_bnl,pc_ngl: GenUnaryLong(op);
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pc_bnl,pc_ngl: GenUnaryLong(op);
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pc_bnq,pc_ngq: GenUnaryQuad(op);
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pc_bnq,pc_ngq: GenUnaryQuad(op);
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pc_bno: GenBno(op);
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pc_bno: GenBno(op);
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@ -2035,6 +2035,8 @@ case callNum of
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78: sp := @'~DIV4'; {CC}
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78: sp := @'~DIV4'; {CC}
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79: sp := @'~MUL8';
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79: sp := @'~MUL8';
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80: sp := @'~UMUL8';
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80: sp := @'~UMUL8';
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81: sp := @'~CDIV8';
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82: sp := @'~UDIV8';
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otherwise:
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otherwise:
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Error(cge1);
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Error(cge1);
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end; {case}
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end; {case}
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