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Recognize more indirect long instructions in the native code optimizer.
These instructions can be generated for indirect accesses to quad values, and the optimization can sometimes make those code sequences more efficient (e.g. avoiding unnecessary reloads of Y).
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parent
dcbeb3bc61
commit
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6
CGI.pas
6
CGI.pas
@ -50,11 +50,13 @@ const
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m_adc_imm = $69;
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m_adc_imm = $69;
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m_adc_s = $63;
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m_adc_s = $63;
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m_adc_indl = $67;
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m_adc_indl = $67;
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m_adc_indly = $77;
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m_and_abs = $2D;
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m_and_abs = $2D;
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m_and_dir = $25;
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m_and_dir = $25;
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m_and_imm = $29;
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m_and_imm = $29;
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m_and_s = $23;
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m_and_s = $23;
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m_and_indl = $27;
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m_and_indl = $27;
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m_and_indly = $37;
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m_asl_a = $0A;
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m_asl_a = $0A;
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m_bcc = $90;
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m_bcc = $90;
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m_bcs = $B0;
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m_bcs = $B0;
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@ -74,6 +76,7 @@ const
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m_cmp_long = $CF;
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m_cmp_long = $CF;
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m_cmp_s = $C3;
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m_cmp_s = $C3;
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m_cmp_indl = $C7;
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m_cmp_indl = $C7;
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m_cmp_indly = $D7;
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m_cop = $02;
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m_cop = $02;
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m_cpx_abs = 236;
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m_cpx_abs = 236;
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m_cpx_dir = 228;
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m_cpx_dir = 228;
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@ -90,6 +93,7 @@ const
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m_eor_imm = 73;
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m_eor_imm = 73;
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m_eor_s = 67;
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m_eor_s = 67;
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m_eor_indl = $47;
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m_eor_indl = $47;
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m_eor_indly = $57;
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m_ina = 26;
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m_ina = 26;
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m_inc_abs = 238;
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m_inc_abs = 238;
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m_inc_absX = $FE;
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m_inc_absX = $FE;
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@ -127,6 +131,7 @@ const
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m_ora_longX = 31;
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m_ora_longX = 31;
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m_ora_s = 3;
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m_ora_s = 3;
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m_ora_indl = $07;
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m_ora_indl = $07;
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m_ora_indly = $17;
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m_pea = 244;
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m_pea = 244;
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m_pei_dir = 212;
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m_pei_dir = 212;
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m_pha = 72;
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m_pha = 72;
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@ -149,6 +154,7 @@ const
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m_sbc_imm = 233;
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m_sbc_imm = 233;
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m_sbc_s = 227;
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m_sbc_s = 227;
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m_sbc_indl = $E7;
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m_sbc_indl = $E7;
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m_sbc_indly = $F7;
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m_sec = 56;
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m_sec = 56;
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m_sep = 226;
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m_sep = 226;
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m_sta_abs = 141;
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m_sta_abs = 141;
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@ -774,7 +774,9 @@ case p_opcode of
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m_and_s,m_asl_a,m_dea,m_eor_abs,m_eor_dir,m_eor_imm,m_eor_s,m_lda_absx,
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m_and_s,m_asl_a,m_dea,m_eor_abs,m_eor_dir,m_eor_imm,m_eor_s,m_lda_absx,
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m_lda_dirx,m_lda_indl,m_lda_indly,m_lda_longx,m_lda_s,m_lsr_a,m_ora_abs,
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m_lda_dirx,m_lda_indl,m_lda_indly,m_lda_longx,m_lda_s,m_lsr_a,m_ora_abs,
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m_ora_dir,m_ora_dirX,m_ora_imm,m_ora_long,m_ora_longX,m_ora_s,m_pla,
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m_ora_dir,m_ora_dirX,m_ora_imm,m_ora_long,m_ora_longX,m_ora_s,m_pla,
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m_sbc_abs,m_sbc_dir,m_sbc_imm,m_sbc_s,m_tdc,m_tsc:
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m_sbc_abs,m_sbc_dir,m_sbc_imm,m_sbc_s,m_tdc,m_tsc,m_adc_indl,m_adc_indly,
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m_and_indl,m_and_indly,m_ora_indl,m_ora_indly,m_sbc_indl,m_sbc_indly,
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m_eor_indl,m_eor_indly:
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aRegister.condition := regUnknown;
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aRegister.condition := regUnknown;
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m_ldy_absX,m_ldy_dirX,m_ply:
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m_ldy_absX,m_ldy_dirX,m_ply:
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@ -784,8 +786,8 @@ case p_opcode of
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xRegister.condition := regUnknown;
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xRegister.condition := regUnknown;
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m_bcc,m_bcs,m_beq,m_bmi,m_bne,m_bpl,m_bra,m_brl,m_bvs,m_clc,m_cmp_abs,
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m_bcc,m_bcs,m_beq,m_bmi,m_bne,m_bpl,m_bra,m_brl,m_bvs,m_clc,m_cmp_abs,
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m_cmp_dir,m_cmp_imm,m_cmp_s,m_cpx_imm,m_jml,m_pha,m_phb,m_phd,
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m_cmp_dir,m_cmp_imm,m_cmp_s,m_cmp_indl,m_cmp_indly,m_cpx_imm,m_jml,
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m_phx,m_phy,m_plb,m_rtl,m_rts,m_sec,m_tcs,d_add,d_pin,
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m_pha,m_phb,m_phd,m_phx,m_phy,m_plb,m_rtl,m_rts,m_sec,m_tcs,d_add,d_pin,
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m_pei_dir,m_cpx_abs,m_cpx_dir,m_cmp_dirx,m_php,m_plp,m_cop,d_wrd: ;
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m_pei_dir,m_cpx_abs,m_cpx_dir,m_cmp_dirx,m_php,m_plp,m_cop,d_wrd: ;
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m_pea: begin
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m_pea: begin
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