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Fix register assignments for dynamic tile renderer
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@ -2,14 +2,16 @@
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;
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; These tile renderes are for "normal" tiles that also apply their mask data. If the case of the second
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; background being disabled, the optimized variants are the same as Tile00000
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_TBMaskedTile dw _TBMaskedTile_00,_TBMaskedTile_0H,_TBMaskedTile_V0,_TBMaskedTile_VH
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dw _TBCopyData,_TBCopyDataH,_TBCopyDataV,_TBCopyDataVH
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;
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; Y register = address of code field tile
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; X register = tile address
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; Accumulator = logical word offset of the tile (0, 2, 4, ..., 82)
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;
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; Need to slightly remap these register inputs to save into the direct page cached values
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_TBMaskedTile_00
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stx _X_REG ; Save these values as we will need to reload them
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sta _X_REG ; Save these values as we will need to reload them
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sty _Y_REG ; at certain points
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sta _T_PTR
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tax
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stx _T_PTR
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; Do the left column first
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@ -43,10 +45,9 @@ _TBMaskedTile_00
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rts
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_TBMaskedTile_0H
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stx _X_REG ; Save these values as we will need to reload them
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sty _Y_REG ; at certain points
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sta _T_PTR
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tax
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sta _X_REG
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sty _Y_REG
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stx _T_PTR
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CopyMaskedWord tiledata+64+0;tiledata+64+32+0;$0003
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CopyMaskedWord tiledata+64+4;tiledata+64+32+4;$1003
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@ -72,10 +73,9 @@ _TBMaskedTile_0H
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rts
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_TBMaskedTile_V0
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stx _X_REG ; Save these values as we will need to reload them
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sty _Y_REG ; at certain points
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sta _T_PTR
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tax
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sta _X_REG
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sty _Y_REG
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stx _T_PTR
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CopyMaskedWord tiledata+0;tiledata+32+0;$7003
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CopyMaskedWord tiledata+4;tiledata+32+4;$6003
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@ -101,10 +101,9 @@ _TBMaskedTile_V0
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rts
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_TBMaskedTile_VH
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stx _X_REG ; Save these values as we will need to reload them
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sty _Y_REG ; at certain points
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sta _T_PTR
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tax
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sta _X_REG
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sty _Y_REG
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stx _T_PTR
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CopyMaskedWord tiledata+64+0;tiledata+64+32+0;$7003
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CopyMaskedWord tiledata+64+4;tiledata+64+32+4;$6003
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