Macintosh-HW/68030tk
1
0
Fork 0
mirror of https://github.com/kr239/68030tk.git synced 2024-06-11 08:29:32 +00:00
Code Issues Projects Releases Wiki Activity
2587047f0d
68030tk/Logic/BUS68030.bl0
MHeinrichs 2587047f0d Some Changes regarding CIIN and Timing
2014-06-15 16:53:31 +02:00

1480 lines
66 KiB
Plaintext
Raw Blame History

#$ DATE Sun Jun 15 16:36:43 2014
#$ TOOL EDIF2BLIF version IspLever 1.0
#$ MODULE bus68030
#$ PINS 59 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ RW_000 IPL_030_1_ DS_030 IPL_030_0_ UDS_000 IPL_1_ LDS_000 IPL_0_ A0 FC_0_ nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_
#$ NODES 473 sm_amiga_ns_0_2_0__n CLK_OSZI_i sm_amiga_ns_0_3_0__n uds_000_int_0_un3_n uds_000_int_0_un1_n un16_ciin_i uds_000_int_0_un0_n CLK_OUT_PRE_50_D_i ipl_030_0_0__un3_n inst_BGACK_030_INTreg \
# AS_030_c ipl_030_0_0__un1_n vcc_n_n ipl_030_0_0__un0_n inst_avec_expreg AS_000_c ipl_030_0_1__un3_n inst_VMA_INTreg ipl_030_0_1__un1_n inst_AMIGA_BUS_ENABLE_INTreg \
# RW_000_c ipl_030_0_1__un0_n inst_CLK_OUT_PRE_33reg ipl_030_0_2__un3_n inst_AS_030_000_SYNC DS_030_c ipl_030_0_2__un1_n inst_BGACK_030_INT_D ipl_030_0_2__un0_n inst_AS_000_DMA \
# UDS_000_c cpu_estse_0_un3_n inst_VPA_D cpu_estse_0_un1_n inst_CLK_OUT_PRE_50_D LDS_000_c cpu_estse_0_un0_n inst_CLK_000_D0 cpu_estse_1_un3_n inst_CLK_000_D1 \
# size_c_0__n cpu_estse_1_un1_n inst_CLK_000_D4 cpu_estse_1_un0_n CLK_CNT_N_0_ size_c_1__n cpu_estse_2_un3_n inst_CLK_OUT_PRE_50 cpu_estse_2_un1_n inst_CLK_OUT_PRE_25 \
# a_c_16__n cpu_estse_2_un0_n inst_CLK_000_D2 as_030_000_sync_0_un3_n inst_CLK_000_D3 a_c_17__n as_030_000_sync_0_un1_n inst_CLK_OUT_PRE_D as_030_000_sync_0_un0_n inst_CLK_OUT_PRE \
# a_c_18__n ds_000_enable_0_un3_n CLK_000_P_SYNC_9_ ds_000_enable_0_un1_n inst_AS_000_INT a_c_19__n ds_000_enable_0_un0_n SM_AMIGA_7_ lds_000_int_0_un3_n SM_AMIGA_6_ \
# a_c_20__n lds_000_int_0_un1_n SM_AMIGA_1_ lds_000_int_0_un0_n SM_AMIGA_0_ a_c_21__n bgack_030_int_0_un3_n SM_AMIGA_4_ bgack_030_int_0_un1_n inst_CLK_030_H \
# a_c_22__n bgack_030_int_0_un0_n CLK_CNT_P_1_ amiga_bus_enable_int_0_un3_n CLK_CNT_N_1_ a_c_23__n amiga_bus_enable_int_0_un1_n inst_RW_000_INT amiga_bus_enable_int_0_un0_n inst_DSACK1_INT \
# a_c_24__n ds_000_dma_0_un3_n state_machine_un3_clk_out_pre_50_n ds_000_dma_0_un1_n CLK_CNT_P_0_ a_c_25__n ds_000_dma_0_un0_n inst_RW_000_DMA as_000_dma_0_un3_n un1_LDS_000_INT \
# a_c_26__n as_000_dma_0_un1_n inst_LDS_000_INT as_000_dma_0_un0_n inst_DS_000_ENABLE a_c_27__n clk_030_h_0_un3_n un1_UDS_000_INT clk_030_h_0_un1_n inst_UDS_000_INT \
# a_c_28__n clk_030_h_0_un0_n rw_000_dma_0_un3_n a_c_29__n rw_000_dma_0_un1_n inst_DS_000_DMA rw_000_dma_0_un0_n SIZE_DMA_0_ a_c_30__n vma_int_0_un3_n \
# SIZE_DMA_1_ vma_int_0_un1_n inst_A0_DMA a_c_31__n vma_int_0_un0_n G_108 as_000_int_0_un3_n G_114 A0_c as_000_int_0_un1_n \
# CLK_000_P_SYNC_0_ as_000_int_0_un0_n CLK_000_P_SYNC_1_ nEXP_SPACE_c dsack1_int_0_un3_n CLK_000_P_SYNC_2_ dsack1_int_0_un1_n CLK_000_P_SYNC_3_ BERR_c dsack1_int_0_un0_n \
# CLK_000_P_SYNC_4_ rw_000_int_0_un3_n CLK_000_P_SYNC_5_ BG_030_c rw_000_int_0_un1_n CLK_000_P_SYNC_6_ rw_000_int_0_un0_n CLK_000_P_SYNC_7_ BG_000DFFSHreg bg_000_0_un3_n \
# CLK_000_P_SYNC_8_ bg_000_0_un1_n un19_fpu_cs bg_000_0_un0_n un5_ciin BGACK_000_c CLK_030_c un16_ciin SM_AMIGA_5_ SM_AMIGA_3_ \
# CLK_OSZI_c SM_AMIGA_2_ CLK_OUT_INTreg IPL_030DFFSH_0_reg IPL_030DFFSH_1_reg IPL_030DFFSH_2_reg ipl_c_0__n ipl_c_1__n ipl_c_2__n CLK_OUT_PRE_25_0 \
# DSACK1_c DTACK_c VPA_c cpu_est_0_ cpu_est_1_ RST_c cpu_est_2_ cpu_est_3_reg RESETDFFRHreg cpu_estse \
# RW_c fc_c_0__n un6_clk_pre_66 un2_clk_pre_66 fc_c_1__n N_96 state_machine_un34_clk_000_d0_n state_machine_un16_clk_000_d0_n AMIGA_BUS_DATA_DIR_c N_88 \
# N_111 state_machine_un8_bgack_030_int_n N_175_1 UDS_000_INT_i state_machine_un10_clk_000_d0_2_n un1_UDS_000_INT_0 state_machine_un38_clk_000_d0_1_n SM_AMIGA_0_sqmuxa_i N_171 DS_000_ENABLE_0_sqmuxa_i \
# cpu_est_ns_1__n un1_SM_AMIGA_0_sqmuxa_2_i DSACK1_INT_0_sqmuxa N_100_i state_machine_un1_as_030_n sm_amiga_ns_0_0__n AS_030_000_SYNC_0_sqmuxa N_102_i state_machine_un10_bg_030_n N_103_i \
# un8_ciin sm_amiga_ns_0_1__n un12_ciin N_106_i un14_ciin N_105_i state_machine_un8_bg_030_n sm_amiga_ns_0_3__n AS_000_INT_1_sqmuxa N_107_i \
# DSACK1_INT_1_sqmuxa sm_amiga_ns_0_4__n state_machine_rw_000_int_3_n N_108_i N_71 N_109_i state_machine_un12_clk_000_d0_n sm_amiga_ns_0_5__n state_machine_un10_clk_000_d0_n N_110_i \
# state_machine_un5_clk_000_d0_n N_163 N_88_i N_164 N_90_i N_165 N_93_0 state_machine_un38_clk_000_d0_n N_97_i state_machine_un31_bgack_030_int_n \
# N_98_i N_174 N_99_i N_175 N_101_i N_112 sm_amiga_i_4__n state_machine_un32_clk_000_d0_n N_91_i state_machine_clk_030_h_2_n \
# N_168_i DS_000_DMA_1_sqmuxa_1 cpu_est_ns_0_2__n AS_000_DMA_1_sqmuxa state_machine_un10_clk_000_d0_2_i_n CLK_030_H_1_sqmuxa_1 N_167_i DS_000_DMA_1_sqmuxa N_170_i state_machine_un24_bgack_030_int_n \
# N_169_i state_machine_un10_bgack_030_int_n N_160_i state_machine_clk_030_h_2_f1_n N_92_0 CLK_030_H_1_sqmuxa N_104_i un1_bgack_030_int_d un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un1_as_030_i_n \
# state_machine_un3_bgack_030_int_d_n state_machine_un6_clk_000_p_sync_i_n AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 state_machine_un6_bgack_000_0_n SM_AMIGA_0_sqmuxa_1 LDS_000_INT_i AMIGA_BUS_ENABLE_INT_3_sqmuxa un1_LDS_000_INT_0 AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un7_ds_030_i_n \
# AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 A0_c_i N_95 size_c_i_1__n un1_AS_030_000_SYNC_0_sqmuxa_1 state_machine_un5_bgack_030_int_d_i_n un1_SM_AMIGA_0_sqmuxa_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i un2_as_030 AMIGA_BUS_ENABLE_INT_2_sqmuxa_i \
# state_machine_un6_bgack_000_n un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 state_machine_un6_clk_000_p_sync_n state_machine_un3_bgack_030_int_d_i_n N_104 un1_bgack_030_int_d_0 N_92 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i cpu_est_ns_2__n AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i \
# N_167 un3_dtack_i N_168 CLK_030_H_i N_169 CLK_030_H_1_sqmuxa_i N_170 state_machine_clk_030_h_2_f1_0_n N_102 state_machine_un10_bgack_030_int_0_n \
# DS_000_ENABLE_0_sqmuxa state_machine_un38_clk_000_d0_i_n N_101 state_machine_un32_clk_000_d0_i_n N_90 state_machine_un34_clk_000_d0_0_n N_91 N_112_i N_100 sm_amiga_ns_0_7__n \
# state_machine_un30_clk_000_d0_n N_175_i N_98 N_174_i N_97 AMIGA_BUS_DATA_DIR_c_0 N_107 state_machine_size_dma_4_0_1__n N_99 state_machine_size_dma_4_0_0__n \
# N_93 N_171_i N_110 N_164_i N_108 N_163_i N_109 cpu_est_ns_0_1__n SM_AMIGA_0_sqmuxa state_machine_un10_clk_000_d0_i_n \
# N_105 state_machine_un5_clk_000_d0_i_n N_106 state_machine_un12_clk_000_d0_0_n N_103 N_71_0 un19_fpu_cs_i state_machine_rw_000_int_3_0_n CLK_000_D1_i BG_030_c_i \
# sm_amiga_i_1__n state_machine_un8_bg_030_i_n sm_amiga_i_0__n state_machine_un10_bg_030_0_n CLK_000_D0_i un8_ciin_i sm_amiga_i_2__n un14_ciin_0 BERR_i un2_clk_pre_66_i \
# state_machine_un30_clk_000_d0_i_n un6_clk_pre_66_i sm_amiga_i_3__n CLK_PRE_66_0 SM_AMIGA_0_sqmuxa_1_i cpu_est_ns_0_1_1__n CLK_000_D3_i cpu_est_ns_0_2_1__n CLK_000_D2_i N_91_i_1 \
# cpu_est_i_1__n un5_ciin_1 cpu_est_i_0__n un5_ciin_2 cpu_est_i_3__n un5_ciin_3 state_machine_un38_clk_000_d0_1_i_n un5_ciin_4 AS_030_000_SYNC_i un5_ciin_5 \
# CLK_000_D4_i un5_ciin_6 sm_amiga_i_5__n un5_ciin_7 sm_amiga_i_6__n un5_ciin_8 a_i_19__n un5_ciin_9 a_i_18__n un5_ciin_10 \
# AS_030_i un5_ciin_11 a_i_16__n state_machine_un8_bg_030_1_n AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n N_95_i un12_ciin_1 BGACK_030_INT_i un12_ciin_2 \
# BGACK_030_INT_D_i un12_ciin_3 AS_000_i un12_ciin_4 CLK_030_i un12_ciin_5 AS_000_DMA_i un12_ciin_6 state_machine_un24_bgack_030_int_i_n AS_030_000_SYNC_0_sqmuxa_1 \
# RW_000_i AS_030_000_SYNC_0_sqmuxa_2 UDS_000_i state_machine_un38_clk_000_d0_1_0_n LDS_000_i state_machine_un5_clk_000_d0_1_n state_machine_un8_bgack_030_int_i_n state_machine_un5_clk_000_d0_2_n CLK_030_H_1_sqmuxa_1_i state_machine_un10_clk_000_d0_1_n \
# DS_000_DMA_1_sqmuxa_1_i state_machine_un10_clk_000_d0_2_0_n DTACK_i state_machine_un10_clk_000_d0_3_n sm_amiga_i_7__n N_175_1_0 N_111_i un3_dtack_i_1 nEXP_SPACE_i un1_bgack_030_int_d_0_1 \
# RW_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 state_machine_un31_bgack_030_int_i_n AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 VPA_D_i state_machine_un7_ds_030_i_1_n VPA_i un19_fpu_cs_1 VMA_INT_i un19_fpu_cs_2 \
# cpu_est_i_2__n un19_fpu_cs_3 N_165_i_0 un19_fpu_cs_4 DSACK1_INT_0_sqmuxa_i un19_fpu_cs_5 N_96_i un19_fpu_cs_6 a_i_31__n DSACK1_INT_0_sqmuxa_1 \
# a_i_30__n SM_AMIGA_0_sqmuxa_1_1 a_i_29__n cpu_est_ns_0_1_2__n a_i_28__n state_machine_clk_000_p_sync_3_1_0__n a_i_27__n DS_000_ENABLE_0_sqmuxa_1 a_i_26__n N_101_1 \
# a_i_25__n N_101_2 a_i_24__n N_101_3 un5_ciin_i N_100_1 un12_ciin_i N_98_1 clk_cnt_n_i_0__n N_97_1 \
# N_107_1 RST_i sm_amiga_ns_0_1_0__n
.model bus68030
.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BERR.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \
CLK_OSZI.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF \
A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \
IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF sm_amiga_ns_0_2_0__n.BLIF CLK_OSZI_i.BLIF sm_amiga_ns_0_3_0__n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF un16_ciin_i.BLIF \
uds_000_int_0_un0_n.BLIF CLK_OUT_PRE_50_D_i.BLIF ipl_030_0_0__un3_n.BLIF inst_BGACK_030_INTreg.BLIF AS_030_c.BLIF ipl_030_0_0__un1_n.BLIF vcc_n_n.BLIF ipl_030_0_0__un0_n.BLIF inst_avec_expreg.BLIF \
AS_000_c.BLIF ipl_030_0_1__un3_n.BLIF inst_VMA_INTreg.BLIF ipl_030_0_1__un1_n.BLIF inst_AMIGA_BUS_ENABLE_INTreg.BLIF RW_000_c.BLIF ipl_030_0_1__un0_n.BLIF inst_CLK_OUT_PRE_33reg.BLIF ipl_030_0_2__un3_n.BLIF \
inst_AS_030_000_SYNC.BLIF DS_030_c.BLIF ipl_030_0_2__un1_n.BLIF inst_BGACK_030_INT_D.BLIF ipl_030_0_2__un0_n.BLIF inst_AS_000_DMA.BLIF UDS_000_c.BLIF cpu_estse_0_un3_n.BLIF inst_VPA_D.BLIF \
cpu_estse_0_un1_n.BLIF inst_CLK_OUT_PRE_50_D.BLIF LDS_000_c.BLIF cpu_estse_0_un0_n.BLIF inst_CLK_000_D0.BLIF cpu_estse_1_un3_n.BLIF inst_CLK_000_D1.BLIF size_c_0__n.BLIF cpu_estse_1_un1_n.BLIF \
inst_CLK_000_D4.BLIF cpu_estse_1_un0_n.BLIF CLK_CNT_N_0_.BLIF size_c_1__n.BLIF cpu_estse_2_un3_n.BLIF inst_CLK_OUT_PRE_50.BLIF cpu_estse_2_un1_n.BLIF inst_CLK_OUT_PRE_25.BLIF a_c_16__n.BLIF \
cpu_estse_2_un0_n.BLIF inst_CLK_000_D2.BLIF as_030_000_sync_0_un3_n.BLIF inst_CLK_000_D3.BLIF a_c_17__n.BLIF as_030_000_sync_0_un1_n.BLIF inst_CLK_OUT_PRE_D.BLIF as_030_000_sync_0_un0_n.BLIF inst_CLK_OUT_PRE.BLIF \
a_c_18__n.BLIF ds_000_enable_0_un3_n.BLIF CLK_000_P_SYNC_9_.BLIF ds_000_enable_0_un1_n.BLIF inst_AS_000_INT.BLIF a_c_19__n.BLIF ds_000_enable_0_un0_n.BLIF SM_AMIGA_7_.BLIF lds_000_int_0_un3_n.BLIF \
SM_AMIGA_6_.BLIF a_c_20__n.BLIF lds_000_int_0_un1_n.BLIF SM_AMIGA_1_.BLIF lds_000_int_0_un0_n.BLIF SM_AMIGA_0_.BLIF a_c_21__n.BLIF bgack_030_int_0_un3_n.BLIF SM_AMIGA_4_.BLIF \
bgack_030_int_0_un1_n.BLIF inst_CLK_030_H.BLIF a_c_22__n.BLIF bgack_030_int_0_un0_n.BLIF CLK_CNT_P_1_.BLIF amiga_bus_enable_int_0_un3_n.BLIF CLK_CNT_N_1_.BLIF a_c_23__n.BLIF amiga_bus_enable_int_0_un1_n.BLIF \
inst_RW_000_INT.BLIF amiga_bus_enable_int_0_un0_n.BLIF inst_DSACK1_INT.BLIF a_c_24__n.BLIF ds_000_dma_0_un3_n.BLIF state_machine_un3_clk_out_pre_50_n.BLIF ds_000_dma_0_un1_n.BLIF CLK_CNT_P_0_.BLIF a_c_25__n.BLIF \
ds_000_dma_0_un0_n.BLIF inst_RW_000_DMA.BLIF as_000_dma_0_un3_n.BLIF un1_LDS_000_INT.BLIF a_c_26__n.BLIF as_000_dma_0_un1_n.BLIF inst_LDS_000_INT.BLIF as_000_dma_0_un0_n.BLIF inst_DS_000_ENABLE.BLIF \
a_c_27__n.BLIF clk_030_h_0_un3_n.BLIF un1_UDS_000_INT.BLIF clk_030_h_0_un1_n.BLIF inst_UDS_000_INT.BLIF a_c_28__n.BLIF clk_030_h_0_un0_n.BLIF rw_000_dma_0_un3_n.BLIF a_c_29__n.BLIF \
rw_000_dma_0_un1_n.BLIF inst_DS_000_DMA.BLIF rw_000_dma_0_un0_n.BLIF SIZE_DMA_0_.BLIF a_c_30__n.BLIF vma_int_0_un3_n.BLIF SIZE_DMA_1_.BLIF vma_int_0_un1_n.BLIF inst_A0_DMA.BLIF \
a_c_31__n.BLIF vma_int_0_un0_n.BLIF G_108.BLIF as_000_int_0_un3_n.BLIF G_114.BLIF A0_c.BLIF as_000_int_0_un1_n.BLIF CLK_000_P_SYNC_0_.BLIF as_000_int_0_un0_n.BLIF \
CLK_000_P_SYNC_1_.BLIF nEXP_SPACE_c.BLIF dsack1_int_0_un3_n.BLIF CLK_000_P_SYNC_2_.BLIF dsack1_int_0_un1_n.BLIF CLK_000_P_SYNC_3_.BLIF BERR_c.BLIF dsack1_int_0_un0_n.BLIF CLK_000_P_SYNC_4_.BLIF \
rw_000_int_0_un3_n.BLIF CLK_000_P_SYNC_5_.BLIF BG_030_c.BLIF rw_000_int_0_un1_n.BLIF CLK_000_P_SYNC_6_.BLIF rw_000_int_0_un0_n.BLIF CLK_000_P_SYNC_7_.BLIF BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF \
CLK_000_P_SYNC_8_.BLIF bg_000_0_un1_n.BLIF un19_fpu_cs.BLIF bg_000_0_un0_n.BLIF un5_ciin.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF un16_ciin.BLIF SM_AMIGA_5_.BLIF \
SM_AMIGA_3_.BLIF CLK_OSZI_c.BLIF SM_AMIGA_2_.BLIF CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF IPL_030DFFSH_1_reg.BLIF IPL_030DFFSH_2_reg.BLIF ipl_c_0__n.BLIF ipl_c_1__n.BLIF \
ipl_c_2__n.BLIF CLK_OUT_PRE_25_0.BLIF DSACK1_c.BLIF DTACK_c.BLIF VPA_c.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF RST_c.BLIF cpu_est_2_.BLIF \
cpu_est_3_reg.BLIF RESETDFFRHreg.BLIF cpu_estse.BLIF RW_c.BLIF fc_c_0__n.BLIF un6_clk_pre_66.BLIF un2_clk_pre_66.BLIF fc_c_1__n.BLIF N_96.BLIF \
state_machine_un34_clk_000_d0_n.BLIF state_machine_un16_clk_000_d0_n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF N_88.BLIF N_111.BLIF state_machine_un8_bgack_030_int_n.BLIF N_175_1.BLIF UDS_000_INT_i.BLIF state_machine_un10_clk_000_d0_2_n.BLIF \
un1_UDS_000_INT_0.BLIF state_machine_un38_clk_000_d0_1_n.BLIF SM_AMIGA_0_sqmuxa_i.BLIF N_171.BLIF DS_000_ENABLE_0_sqmuxa_i.BLIF cpu_est_ns_1__n.BLIF un1_SM_AMIGA_0_sqmuxa_2_i.BLIF DSACK1_INT_0_sqmuxa.BLIF N_100_i.BLIF \
state_machine_un1_as_030_n.BLIF sm_amiga_ns_0_0__n.BLIF AS_030_000_SYNC_0_sqmuxa.BLIF N_102_i.BLIF state_machine_un10_bg_030_n.BLIF N_103_i.BLIF un8_ciin.BLIF sm_amiga_ns_0_1__n.BLIF un12_ciin.BLIF \
N_106_i.BLIF un14_ciin.BLIF N_105_i.BLIF state_machine_un8_bg_030_n.BLIF sm_amiga_ns_0_3__n.BLIF AS_000_INT_1_sqmuxa.BLIF N_107_i.BLIF DSACK1_INT_1_sqmuxa.BLIF sm_amiga_ns_0_4__n.BLIF \
state_machine_rw_000_int_3_n.BLIF N_108_i.BLIF N_71.BLIF N_109_i.BLIF state_machine_un12_clk_000_d0_n.BLIF sm_amiga_ns_0_5__n.BLIF state_machine_un10_clk_000_d0_n.BLIF N_110_i.BLIF state_machine_un5_clk_000_d0_n.BLIF \
N_163.BLIF N_88_i.BLIF N_164.BLIF N_90_i.BLIF N_165.BLIF N_93_0.BLIF state_machine_un38_clk_000_d0_n.BLIF N_97_i.BLIF state_machine_un31_bgack_030_int_n.BLIF \
N_98_i.BLIF N_174.BLIF N_99_i.BLIF N_175.BLIF N_101_i.BLIF N_112.BLIF sm_amiga_i_4__n.BLIF state_machine_un32_clk_000_d0_n.BLIF N_91_i.BLIF \
state_machine_clk_030_h_2_n.BLIF N_168_i.BLIF DS_000_DMA_1_sqmuxa_1.BLIF cpu_est_ns_0_2__n.BLIF AS_000_DMA_1_sqmuxa.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF CLK_030_H_1_sqmuxa_1.BLIF N_167_i.BLIF DS_000_DMA_1_sqmuxa.BLIF \
N_170_i.BLIF state_machine_un24_bgack_030_int_n.BLIF N_169_i.BLIF state_machine_un10_bgack_030_int_n.BLIF N_160_i.BLIF state_machine_clk_030_h_2_f1_n.BLIF N_92_0.BLIF CLK_030_H_1_sqmuxa.BLIF N_104_i.BLIF \
un1_bgack_030_int_d.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF state_machine_un1_as_030_i_n.BLIF state_machine_un3_bgack_030_int_d_n.BLIF state_machine_un6_clk_000_p_sync_i_n.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF state_machine_un6_bgack_000_0_n.BLIF SM_AMIGA_0_sqmuxa_1.BLIF LDS_000_INT_i.BLIF \
AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF un1_LDS_000_INT_0.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF state_machine_un7_ds_030_i_n.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF A0_c_i.BLIF N_95.BLIF size_c_i_1__n.BLIF un1_AS_030_000_SYNC_0_sqmuxa_1.BLIF \
state_machine_un5_bgack_030_int_d_i_n.BLIF un1_SM_AMIGA_0_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF un2_as_030.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF state_machine_un6_bgack_000_n.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF state_machine_un6_clk_000_p_sync_n.BLIF state_machine_un3_bgack_030_int_d_i_n.BLIF \
N_104.BLIF un1_bgack_030_int_d_0.BLIF N_92.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF cpu_est_ns_2__n.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF N_167.BLIF un3_dtack_i.BLIF N_168.BLIF \
CLK_030_H_i.BLIF N_169.BLIF CLK_030_H_1_sqmuxa_i.BLIF N_170.BLIF state_machine_clk_030_h_2_f1_0_n.BLIF N_102.BLIF state_machine_un10_bgack_030_int_0_n.BLIF DS_000_ENABLE_0_sqmuxa.BLIF state_machine_un38_clk_000_d0_i_n.BLIF \
N_101.BLIF state_machine_un32_clk_000_d0_i_n.BLIF N_90.BLIF state_machine_un34_clk_000_d0_0_n.BLIF N_91.BLIF N_112_i.BLIF N_100.BLIF sm_amiga_ns_0_7__n.BLIF state_machine_un30_clk_000_d0_n.BLIF \
N_175_i.BLIF N_98.BLIF N_174_i.BLIF N_97.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF N_107.BLIF state_machine_size_dma_4_0_1__n.BLIF N_99.BLIF state_machine_size_dma_4_0_0__n.BLIF \
N_93.BLIF N_171_i.BLIF N_110.BLIF N_164_i.BLIF N_108.BLIF N_163_i.BLIF N_109.BLIF cpu_est_ns_0_1__n.BLIF SM_AMIGA_0_sqmuxa.BLIF \
state_machine_un10_clk_000_d0_i_n.BLIF N_105.BLIF state_machine_un5_clk_000_d0_i_n.BLIF N_106.BLIF state_machine_un12_clk_000_d0_0_n.BLIF N_103.BLIF N_71_0.BLIF un19_fpu_cs_i.BLIF state_machine_rw_000_int_3_0_n.BLIF \
CLK_000_D1_i.BLIF BG_030_c_i.BLIF sm_amiga_i_1__n.BLIF state_machine_un8_bg_030_i_n.BLIF sm_amiga_i_0__n.BLIF state_machine_un10_bg_030_0_n.BLIF CLK_000_D0_i.BLIF un8_ciin_i.BLIF sm_amiga_i_2__n.BLIF \
un14_ciin_0.BLIF BERR_i.BLIF un2_clk_pre_66_i.BLIF state_machine_un30_clk_000_d0_i_n.BLIF un6_clk_pre_66_i.BLIF sm_amiga_i_3__n.BLIF CLK_PRE_66_0.BLIF SM_AMIGA_0_sqmuxa_1_i.BLIF cpu_est_ns_0_1_1__n.BLIF \
CLK_000_D3_i.BLIF cpu_est_ns_0_2_1__n.BLIF CLK_000_D2_i.BLIF N_91_i_1.BLIF cpu_est_i_1__n.BLIF un5_ciin_1.BLIF cpu_est_i_0__n.BLIF un5_ciin_2.BLIF cpu_est_i_3__n.BLIF \
un5_ciin_3.BLIF state_machine_un38_clk_000_d0_1_i_n.BLIF un5_ciin_4.BLIF AS_030_000_SYNC_i.BLIF un5_ciin_5.BLIF CLK_000_D4_i.BLIF un5_ciin_6.BLIF sm_amiga_i_5__n.BLIF un5_ciin_7.BLIF \
sm_amiga_i_6__n.BLIF un5_ciin_8.BLIF a_i_19__n.BLIF un5_ciin_9.BLIF a_i_18__n.BLIF un5_ciin_10.BLIF AS_030_i.BLIF un5_ciin_11.BLIF a_i_16__n.BLIF \
state_machine_un8_bg_030_1_n.BLIF AS_030_000_SYNC_0_sqmuxa_i.BLIF state_machine_un8_bg_030_2_n.BLIF N_95_i.BLIF un12_ciin_1.BLIF BGACK_030_INT_i.BLIF un12_ciin_2.BLIF BGACK_030_INT_D_i.BLIF un12_ciin_3.BLIF \
AS_000_i.BLIF un12_ciin_4.BLIF CLK_030_i.BLIF un12_ciin_5.BLIF AS_000_DMA_i.BLIF un12_ciin_6.BLIF state_machine_un24_bgack_030_int_i_n.BLIF AS_030_000_SYNC_0_sqmuxa_1.BLIF RW_000_i.BLIF \
AS_030_000_SYNC_0_sqmuxa_2.BLIF UDS_000_i.BLIF state_machine_un38_clk_000_d0_1_0_n.BLIF LDS_000_i.BLIF state_machine_un5_clk_000_d0_1_n.BLIF state_machine_un8_bgack_030_int_i_n.BLIF state_machine_un5_clk_000_d0_2_n.BLIF CLK_030_H_1_sqmuxa_1_i.BLIF state_machine_un10_clk_000_d0_1_n.BLIF \
DS_000_DMA_1_sqmuxa_1_i.BLIF state_machine_un10_clk_000_d0_2_0_n.BLIF DTACK_i.BLIF state_machine_un10_clk_000_d0_3_n.BLIF sm_amiga_i_7__n.BLIF N_175_1_0.BLIF N_111_i.BLIF un3_dtack_i_1.BLIF nEXP_SPACE_i.BLIF \
un1_bgack_030_int_d_0_1.BLIF RW_i.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF state_machine_un31_bgack_030_int_i_n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF VPA_D_i.BLIF state_machine_un7_ds_030_i_1_n.BLIF VPA_i.BLIF un19_fpu_cs_1.BLIF \
VMA_INT_i.BLIF un19_fpu_cs_2.BLIF cpu_est_i_2__n.BLIF un19_fpu_cs_3.BLIF N_165_i_0.BLIF un19_fpu_cs_4.BLIF DSACK1_INT_0_sqmuxa_i.BLIF un19_fpu_cs_5.BLIF N_96_i.BLIF \
un19_fpu_cs_6.BLIF a_i_31__n.BLIF DSACK1_INT_0_sqmuxa_1.BLIF a_i_30__n.BLIF SM_AMIGA_0_sqmuxa_1_1.BLIF a_i_29__n.BLIF cpu_est_ns_0_1_2__n.BLIF a_i_28__n.BLIF state_machine_clk_000_p_sync_3_1_0__n.BLIF \
a_i_27__n.BLIF DS_000_ENABLE_0_sqmuxa_1.BLIF a_i_26__n.BLIF N_101_1.BLIF a_i_25__n.BLIF N_101_2.BLIF a_i_24__n.BLIF N_101_3.BLIF un5_ciin_i.BLIF \
N_100_1.BLIF un12_ciin_i.BLIF N_98_1.BLIF clk_cnt_n_i_0__n.BLIF N_97_1.BLIF N_107_1.BLIF RST_i.BLIF sm_amiga_ns_0_1_0__n.BLIF AS_030.PIN \
AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN \
DTACK.PIN RW.PIN
.outputs IPL_030_2_ BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET \
AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.D cpu_est_1_.C \
cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \
SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_P_0_.D CLK_CNT_P_0_.C CLK_CNT_P_0_.AR \
CLK_CNT_P_1_.D CLK_CNT_P_1_.C CLK_CNT_P_1_.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C \
IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D \
SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_0_.AR \
CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_1_.AR CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_2_.AR CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_3_.AR CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C \
CLK_000_P_SYNC_4_.AR CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_5_.AR CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_6_.AR CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_7_.AR CLK_000_P_SYNC_8_.D \
CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_8_.AR CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_9_.AR CLK_CNT_N_0_.D CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.D CLK_CNT_N_1_.C CLK_CNT_N_1_.AP \
inst_RW_000_INT.D inst_RW_000_INT.C inst_RW_000_INT.AP inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C \
inst_CLK_OUT_PRE_25.AR inst_AMIGA_BUS_ENABLE_INTreg.D inst_AMIGA_BUS_ENABLE_INTreg.C inst_AMIGA_BUS_ENABLE_INTreg.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_000_INT.AP inst_DS_000_ENABLE.D \
inst_DS_000_ENABLE.C inst_DS_000_ENABLE.AR BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP \
inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_CLK_030_H.D inst_CLK_030_H.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_DMA.AP \
inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_CLK_OUT_PRE_33reg.D inst_CLK_OUT_PRE_33reg.C \
inst_CLK_OUT_PRE_33reg.AR inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP RESETDFFRHreg.D \
RESETDFFRHreg.C RESETDFFRHreg.AR CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP \
inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_D.AR inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C \
inst_VPA_D.AP inst_avec_expreg.D inst_avec_expreg.C inst_avec_expreg.AR inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR CLK_OUT_PRE_25_0.X1 CLK_OUT_PRE_25_0.X2 G_108.X1 G_108.X2 \
G_114.X1 G_114.X2 cpu_estse.X1 cpu_estse.X2 SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ sm_amiga_ns_0_2_0__n CLK_OSZI_i sm_amiga_ns_0_3_0__n uds_000_int_0_un3_n uds_000_int_0_un1_n un16_ciin_i uds_000_int_0_un0_n \
CLK_OUT_PRE_50_D_i ipl_030_0_0__un3_n AS_030_c ipl_030_0_0__un1_n vcc_n_n ipl_030_0_0__un0_n AS_000_c ipl_030_0_1__un3_n ipl_030_0_1__un1_n RW_000_c ipl_030_0_1__un0_n \
ipl_030_0_2__un3_n DS_030_c ipl_030_0_2__un1_n ipl_030_0_2__un0_n UDS_000_c cpu_estse_0_un3_n cpu_estse_0_un1_n LDS_000_c cpu_estse_0_un0_n cpu_estse_1_un3_n size_c_0__n \
cpu_estse_1_un1_n cpu_estse_1_un0_n size_c_1__n cpu_estse_2_un3_n cpu_estse_2_un1_n a_c_16__n cpu_estse_2_un0_n as_030_000_sync_0_un3_n a_c_17__n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n \
a_c_18__n ds_000_enable_0_un3_n ds_000_enable_0_un1_n a_c_19__n ds_000_enable_0_un0_n lds_000_int_0_un3_n a_c_20__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_21__n bgack_030_int_0_un3_n \
bgack_030_int_0_un1_n a_c_22__n bgack_030_int_0_un0_n amiga_bus_enable_int_0_un3_n a_c_23__n amiga_bus_enable_int_0_un1_n amiga_bus_enable_int_0_un0_n a_c_24__n ds_000_dma_0_un3_n state_machine_un3_clk_out_pre_50_n ds_000_dma_0_un1_n \
a_c_25__n ds_000_dma_0_un0_n as_000_dma_0_un3_n un1_LDS_000_INT a_c_26__n as_000_dma_0_un1_n as_000_dma_0_un0_n a_c_27__n clk_030_h_0_un3_n un1_UDS_000_INT clk_030_h_0_un1_n \
a_c_28__n clk_030_h_0_un0_n rw_000_dma_0_un3_n a_c_29__n rw_000_dma_0_un1_n rw_000_dma_0_un0_n a_c_30__n vma_int_0_un3_n vma_int_0_un1_n a_c_31__n vma_int_0_un0_n \
as_000_int_0_un3_n A0_c as_000_int_0_un1_n as_000_int_0_un0_n nEXP_SPACE_c dsack1_int_0_un3_n dsack1_int_0_un1_n BERR_c dsack1_int_0_un0_n rw_000_int_0_un3_n BG_030_c \
rw_000_int_0_un1_n rw_000_int_0_un0_n bg_000_0_un3_n bg_000_0_un1_n un19_fpu_cs bg_000_0_un0_n un5_ciin BGACK_000_c CLK_030_c un16_ciin CLK_OSZI_c \
ipl_c_0__n ipl_c_1__n ipl_c_2__n DSACK1_c DTACK_c VPA_c RST_c RW_c fc_c_0__n un6_clk_pre_66 un2_clk_pre_66 \
fc_c_1__n N_96 state_machine_un34_clk_000_d0_n state_machine_un16_clk_000_d0_n AMIGA_BUS_DATA_DIR_c N_88 N_111 state_machine_un8_bgack_030_int_n N_175_1 UDS_000_INT_i state_machine_un10_clk_000_d0_2_n \
un1_UDS_000_INT_0 state_machine_un38_clk_000_d0_1_n SM_AMIGA_0_sqmuxa_i N_171 DS_000_ENABLE_0_sqmuxa_i cpu_est_ns_1__n un1_SM_AMIGA_0_sqmuxa_2_i DSACK1_INT_0_sqmuxa N_100_i state_machine_un1_as_030_n sm_amiga_ns_0_0__n \
AS_030_000_SYNC_0_sqmuxa N_102_i state_machine_un10_bg_030_n N_103_i un8_ciin sm_amiga_ns_0_1__n un12_ciin N_106_i un14_ciin N_105_i state_machine_un8_bg_030_n \
sm_amiga_ns_0_3__n AS_000_INT_1_sqmuxa N_107_i DSACK1_INT_1_sqmuxa sm_amiga_ns_0_4__n state_machine_rw_000_int_3_n N_108_i N_71 N_109_i state_machine_un12_clk_000_d0_n sm_amiga_ns_0_5__n \
state_machine_un10_clk_000_d0_n N_110_i state_machine_un5_clk_000_d0_n N_163 N_88_i N_164 N_90_i N_165 N_93_0 state_machine_un38_clk_000_d0_n N_97_i \
state_machine_un31_bgack_030_int_n N_98_i N_174 N_99_i N_175 N_101_i N_112 sm_amiga_i_4__n state_machine_un32_clk_000_d0_n N_91_i state_machine_clk_030_h_2_n \
N_168_i DS_000_DMA_1_sqmuxa_1 cpu_est_ns_0_2__n AS_000_DMA_1_sqmuxa state_machine_un10_clk_000_d0_2_i_n CLK_030_H_1_sqmuxa_1 N_167_i DS_000_DMA_1_sqmuxa N_170_i state_machine_un24_bgack_030_int_n N_169_i \
state_machine_un10_bgack_030_int_n N_160_i state_machine_clk_030_h_2_f1_n N_92_0 CLK_030_H_1_sqmuxa N_104_i un1_bgack_030_int_d un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un1_as_030_i_n state_machine_un3_bgack_030_int_d_n state_machine_un6_clk_000_p_sync_i_n \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 state_machine_un6_bgack_000_0_n SM_AMIGA_0_sqmuxa_1 LDS_000_INT_i AMIGA_BUS_ENABLE_INT_3_sqmuxa un1_LDS_000_INT_0 AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un7_ds_030_i_n AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 A0_c_i N_95 \
size_c_i_1__n un1_AS_030_000_SYNC_0_sqmuxa_1 state_machine_un5_bgack_030_int_d_i_n un1_SM_AMIGA_0_sqmuxa_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i un2_as_030 AMIGA_BUS_ENABLE_INT_2_sqmuxa_i state_machine_un6_bgack_000_n un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 state_machine_un6_clk_000_p_sync_n state_machine_un3_bgack_030_int_d_i_n \
N_104 un1_bgack_030_int_d_0 N_92 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i cpu_est_ns_2__n AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i N_167 un3_dtack_i N_168 CLK_030_H_i N_169 \
CLK_030_H_1_sqmuxa_i N_170 state_machine_clk_030_h_2_f1_0_n N_102 state_machine_un10_bgack_030_int_0_n DS_000_ENABLE_0_sqmuxa state_machine_un38_clk_000_d0_i_n N_101 state_machine_un32_clk_000_d0_i_n N_90 state_machine_un34_clk_000_d0_0_n \
N_91 N_112_i N_100 sm_amiga_ns_0_7__n state_machine_un30_clk_000_d0_n N_175_i N_98 N_174_i N_97 AMIGA_BUS_DATA_DIR_c_0 N_107 \
state_machine_size_dma_4_0_1__n N_99 state_machine_size_dma_4_0_0__n N_93 N_171_i N_110 N_164_i N_108 N_163_i N_109 cpu_est_ns_0_1__n \
SM_AMIGA_0_sqmuxa state_machine_un10_clk_000_d0_i_n N_105 state_machine_un5_clk_000_d0_i_n N_106 state_machine_un12_clk_000_d0_0_n N_103 N_71_0 un19_fpu_cs_i state_machine_rw_000_int_3_0_n CLK_000_D1_i \
BG_030_c_i sm_amiga_i_1__n state_machine_un8_bg_030_i_n sm_amiga_i_0__n state_machine_un10_bg_030_0_n CLK_000_D0_i un8_ciin_i sm_amiga_i_2__n un14_ciin_0 BERR_i un2_clk_pre_66_i \
state_machine_un30_clk_000_d0_i_n un6_clk_pre_66_i sm_amiga_i_3__n CLK_PRE_66_0 SM_AMIGA_0_sqmuxa_1_i cpu_est_ns_0_1_1__n CLK_000_D3_i cpu_est_ns_0_2_1__n CLK_000_D2_i N_91_i_1 cpu_est_i_1__n \
un5_ciin_1 cpu_est_i_0__n un5_ciin_2 cpu_est_i_3__n un5_ciin_3 state_machine_un38_clk_000_d0_1_i_n un5_ciin_4 AS_030_000_SYNC_i un5_ciin_5 CLK_000_D4_i un5_ciin_6 \
sm_amiga_i_5__n un5_ciin_7 sm_amiga_i_6__n un5_ciin_8 a_i_19__n un5_ciin_9 a_i_18__n un5_ciin_10 AS_030_i un5_ciin_11 a_i_16__n \
state_machine_un8_bg_030_1_n AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n N_95_i un12_ciin_1 BGACK_030_INT_i un12_ciin_2 BGACK_030_INT_D_i un12_ciin_3 AS_000_i un12_ciin_4 \
CLK_030_i un12_ciin_5 AS_000_DMA_i un12_ciin_6 state_machine_un24_bgack_030_int_i_n AS_030_000_SYNC_0_sqmuxa_1 RW_000_i AS_030_000_SYNC_0_sqmuxa_2 UDS_000_i state_machine_un38_clk_000_d0_1_0_n LDS_000_i \
state_machine_un5_clk_000_d0_1_n state_machine_un8_bgack_030_int_i_n state_machine_un5_clk_000_d0_2_n CLK_030_H_1_sqmuxa_1_i state_machine_un10_clk_000_d0_1_n DS_000_DMA_1_sqmuxa_1_i state_machine_un10_clk_000_d0_2_0_n DTACK_i state_machine_un10_clk_000_d0_3_n sm_amiga_i_7__n N_175_1_0 \
N_111_i un3_dtack_i_1 nEXP_SPACE_i un1_bgack_030_int_d_0_1 RW_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 state_machine_un31_bgack_030_int_i_n AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 VPA_D_i state_machine_un7_ds_030_i_1_n VPA_i \
un19_fpu_cs_1 VMA_INT_i un19_fpu_cs_2 cpu_est_i_2__n un19_fpu_cs_3 N_165_i_0 un19_fpu_cs_4 DSACK1_INT_0_sqmuxa_i un19_fpu_cs_5 N_96_i un19_fpu_cs_6 \
a_i_31__n DSACK1_INT_0_sqmuxa_1 a_i_30__n SM_AMIGA_0_sqmuxa_1_1 a_i_29__n cpu_est_ns_0_1_2__n a_i_28__n state_machine_clk_000_p_sync_3_1_0__n a_i_27__n DS_000_ENABLE_0_sqmuxa_1 a_i_26__n \
N_101_1 a_i_25__n N_101_2 a_i_24__n N_101_3 un5_ciin_i N_100_1 un12_ciin_i N_98_1 clk_cnt_n_i_0__n N_97_1 \
N_107_1 RST_i sm_amiga_ns_0_1_0__n AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE \
SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE CIIN.OE
.names inst_AS_000_DMA.BLIF AS_030
1 1
.names AS_030.PIN AS_030_c
1 1
.names un3_dtack_i.BLIF AS_030.OE
1 1
.names inst_AS_000_INT.BLIF AS_000
1 1
.names AS_000.PIN AS_000_c
1 1
.names inst_BGACK_030_INTreg.BLIF AS_000.OE
1 1
.names inst_RW_000_INT.BLIF RW_000
1 1
.names RW_000.PIN RW_000_c
1 1
.names inst_BGACK_030_INTreg.BLIF RW_000.OE
1 1
.names inst_DS_000_DMA.BLIF DS_030
1 1
.names DS_030.PIN DS_030_c
1 1
.names un3_dtack_i.BLIF DS_030.OE
1 1
.names un1_UDS_000_INT.BLIF UDS_000
1 1
.names UDS_000.PIN UDS_000_c
1 1
.names inst_BGACK_030_INTreg.BLIF UDS_000.OE
1 1
.names un1_LDS_000_INT.BLIF LDS_000
1 1
.names LDS_000.PIN LDS_000_c
1 1
.names inst_BGACK_030_INTreg.BLIF LDS_000.OE
1 1
.names SIZE_DMA_0_.BLIF SIZE_0_
1 1
.names SIZE_0_.PIN size_c_0__n
1 1
.names un3_dtack_i.BLIF SIZE_0_.OE
1 1
.names SIZE_DMA_1_.BLIF SIZE_1_
1 1
.names SIZE_1_.PIN size_c_1__n
1 1
.names un3_dtack_i.BLIF SIZE_1_.OE
1 1
.names inst_A0_DMA.BLIF A0
1 1
.names A0.PIN A0_c
1 1
.names un3_dtack_i.BLIF A0.OE
1 1
.names inst_DSACK1_INT.BLIF DSACK1
1 1
.names DSACK1.PIN DSACK1_c
1 1
.names nEXP_SPACE_c.BLIF DSACK1.OE
1 1
.names DSACK1_c.BLIF DTACK
1 1
.names DTACK.PIN DTACK_c
1 1
.names un3_dtack_i.BLIF DTACK.OE
1 1
.names inst_RW_000_DMA.BLIF RW
1 1
.names RW.PIN RW_c
1 1
.names BGACK_030_INT_i.BLIF RW.OE
1 1
.names un5_ciin.BLIF CIIN
1 1
.names un16_ciin_i.BLIF CIIN.OE
1 1
.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n
11 1
.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_164
11 1
.names sm_amiga_i_2__n.BLIF sm_amiga_i_4__n.BLIF N_91_i_1
11 1
.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_165
11 1
.names N_91_i_1.BLIF sm_amiga_i_6__n.BLIF N_91_i
11 1
.names VPA_c.BLIF VPA_i
0 1
.names CLK_OSZI_i.BLIF CLK_CNT_N_0_.C
1 1
.names state_machine_un34_clk_000_d0_0_n.BLIF state_machine_un34_clk_000_d0_n
0 1
.names inst_VMA_INTreg.BLIF VMA_INT_i
0 1
.names N_112.BLIF N_112_i
0 1
.names inst_VPA_D.BLIF VPA_D_i
0 1
.names RST_i.BLIF CLK_CNT_N_0_.AR
1 1
.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D
0 1
.names LDS_000_i.BLIF UDS_000_i.BLIF state_machine_un31_bgack_030_int_n
11 1
.names N_175.BLIF N_175_i
0 1
.names state_machine_un31_bgack_030_int_n.BLIF state_machine_un31_bgack_030_int_i_n
0 1
.names N_174.BLIF N_174_i
0 1
.names state_machine_un8_bgack_030_int_n.BLIF state_machine_un31_bgack_030_int_n.BLIF state_machine_size_dma_4_0_0__n
11 1
.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.D
1 1
.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c
0 1
.names state_machine_un8_bgack_030_int_n.BLIF state_machine_un31_bgack_030_int_i_n.BLIF state_machine_size_dma_4_0_1__n
11 1
.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D
0 1
.names a_c_24__n.BLIF a_i_24__n
0 1
.names CLK_OSZI_i.BLIF CLK_CNT_N_1_.C
1 1
.names state_machine_size_dma_4_0_0__n.BLIF SIZE_DMA_0_.D
0 1
.names a_c_27__n.BLIF a_i_27__n
0 1
.names N_171.BLIF N_171_i
0 1
.names a_c_26__n.BLIF a_i_26__n
0 1
.names RST_i.BLIF CLK_CNT_N_1_.AP
1 1
.names N_164.BLIF N_164_i
0 1
.names a_c_29__n.BLIF a_i_29__n
0 1
.names N_163.BLIF N_163_i
0 1
.names a_c_28__n.BLIF a_i_28__n
0 1
.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n
0 1
.names a_c_31__n.BLIF a_i_31__n
0 1
.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n
0 1
.names a_c_30__n.BLIF a_i_30__n
0 1
.names CLK_OSZI_c.BLIF inst_RW_000_INT.C
1 1
.names state_machine_un5_clk_000_d0_n.BLIF state_machine_un5_clk_000_d0_i_n
0 1
.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n
0 1
.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n
0 1
.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n
11 1
.names RST_i.BLIF inst_RW_000_INT.AP
1 1
.names A0_c.BLIF A0_c_i
0 1
.names N_96_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
11 1
.names size_c_1__n.BLIF size_c_i_1__n
0 1
.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D
1- 1
-1 1
.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i
0 1
.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n
0 1
.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i
0 1
.names inst_DSACK1_INT.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n
11 1
.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C
1 1
.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa
0 1
.names DSACK1_INT_0_sqmuxa_i.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n
11 1
.names state_machine_un3_bgack_030_int_d_n.BLIF state_machine_un3_bgack_030_int_d_i_n
0 1
.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D
1- 1
-1 1
.names RST_i.BLIF inst_VMA_INTreg.AP
1 1
.names un1_bgack_030_int_d_0.BLIF un1_bgack_030_int_d
0 1
.names N_71.BLIF rw_000_int_0_un3_n
0 1
.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i
0 1
.names state_machine_rw_000_int_3_n.BLIF N_71.BLIF rw_000_int_0_un1_n
11 1
.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i
0 1
.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n
11 1
.names inst_CLK_030_H.BLIF CLK_030_H_i
0 1
.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D
1- 1
-1 1
.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C
1 1
.names CLK_030_H_1_sqmuxa.BLIF CLK_030_H_1_sqmuxa_i
0 1
.names RW_i.BLIF sm_amiga_i_7__n.BLIF state_machine_rw_000_int_3_0_n
11 1
.names state_machine_clk_030_h_2_f1_0_n.BLIF state_machine_clk_030_h_2_f1_n
0 1
.names N_96_i.BLIF sm_amiga_i_7__n.BLIF N_71_0
11 1
.names RST_i.BLIF inst_BGACK_030_INTreg.AP
1 1
.names state_machine_un10_bgack_030_int_0_n.BLIF state_machine_un10_bgack_030_int_n
0 1
.names N_96.BLIF N_96_i
0 1
.names state_machine_un38_clk_000_d0_n.BLIF state_machine_un38_clk_000_d0_i_n
0 1
.names N_96_i.BLIF state_machine_un1_as_030_i_n.BLIF AS_000_INT_1_sqmuxa
11 1
.names state_machine_un32_clk_000_d0_n.BLIF state_machine_un32_clk_000_d0_i_n
0 1
.names DSACK1_INT_0_sqmuxa.BLIF DSACK1_INT_0_sqmuxa_i
0 1
.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
0 1
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C
1 1
.names N_91_i.BLIF N_91
0 1
.names CLK_CNT_N_1_.BLIF CLK_CNT_P_1_.BLIF un6_clk_pre_66
11 1
.names N_168.BLIF N_168_i
0 1
.names CLK_CNT_N_0_.BLIF clk_cnt_n_i_0__n
0 1
.names RST_i.BLIF inst_CLK_OUT_PRE_25.AR
1 1
.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n
0 1
.names clk_cnt_n_i_0__n.BLIF CLK_CNT_P_0_.BLIF un2_clk_pre_66
11 1
.names state_machine_un10_clk_000_d0_2_n.BLIF state_machine_un10_clk_000_d0_2_i_n
0 1
.names un2_clk_pre_66_i.BLIF un6_clk_pre_66_i.BLIF CLK_PRE_66_0
11 1
.names N_167.BLIF N_167_i
0 1
.names N_170.BLIF N_170_i
0 1
.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_INTreg.C
1 1
.names N_169.BLIF N_169_i
0 1
.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n
0 1
.names N_92_0.BLIF N_92
0 1
.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n
11 1
.names RST_i.BLIF inst_AMIGA_BUS_ENABLE_INTreg.AP
1 1
.names N_104.BLIF N_104_i
0 1
.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
11 1
.names state_machine_un1_as_030_i_n.BLIF state_machine_un1_as_030_n
0 1
.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D
1- 1
-1 1
.names state_machine_un6_clk_000_p_sync_n.BLIF state_machine_un6_clk_000_p_sync_i_n
0 1
.names un12_ciin.BLIF un12_ciin_i
0 1
.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n
0 1
.names AS_030_i.BLIF un12_ciin_i.BLIF un8_ciin
11 1
.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
1 1
.names inst_LDS_000_INT.BLIF LDS_000_INT_i
0 1
.names nEXP_SPACE_c.BLIF un8_ciin_i.BLIF un14_ciin_0
11 1
.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT
0 1
.names BG_030_c_i.BLIF state_machine_un8_bg_030_i_n.BLIF state_machine_un10_bg_030_0_n
11 1
.names RST_i.BLIF inst_AS_030_000_SYNC.AP
1 1
.names N_105.BLIF N_105_i
0 1
.names un5_ciin.BLIF un5_ciin_i
0 1
.names sm_amiga_ns_0_3__n.BLIF SM_AMIGA_4_.D
0 1
.names un5_ciin_i.BLIF un14_ciin.BLIF un16_ciin
11 1
.names N_107.BLIF N_107_i
0 1
.names a_c_25__n.BLIF a_i_25__n
0 1
.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D
0 1
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
0 1
.names CLK_OSZI_c.BLIF inst_AS_000_INT.C
1 1
.names N_108.BLIF N_108_i
0 1
.names RST_c.BLIF RST_i
0 1
.names N_109.BLIF N_109_i
0 1
.names inst_CLK_OUT_PRE_33reg.BLIF inst_CLK_OUT_PRE_33reg.D
0 1
.names RST_i.BLIF inst_AS_000_INT.AP
1 1
.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D
0 1
.names G_108.BLIF CLK_CNT_N_0_.D
0 1
.names N_110.BLIF N_110_i
0 1
.names CLK_OSZI_c.BLIF CLK_OSZI_i
0 1
.names N_88_i.BLIF N_88
0 1
.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i
0 1
.names N_90_i.BLIF N_90
0 1
.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF state_machine_un3_clk_out_pre_50_n
11 1
.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C
1 1
.names N_93_0.BLIF N_93
0 1
.names un16_ciin.BLIF un16_ciin_i
0 1
.names N_97.BLIF N_97_i
0 1
.names G_114.BLIF CLK_CNT_P_0_.D
0 1
.names RST_i.BLIF inst_DS_000_ENABLE.AR
1 1
.names N_98.BLIF N_98_i
0 1
.names vcc_n_n
1
.names N_99.BLIF N_99_i
0 1
.names N_101.BLIF N_101_i
0 1
.names inst_UDS_000_INT.BLIF UDS_000_INT_i
0 1
.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C
1 1
.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT
0 1
.names SM_AMIGA_0_sqmuxa.BLIF SM_AMIGA_0_sqmuxa_i
0 1
.names RST_i.BLIF BG_000DFFSHreg.AP
1 1
.names DS_000_ENABLE_0_sqmuxa.BLIF DS_000_ENABLE_0_sqmuxa_i
0 1
.names un1_SM_AMIGA_0_sqmuxa_2_i.BLIF un1_SM_AMIGA_0_sqmuxa_2
0 1
.names N_100.BLIF N_100_i
0 1
.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D
0 1
.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C
1 1
.names N_102.BLIF N_102_i
0 1
.names N_103.BLIF N_103_i
0 1
.names RST_i.BLIF inst_DSACK1_INT.AP
1 1
.names sm_amiga_ns_0_1__n.BLIF SM_AMIGA_6_.D
0 1
.names N_106.BLIF N_106_i
0 1
.names inst_CLK_000_D1.BLIF CLK_000_D1_i
0 1
.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF state_machine_un6_clk_000_p_sync_n
11 1
.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C
1 1
.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0
11 1
.names DS_030_c.BLIF uds_000_int_0_un3_n
0 1
.names RST_i.BLIF inst_LDS_000_INT.AP
1 1
.names inst_UDS_000_INT.BLIF DS_030_c.BLIF uds_000_int_0_un1_n
11 1
.names A0_c.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n
11 1
.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D
1- 1
-1 1
.names un19_fpu_cs.BLIF un19_fpu_cs_i
0 1
.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C
1 1
.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n
0 1
.names N_93.BLIF sm_amiga_i_2__n.BLIF N_110
11 1
.names CLK_OSZI_c.BLIF cpu_est_0_.C
1 1
.names RST_i.BLIF inst_UDS_000_INT.AP
1 1
.names N_88_i.BLIF SM_AMIGA_2_.BLIF N_109
11 1
.names SM_AMIGA_3_.BLIF state_machine_un30_clk_000_d0_n.BLIF N_108
11 1
.names RST_i.BLIF cpu_est_0_.AR
1 1
.names N_88_i.BLIF SM_AMIGA_4_.BLIF N_106
11 1
.names inst_CLK_000_D0.BLIF CLK_000_D0_i
0 1
.names CLK_OSZI_c.BLIF inst_A0_DMA.C
1 1
.names CLK_000_D0_i.BLIF SM_AMIGA_5_.BLIF N_105
11 1
.names N_88_i.BLIF SM_AMIGA_6_.BLIF N_103
11 1
.names CLK_OSZI_c.BLIF cpu_est_1_.C
1 1
.names RST_i.BLIF inst_A0_DMA.AP
1 1
.names N_88.BLIF SM_AMIGA_0_.BLIF N_99
11 1
.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
0 1
.names RST_i.BLIF cpu_est_1_.AR
1 1
.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n
0 1
.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_95
11 1
.names CLK_OSZI_c.BLIF inst_CLK_030_H.C
1 1
.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_0_sqmuxa
11 1
.names state_machine_un16_clk_000_d0_n.BLIF state_machine_un34_clk_000_d0_n.BLIF state_machine_un30_clk_000_d0_n
11 1
.names CLK_OSZI_c.BLIF cpu_est_2_.C
1 1
.names DS_000_ENABLE_0_sqmuxa_i.BLIF SM_AMIGA_0_sqmuxa_i.BLIF un1_SM_AMIGA_0_sqmuxa_2_i
11 1
.names SM_AMIGA_0_sqmuxa_1.BLIF SM_AMIGA_0_sqmuxa_1_i
0 1
.names RST_i.BLIF cpu_est_2_.AR
1 1
.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C
1 1
.names SM_AMIGA_7_.BLIF SM_AMIGA_0_sqmuxa_1.BLIF N_102
11 1
.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF N_96
11 1
.names RST_i.BLIF inst_RW_000_DMA.AP
1 1
.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n
0 1
.names state_machine_un30_clk_000_d0_n.BLIF state_machine_un30_clk_000_d0_i_n
0 1
.names CLK_OSZI_c.BLIF cpu_est_3_reg.C
1 1
.names BERR_c.BLIF SM_AMIGA_1_.BLIF N_93_0
11 1
.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_90_i
11 1
.names RST_i.BLIF cpu_est_3_reg.AR
1 1
.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C
1 1
.names BERR_c.BLIF BERR_i
0 1
.names BERR_c.BLIF CLK_000_D0_i.BLIF N_88_i
11 1
.names RST_i.BLIF inst_DS_000_DMA.AP
1 1
.names inst_CLK_000_D0.BLIF N_110_i.BLIF SM_AMIGA_1_.D
11 1
.names N_108_i.BLIF N_109_i.BLIF sm_amiga_ns_0_5__n
11 1
.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C
1 1
.names N_107_i.BLIF SM_AMIGA_0_sqmuxa_i.BLIF sm_amiga_ns_0_4__n
11 1
.names N_105_i.BLIF N_106_i.BLIF sm_amiga_ns_0_3__n
11 1
.names RST_i.BLIF SM_AMIGA_3_.AR
1 1
.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C
1 1
.names N_102_i.BLIF N_103_i.BLIF sm_amiga_ns_0_1__n
11 1
.names CLK_000_D0_i.BLIF SM_AMIGA_1_.BLIF N_111
11 1
.names RST_i.BLIF inst_AS_000_DMA.AP
1 1
.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n
11 1
.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_167
11 1
.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C
1 1
.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_168
11 1
.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D
1 1
.names A_16_.BLIF a_c_16__n
1 1
.names state_machine_un38_clk_000_d0_1_n.BLIF state_machine_un38_clk_000_d0_1_i_n
0 1
.names RST_i.BLIF SM_AMIGA_2_.AR
1 1
.names A_17_.BLIF a_c_17__n
1 1
.names cpu_est_2_.BLIF state_machine_un38_clk_000_d0_1_i_n.BLIF N_169
11 1
.names CLK_OSZI_c.BLIF inst_CLK_000_D4.C
1 1
.names A_18_.BLIF a_c_18__n
1 1
.names cpu_est_3_reg.BLIF cpu_est_i_3__n
0 1
.names A_19_.BLIF a_c_19__n
1 1
.names N_171.BLIF cpu_est_i_3__n.BLIF N_170
11 1
.names RST_i.BLIF inst_CLK_000_D4.AP
1 1
.names A_20_.BLIF a_c_20__n
1 1
.names cpu_est_0_.BLIF cpu_est_i_0__n
0 1
.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C
1 1
.names A_21_.BLIF a_c_21__n
1 1
.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_171
11 1
.names A_22_.BLIF a_c_22__n
1 1
.names N_169_i.BLIF N_170_i.BLIF N_160_i
11 1
.names RST_i.BLIF SM_AMIGA_1_.AR
1 1
.names A_23_.BLIF a_c_23__n
1 1
.names cpu_est_1_.BLIF cpu_est_i_1__n
0 1
.names A_24_.BLIF a_c_24__n
1 1
.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF state_machine_un38_clk_000_d0_1_n
11 1
.names RST_i.BLIF inst_CLK_OUT_PRE_33reg.AR
1 1
.names A_25_.BLIF a_c_25__n
1 1
.names inst_CLK_000_D2.BLIF CLK_000_D2_i
0 1
.names A_26_.BLIF a_c_26__n
1 1
.names inst_CLK_000_D3.BLIF CLK_000_D3_i
0 1
.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C
1 1
.names A_27_.BLIF a_c_27__n
1 1
.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D
1 1
.names A_28_.BLIF a_c_28__n
1 1
.names AS_030_i.BLIF BERR_c.BLIF state_machine_un1_as_030_i_n
11 1
.names RST_i.BLIF SM_AMIGA_0_.AR
1 1
.names A_29_.BLIF a_c_29__n
1 1
.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
0 1
.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C
1 1
.names A_30_.BLIF a_c_30__n
1 1
.names N_92.BLIF sm_amiga_i_6__n.BLIF N_104
11 1
.names A_31_.BLIF a_c_31__n
1 1
.names inst_CLK_000_D0.BLIF N_104_i.BLIF SM_AMIGA_5_.D
11 1
.names RST_i.BLIF inst_CLK_000_D2.AP
1 1
.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
0 1
.names CLK_OSZI_c.BLIF CLK_CNT_P_0_.C
1 1
.names nEXP_SPACE.BLIF nEXP_SPACE_c
1 1
.names BERR_c.BLIF SM_AMIGA_5_.BLIF N_92_0
11 1
.names BERR.BLIF BERR_c
1 1
.names state_machine_un1_as_030_i_n.BLIF un1_SM_AMIGA_0_sqmuxa_2_i.BLIF un2_as_030
11 1
.names RST_i.BLIF CLK_CNT_P_0_.AR
1 1
.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE.D
1 1
.names BG_030.BLIF BG_030_c
1 1
.names inst_CLK_000_D4.BLIF CLK_000_D4_i
0 1
.names BG_000DFFSHreg.BLIF BG_000
1 1
.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
0 1
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C
1 1
.names inst_BGACK_030_INTreg.BLIF BGACK_030
1 1
.names state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_0__un3_n
0 1
.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.D
1 1
.names BGACK_000.BLIF BGACK_000_c
1 1
.names ipl_c_0__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_0__un1_n
11 1
.names RST_i.BLIF inst_CLK_OUT_PRE.AR
1 1
.names CLK_030.BLIF CLK_030_c
1 1
.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
11 1
.names CLK_OSZI_c.BLIF CLK_CNT_P_1_.C
1 1
.names CLK_000.BLIF inst_CLK_000_D0.D
1 1
.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D
1- 1
-1 1
.names CLK_OSZI.BLIF CLK_OSZI_c
1 1
.names state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_1__un3_n
0 1
.names RST_i.BLIF CLK_CNT_P_1_.AR
1 1
.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D
1 1
.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT
1 1
.names ipl_c_1__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_1__un1_n
11 1
.names CLK_OUT_INTreg.BLIF CLK_EXP
1 1
.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
11 1
.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C
1 1
.names un19_fpu_cs_i.BLIF FPU_CS
1 1
.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D
1- 1
-1 1
.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_
1 1
.names state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_2__un3_n
0 1
.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C
1 1
.names RST_i.BLIF inst_CLK_000_D3.AP
1 1
.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
1 1
.names ipl_c_2__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_2__un1_n
11 1
.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
1 1
.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
11 1
.names RST_i.BLIF SIZE_DMA_0_.AP
1 1
.names IPL_0_.BLIF ipl_c_0__n
1 1
.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D
1- 1
-1 1
.names vcc_n_n.BLIF RESETDFFRHreg.D
1 1
.names IPL_1_.BLIF ipl_c_1__n
1 1
.names state_machine_un6_clk_000_p_sync_n.BLIF cpu_estse_0_un3_n
0 1
.names IPL_2_.BLIF ipl_c_2__n
1 1
.names cpu_est_ns_1__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF cpu_estse_0_un1_n
11 1
.names CLK_OSZI_c.BLIF RESETDFFRHreg.C
1 1
.names cpu_est_1_.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n
11 1
.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C
1 1
.names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D
1- 1
-1 1
.names RST_i.BLIF RESETDFFRHreg.AR
1 1
.names vcc_n_n.BLIF AVEC
1 1
.names state_machine_un6_clk_000_p_sync_n.BLIF cpu_estse_1_un3_n
0 1
.names RST_i.BLIF SIZE_DMA_1_.AP
1 1
.names inst_avec_expreg.BLIF AVEC_EXP
1 1
.names cpu_est_ns_2__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF cpu_estse_1_un1_n
11 1
.names cpu_est_3_reg.BLIF E
1 1
.names cpu_est_2_.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n
11 1
.names VPA.BLIF VPA_c
1 1
.names cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF cpu_est_2_.D
1- 1
-1 1
.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C
1 1
.names inst_VMA_INTreg.BLIF VMA
1 1
.names state_machine_un6_clk_000_p_sync_n.BLIF cpu_estse_2_un3_n
0 1
.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C
1 1
.names RST.BLIF RST_c
1 1
.names N_160_i.BLIF state_machine_un6_clk_000_p_sync_n.BLIF cpu_estse_2_un1_n
11 1
.names RST_i.BLIF CLK_OUT_INTreg.AR
1 1
.names RESETDFFRHreg.BLIF RESET
1 1
.names cpu_est_3_reg.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n
11 1
.names RST_i.BLIF IPL_030DFFSH_0_reg.AP
1 1
.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D
1- 1
-1 1
.names FC_0_.BLIF fc_c_0__n
1 1
.names N_95.BLIF N_95_i
0 1
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
.names FC_1_.BLIF fc_c_1__n
1 1
.names N_95_i.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa
11 1
.names inst_AMIGA_BUS_ENABLE_INTreg.BLIF AMIGA_BUS_ENABLE
1 1
.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AS_030_i.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2
11 1
.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C
1 1
.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C
1 1
.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR
1 1
.names un1_AS_030_000_SYNC_0_sqmuxa_1.BLIF as_030_000_sync_0_un3_n
0 1
.names inst_CLK_OUT_PRE_33reg.BLIF AMIGA_BUS_ENABLE_LOW
1 1
.names inst_AS_030_000_SYNC.BLIF un1_AS_030_000_SYNC_0_sqmuxa_1.BLIF as_030_000_sync_0_un1_n
11 1
.names RST_i.BLIF IPL_030DFFSH_1_reg.AP
1 1
.names RST_i.BLIF inst_CLK_000_D1.AP
1 1
.names state_machine_un1_as_030_n.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n
11 1
.names N_98_i.BLIF N_100_i.BLIF sm_amiga_ns_0_2_0__n
11 1
.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D
1- 1
-1 1
.names sm_amiga_ns_0_1_0__n.BLIF sm_amiga_ns_0_2_0__n.BLIF sm_amiga_ns_0_3_0__n
11 1
.names un2_as_030.BLIF ds_000_enable_0_un3_n
0 1
.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
1 1
.names sm_amiga_ns_0_3_0__n.BLIF N_101_i.BLIF sm_amiga_ns_0_0__n
11 1
.names inst_DS_000_ENABLE.BLIF un2_as_030.BLIF ds_000_enable_0_un1_n
11 1
.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C
1 1
.names inst_CLK_000_D0.BLIF RW_c.BLIF DS_000_ENABLE_0_sqmuxa_1
11 1
.names un1_SM_AMIGA_0_sqmuxa_2.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n
11 1
.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C
1 1
.names DS_000_ENABLE_0_sqmuxa_1.BLIF SM_AMIGA_6_.BLIF DS_000_ENABLE_0_sqmuxa
11 1
.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF inst_DS_000_ENABLE.D
1- 1
-1 1
.names RST_i.BLIF IPL_030DFFSH_2_reg.AP
1 1
.names N_90_i.BLIF N_91_i.BLIF N_101_1
11 1
.names DS_030_c.BLIF lds_000_int_0_un3_n
0 1
.names RST_i.BLIF inst_BGACK_030_INT_D.AP
1 1
.names SM_AMIGA_0_sqmuxa_1_i.BLIF sm_amiga_i_0__n.BLIF N_101_2
11 1
.names inst_LDS_000_INT.BLIF DS_030_c.BLIF lds_000_int_0_un1_n
11 1
.names N_101_1.BLIF N_101_2.BLIF N_101_3
11 1
.names state_machine_un7_ds_030_i_n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n
11 1
.names N_101_3.BLIF sm_amiga_i_3__n.BLIF N_101
11 1
.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D
1- 1
-1 1
.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C
1 1
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50_D.D
1 1
.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_100_1
11 1
.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n
0 1
.names N_100_1.BLIF state_machine_un30_clk_000_d0_i_n.BLIF N_100
11 1
.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n
11 1
.names RST_i.BLIF SM_AMIGA_7_.AP
1 1
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50_D.C
1 1
.names N_90.BLIF BERR_i.BLIF N_98_1
11 1
.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n
11 1
.names N_98_1.BLIF inst_CLK_000_D0.BLIF N_98
11 1
.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D
1- 1
-1 1
.names RST_i.BLIF inst_CLK_OUT_PRE_50_D.AR
1 1
.names N_91.BLIF BERR_i.BLIF N_97_1
11 1
.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0
11 1
.names N_97_1.BLIF CLK_000_D0_i.BLIF N_97
11 1
.names AS_030_000_SYNC_0_sqmuxa.BLIF AS_030_000_SYNC_0_sqmuxa_i
0 1
.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C
1 1
.names BERR_c.BLIF SM_AMIGA_3_.BLIF N_107_1
11 1
.names AS_030_000_SYNC_0_sqmuxa_i.BLIF state_machine_un1_as_030_i_n.BLIF un1_AS_030_000_SYNC_0_sqmuxa_1
11 1
.names N_107_1.BLIF state_machine_un30_clk_000_d0_i_n.BLIF N_107
11 1
.names AS_030_c.BLIF AS_030_i
0 1
.names RST_i.BLIF SM_AMIGA_6_.AR
1 1
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C
1 1
.names N_99_i.BLIF N_97_i.BLIF sm_amiga_ns_0_1_0__n
11 1
.names a_c_16__n.BLIF a_i_16__n
0 1
.names AS_030_i.BLIF a_c_17__n.BLIF un19_fpu_cs_1
11 1
.names a_c_19__n.BLIF a_i_19__n
0 1
.names RST_i.BLIF inst_CLK_OUT_PRE_D.AR
1 1
.names a_i_16__n.BLIF a_i_18__n.BLIF un19_fpu_cs_2
11 1
.names a_c_18__n.BLIF a_i_18__n
0 1
.names a_i_19__n.BLIF BGACK_000_c.BLIF un19_fpu_cs_3
11 1
.names BGACK_000_c.BLIF state_machine_un6_clk_000_p_sync_i_n.BLIF state_machine_un6_bgack_000_0_n
11 1
.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C
1 1
.names fc_c_0__n.BLIF fc_c_1__n.BLIF un19_fpu_cs_4
11 1
.names DS_000_DMA_1_sqmuxa_1.BLIF state_machine_un24_bgack_030_int_i_n.BLIF DS_000_DMA_1_sqmuxa
11 1
.names un19_fpu_cs_1.BLIF un19_fpu_cs_2.BLIF un19_fpu_cs_5
11 1
.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_n.BLIF CLK_030_H_1_sqmuxa_1
11 1
.names RST_i.BLIF SM_AMIGA_5_.AR
1 1
.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C
1 1
.names un19_fpu_cs_3.BLIF un19_fpu_cs_4.BLIF un19_fpu_cs_6
11 1
.names CLK_030_c.BLIF CLK_030_i
0 1
.names un19_fpu_cs_5.BLIF un19_fpu_cs_6.BLIF un19_fpu_cs
11 1
.names inst_AS_000_DMA.BLIF AS_000_DMA_i
0 1
.names RST_i.BLIF inst_CLK_000_D0.AP
1 1
.names inst_CLK_000_D3.BLIF CLK_000_D4_i.BLIF DSACK1_INT_0_sqmuxa_1
11 1
.names AS_000_DMA_i.BLIF CLK_030_i.BLIF CLK_030_H_1_sqmuxa
11 1
.names DSACK1_INT_0_sqmuxa_1.BLIF SM_AMIGA_1_.BLIF DSACK1_INT_0_sqmuxa
11 1
.names AS_000_c.BLIF AS_000_i
0 1
.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C
1 1
.names AS_030_000_SYNC_i.BLIF nEXP_SPACE_c.BLIF SM_AMIGA_0_sqmuxa_1_1
11 1
.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_175_1
11 1
.names VPA_c.BLIF inst_VPA_D.D
1 1
.names SM_AMIGA_0_sqmuxa_1_1.BLIF state_machine_un16_clk_000_d0_n.BLIF SM_AMIGA_0_sqmuxa_1
11 1
.names N_175_1.BLIF state_machine_un10_bgack_030_int_n.BLIF state_machine_un8_bgack_030_int_n
11 1
.names RST_i.BLIF SM_AMIGA_4_.AR
1 1
.names N_167_i.BLIF N_168_i.BLIF cpu_est_ns_0_1_2__n
11 1
.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF amiga_bus_enable_int_0_un3_n
0 1
.names CLK_OSZI_c.BLIF inst_VPA_D.C
1 1
.names cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF cpu_est_ns_0_2__n
11 1
.names inst_AMIGA_BUS_ENABLE_INTreg.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF amiga_bus_enable_int_0_un1_n
11 1
.names CLK_000_D2_i.BLIF CLK_000_D3_i.BLIF state_machine_clk_000_p_sync_3_1_0__n
11 1
.names un1_bgack_030_int_d.BLIF amiga_bus_enable_int_0_un3_n.BLIF amiga_bus_enable_int_0_un0_n
11 1
.names RST_i.BLIF inst_VPA_D.AP
1 1
.names state_machine_clk_000_p_sync_3_1_0__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF CLK_000_P_SYNC_0_.D
11 1
.names amiga_bus_enable_int_0_un1_n.BLIF amiga_bus_enable_int_0_un0_n.BLIF inst_AMIGA_BUS_ENABLE_INTreg.D
1- 1
-1 1
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C
1 1
.names state_machine_un10_clk_000_d0_2_n.BLIF inst_AS_000_INT.BLIF state_machine_un10_clk_000_d0_1_n
11 1
.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF state_machine_un3_bgack_030_int_d_n
11 1
.names inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF state_machine_un10_clk_000_d0_2_0_n
11 1
.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_0_sqmuxa_1_i.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1
11 1
.names RST_i.BLIF CLK_000_P_SYNC_0_.AR
1 1
.names state_machine_un10_clk_000_d0_1_n.BLIF state_machine_un10_clk_000_d0_2_0_n.BLIF state_machine_un10_clk_000_d0_3_n
11 1
.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0
11 1
.names CLK_OSZI_c.BLIF inst_avec_expreg.C
1 1
.names state_machine_un10_clk_000_d0_3_n.BLIF cpu_est_i_3__n.BLIF state_machine_un10_clk_000_d0_n
11 1
.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
0 1
.names N_175_1.BLIF RW_c.BLIF N_175_1_0
11 1
.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i
0 1
.names RST_i.BLIF inst_avec_expreg.AR
1 1
.names N_175_1_0.BLIF nEXP_SPACE_i.BLIF N_175
11 1
.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF state_machine_un5_bgack_030_int_d_i_n
11 1
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C
1 1
.names nEXP_SPACE_i.BLIF AS_000_DMA_i.BLIF un3_dtack_i_1
11 1
.names CLK_030_H_1_sqmuxa_1.BLIF CLK_030_H_1_sqmuxa_1_i
0 1
.names un3_dtack_i_1.BLIF BGACK_030_INT_i.BLIF un3_dtack_i
11 1
.names DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n
0 1
.names RST_i.BLIF CLK_000_P_SYNC_1_.AR
1 1
.names state_machine_un3_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF un1_bgack_030_int_d_0_1
11 1
.names inst_DS_000_DMA.BLIF DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n
11 1
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C
1 1
.names un1_bgack_030_int_d_0_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF un1_bgack_030_int_d_0
11 1
.names CLK_030_H_1_sqmuxa_1_i.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n
11 1
.names N_111_i.BLIF sm_amiga_i_0__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1
11 1
.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.D
1- 1
-1 1
.names RST_i.BLIF inst_CLK_OUT_PRE_50.AR
1 1
.names sm_amiga_i_7__n.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_2
11 1
.names state_machine_un8_bgack_030_int_n.BLIF state_machine_un8_bgack_030_int_i_n
0 1
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C
1 1
.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa
11 1
.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n
0 1
.names size_c_i_1__n.BLIF A0_c_i.BLIF state_machine_un7_ds_030_i_1_n
11 1
.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n
11 1
.names RST_i.BLIF CLK_000_P_SYNC_2_.AR
1 1
.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_PRE_25_0.X1
1 1
.names state_machine_un7_ds_030_i_1_n.BLIF size_c_0__n.BLIF state_machine_un7_ds_030_i_n
11 1
.names state_machine_un8_bgack_030_int_i_n.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n
11 1
.names a_i_24__n.BLIF a_i_25__n.BLIF un12_ciin_1
11 1
.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_AS_000_DMA.D
1- 1
-1 1
.names state_machine_un3_clk_out_pre_50_n.BLIF CLK_OUT_PRE_25_0.X2
1 1
.names a_i_26__n.BLIF a_i_27__n.BLIF un12_ciin_2
11 1
.names inst_CLK_030_H.BLIF CLK_030_c.BLIF state_machine_un24_bgack_030_int_n
11 1
.names a_i_28__n.BLIF a_i_29__n.BLIF un12_ciin_3
11 1
.names UDS_000_c.BLIF UDS_000_i
0 1
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C
1 1
.names a_i_30__n.BLIF a_i_31__n.BLIF un12_ciin_4
11 1
.names LDS_000_c.BLIF LDS_000_i
0 1
.names CLK_CNT_N_0_.BLIF G_108.X1
1 1
.names un12_ciin_1.BLIF un12_ciin_2.BLIF un12_ciin_5
11 1
.names LDS_000_c.BLIF UDS_000_c.BLIF state_machine_un10_bgack_030_int_0_n
11 1
.names RST_i.BLIF CLK_000_P_SYNC_3_.AR
1 1
.names un12_ciin_3.BLIF un12_ciin_4.BLIF un12_ciin_6
11 1
.names CLK_030_i.BLIF state_machine_un8_bgack_030_int_n.BLIF AS_000_DMA_1_sqmuxa
11 1
.names CLK_CNT_N_1_.BLIF G_108.X2
1 1
.names un12_ciin_5.BLIF un12_ciin_6.BLIF un12_ciin
11 1
.names UDS_000_c.BLIF state_machine_un8_bgack_030_int_n.BLIF inst_A0_DMA.D
11 1
.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_7_.BLIF AS_030_000_SYNC_0_sqmuxa_1
11 1
.names CLK_030_H_1_sqmuxa_i.BLIF CLK_030_H_i.BLIF state_machine_clk_030_h_2_f1_0_n
11 1
.names nEXP_SPACE_c.BLIF un19_fpu_cs_i.BLIF AS_030_000_SYNC_0_sqmuxa_2
11 1
.names state_machine_clk_030_h_2_f1_n.BLIF state_machine_un8_bgack_030_int_n.BLIF state_machine_clk_030_h_2_n
11 1
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C
1 1
.names CLK_CNT_P_0_.BLIF G_114.X1
1 1
.names AS_030_000_SYNC_0_sqmuxa_1.BLIF AS_030_000_SYNC_0_sqmuxa_2.BLIF AS_030_000_SYNC_0_sqmuxa
11 1
.names RW_000_c.BLIF RW_000_i
0 1
.names state_machine_un38_clk_000_d0_1_n.BLIF VMA_INT_i.BLIF state_machine_un38_clk_000_d0_1_0_n
11 1
.names RW_000_i.BLIF state_machine_un8_bgack_030_int_n.BLIF DS_000_DMA_1_sqmuxa_1
11 1
.names RST_i.BLIF CLK_000_P_SYNC_4_.AR
1 1
.names CLK_CNT_P_1_.BLIF G_114.X2
1 1
.names state_machine_un38_clk_000_d0_1_0_n.BLIF VPA_i.BLIF state_machine_un38_clk_000_d0_n
11 1
.names state_machine_un24_bgack_030_int_n.BLIF state_machine_un24_bgack_030_int_i_n
0 1
.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un5_clk_000_d0_1_n
11 1
.names RW_c.BLIF RW_i
0 1
.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF state_machine_un5_clk_000_d0_2_n
11 1
.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_174
11 1
.names cpu_est_0_.BLIF cpu_estse.X1
1 1
.names state_machine_un5_clk_000_d0_1_n.BLIF state_machine_un5_clk_000_d0_2_n.BLIF state_machine_un5_clk_000_d0_n
11 1
.names N_174_i.BLIF N_175_i.BLIF AMIGA_BUS_DATA_DIR_c_0
11 1
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C
1 1
.names AS_030_i.BLIF a_c_20__n.BLIF un5_ciin_1
11 1
.names nEXP_SPACE_c.BLIF nEXP_SPACE_i
0 1
.names state_machine_un6_clk_000_p_sync_n.BLIF cpu_estse.X2
1 1
.names a_c_21__n.BLIF a_c_22__n.BLIF un5_ciin_2
11 1
.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF state_machine_un16_clk_000_d0_n
11 1
.names RST_i.BLIF CLK_000_P_SYNC_5_.AR
1 1
.names a_c_23__n.BLIF a_i_24__n.BLIF un5_ciin_3
11 1
.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
0 1
.names a_i_25__n.BLIF a_i_26__n.BLIF un5_ciin_4
11 1
.names N_111.BLIF N_111_i
0 1
.names cpu_estse.BLIF cpu_est_0_.D
1 1
.names a_i_31__n.BLIF a_i_27__n.BLIF un5_ciin_5
11 1
.names N_111_i.BLIF N_112_i.BLIF sm_amiga_ns_0_7__n
11 1
.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D
1 1
.names a_i_28__n.BLIF a_i_29__n.BLIF un5_ciin_6
11 1
.names N_88_i.BLIF SM_AMIGA_0_.BLIF N_112
11 1
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C
1 1
.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D
1 1
.names un5_ciin_1.BLIF un5_ciin_2.BLIF un5_ciin_7
11 1
.names state_machine_un32_clk_000_d0_i_n.BLIF state_machine_un38_clk_000_d0_i_n.BLIF state_machine_un34_clk_000_d0_0_n
11 1
.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D
1 1
.names un5_ciin_3.BLIF un5_ciin_4.BLIF un5_ciin_8
11 1
.names DTACK_c.BLIF DTACK_i
0 1
.names RST_i.BLIF CLK_000_P_SYNC_6_.AR
1 1
.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D
1 1
.names un5_ciin_5.BLIF un5_ciin_6.BLIF un5_ciin_9
11 1
.names DTACK_i.BLIF VPA_c.BLIF state_machine_un32_clk_000_d0_n
11 1
.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D
1 1
.names un5_ciin_7.BLIF un5_ciin_8.BLIF un5_ciin_10
11 1
.names RST_c.BLIF clk_030_h_0_un3_n
0 1
.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D
1 1
.names un5_ciin_9.BLIF a_i_30__n.BLIF un5_ciin_11
11 1
.names state_machine_clk_030_h_2_n.BLIF RST_c.BLIF clk_030_h_0_un1_n
11 1
.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D
1 1
.names un5_ciin_10.BLIF un5_ciin_11.BLIF un5_ciin
11 1
.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n
11 1
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C
1 1
.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D
1 1
.names AS_030_c.BLIF inst_CLK_000_D0.BLIF state_machine_un8_bg_030_1_n
11 1
.names clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF inst_CLK_030_H.D
1- 1
-1 1
.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D
1 1
.names CLK_000_D1_i.BLIF nEXP_SPACE_c.BLIF state_machine_un8_bg_030_2_n
11 1
.names DS_000_DMA_1_sqmuxa_1.BLIF DS_000_DMA_1_sqmuxa_1_i
0 1
.names RST_i.BLIF CLK_000_P_SYNC_7_.AR
1 1
.names CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D
1 1
.names state_machine_un8_bg_030_1_n.BLIF state_machine_un8_bg_030_2_n.BLIF state_machine_un8_bg_030_n
11 1
.names AS_000_DMA_1_sqmuxa.BLIF rw_000_dma_0_un3_n
0 1
.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D
1 1
.names N_71_0.BLIF N_71
0 1
.names inst_RW_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF rw_000_dma_0_un1_n
11 1
.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_PRE_D.D
1 1
.names state_machine_rw_000_int_3_0_n.BLIF state_machine_rw_000_int_3_n
0 1
.names DS_000_DMA_1_sqmuxa_1_i.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n
11 1
.names CLK_000_P_SYNC_9_.BLIF inst_avec_expreg.D
1 1
.names BG_030_c.BLIF BG_030_c_i
0 1
.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF inst_RW_000_DMA.D
1- 1
-1 1
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C
1 1
.names state_machine_un8_bg_030_n.BLIF state_machine_un8_bg_030_i_n
0 1
.names DSACK1_INT_0_sqmuxa_i.BLIF state_machine_un1_as_030_i_n.BLIF DSACK1_INT_1_sqmuxa
11 1
.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n
0 1
.names N_165.BLIF N_165_i_0
0 1
.names RST_i.BLIF CLK_000_P_SYNC_8_.AR
1 1
.names un8_ciin.BLIF un8_ciin_i
0 1
.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n
0 1
.names un14_ciin_0.BLIF un14_ciin
0 1
.names N_165_i_0.BLIF state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n
11 1
.names un2_clk_pre_66.BLIF un2_clk_pre_66_i
0 1
.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
11 1
.names un6_clk_pre_66.BLIF un6_clk_pre_66_i
0 1
.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D
1- 1
-1 1
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C
1 1
.names CLK_PRE_66_0.BLIF inst_CLK_OUT_PRE_33reg.C
0 1
.names state_machine_un5_clk_000_d0_i_n.BLIF state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un12_clk_000_d0_0_n
11 1
.names N_163_i.BLIF N_164_i.BLIF cpu_est_ns_0_1_1__n
11 1
.names cpu_est_2_.BLIF cpu_est_i_2__n
0 1
.names RST_i.BLIF CLK_000_P_SYNC_9_.AR
1 1
.names N_165_i_0.BLIF N_171_i.BLIF cpu_est_ns_0_2_1__n
11 1
.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_163
11 1
.end
Reference in New Issue View Git Blame Copy Permalink