Macintosh-HW/GW_Parts
1
0
Fork 0
mirror of https://github.com/garrettsworkshop/GW_Parts.git synced 2024-12-21 02:29:22 +00:00
Code Issues Projects Releases Wiki Activity

Added 16Mx4 DRAM and 1Mx16 DRAM and 4Mx1 DRAM

Browse Source
This commit is contained in:
Zane Kaminski 2021-06-21 12:05:22 -04:00
parent d336a0dcb4
commit 7e46e8a641
2 changed files with 136 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
GW_RAM.dcm
View File

@ -1,9 +1,5 @@
EESchema-DOCLIB Version 2.0
#
$CMP DRAM-16Mx4-SOP-32
F https://shop.micross.com/pdf/AS4C4M4.pdf
$ENDCMP
#
$CMP DRAM-4Mx4-SOP-24
F https://shop.micross.com/pdf/AS4C4M4.pdf
$ENDCMP

136
GW_RAM.lib
View File

@ -48,6 +48,58 @@ X ~RAS~ 9 400 -200 100 L 50 50 1 1 I
ENDDRAW
ENDDEF
#
# DRAM-1Mx16-SOP-42
#
DEF DRAM-1Mx16-SOP-42 U 0 20 Y Y 1 F N
F0 "U" 0 950 50 H V C CNN
F1 "DRAM-1Mx16-SOP-42" 0 0 50 V V C CNN
F2 "stdpads:SOP-42_400mil" 0 -950 50 H I C CNN
F3 "" 0 -350 50 H I C CNN
DRAW
S -300 900 300 -900 0 1 10 f
X VDD 1 -400 800 100 R 50 50 1 1 W
X DQ7 10 400 100 100 L 50 50 1 1 B
X NC 11 400 50 100 L 50 50 1 1 N N
X NC 12 400 0 100 L 50 50 1 1 N N
X ~WE~ 13 -400 -600 100 R 50 50 1 1 I
X ~RAS~ 14 -400 -500 100 R 50 50 1 1 I
X A0 17 -400 700 100 R 50 50 1 1 I
X A1 18 -400 600 100 R 50 50 1 1 I
X A2 19 -400 500 100 R 50 50 1 1 I
X DQ0 2 400 800 100 L 50 50 1 1 B
X A3 20 -400 400 100 R 50 50 1 1 I
X VDD 21 -400 800 100 R 50 50 1 1 W N
X GND 22 -400 -800 100 R 50 50 1 1 W
X A4 23 -400 300 100 R 50 50 1 1 I
X A5 24 -400 200 100 R 50 50 1 1 I
X A6 25 -400 100 100 R 50 50 1 1 I
X A7 26 -400 0 100 R 50 50 1 1 I
X A8 27 -400 -100 100 R 50 50 1 1 I
X A9 28 -400 -200 100 R 50 50 1 1 I
X ~OE~ 29 -400 -700 100 R 50 50 1 1 I
X DQ1 3 400 700 100 L 50 50 1 1 B
X ~UCAS~ 30 -400 -400 100 R 50 50 1 1 I
X ~LCAS~ 31 -400 -300 100 R 50 50 1 1 I
X NC 32 400 -50 100 L 50 50 1 1 N N
X DQ8 33 400 -100 100 L 50 50 1 1 B
X DQ9 34 400 -200 100 L 50 50 1 1 B
X DQ10 35 400 -300 100 L 50 50 1 1 B
X DQ11 36 400 -400 100 L 50 50 1 1 B
X GND 37 -400 -800 100 R 50 50 1 1 W N
X DQ12 38 400 -500 100 L 50 50 1 1 B
X DQ13 39 400 -600 100 L 50 50 1 1 B
X DQ2 4 400 600 100 L 50 50 1 1 B
X DQ14 40 400 -700 100 L 50 50 1 1 B
X DQ15 41 400 -800 100 L 50 50 1 1 B
X GND 42 -400 -800 100 R 50 50 1 1 W N
X DQ3 5 400 500 100 L 50 50 1 1 B
X VDD 6 -400 800 100 R 50 50 1 1 W N
X DQ4 7 400 400 100 L 50 50 1 1 B
X DQ5 8 400 300 100 L 50 50 1 1 B
X DQ6 9 400 200 100 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# DRAM-2Mx8-SOP-28
#
DEF DRAM-2Mx8-SOP-28 U 0 20 Y Y 1 F N
@ -88,6 +140,41 @@ X A10 9 -400 -400 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# DRAM-4Mx1-SOP-20
#
DEF DRAM-4Mx1-SOP-20 U 0 20 Y Y 1 F N
F0 "U" 0 650 50 H V C CNN
F1 "DRAM-4Mx1-SOP-20" 0 0 50 V V C CNN
F2 "stdpads:SOP-24-26-300mil" 0 -650 50 H I C CNN
F3 "" 0 -600 50 H I C CNN
$FPLIST
SOJ*10.16x23.49mm*P1.27mm*
$ENDFPLIST
DRAW
S -300 600 300 -600 0 1 10 f
X D 1 400 400 100 L 50 50 1 1 I
X A1 10 -400 400 100 R 50 50 1 1 I
X A2 11 -400 300 100 R 50 50 1 1 I
X A3 12 -400 200 100 R 50 50 1 1 I
X VDD 13 400 500 100 L 50 50 1 1 W
X A4 14 -400 100 100 R 50 50 1 1 I
X A5 15 -400 0 100 R 50 50 1 1 I
X A6 16 -400 -100 100 R 50 50 1 1 I
X A7 17 -400 -200 100 R 50 50 1 1 I
X A8 18 -400 -300 100 R 50 50 1 1 I
X ~WE~ 2 400 -300 100 L 50 50 1 1 I
X A9 22 -400 -400 100 R 50 50 1 1 I
X NC 23 400 0 100 L 50 50 1 1 N N
X ~CAS~ 24 400 -100 100 L 50 50 1 1 I
X Q 25 400 300 100 L 50 50 1 1 T
X GND 26 400 -500 100 L 50 50 1 1 W
X ~RAS~ 3 400 -200 100 L 50 50 1 1 I
X NC 4 400 50 100 L 50 50 1 1 N N
X A10 5 -400 -500 100 R 50 50 1 1 I
X A0 9 -400 500 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# DRAM-4Mx4-SOP-24
#
DEF DRAM-4Mx4-SOP-24 U 0 20 Y Y 1 F N
@ -552,6 +639,55 @@ X D2 9 400 850 100 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# VRAM-128kx8-SOP-40
#
DEF VRAM-128kx8-SOP-40 U 0 20 Y Y 1 F N
F0 "U" 0 1050 50 H V C CNN
F1 "VRAM-128kx8-SOP-40" 50 0 50 V V C CNN
F2 "stdpads:SOP-24-26-300mil" 0 -1050 50 H I C CNN
F3 "" 0 -250 50 H I C CNN
DRAW
S -300 1000 300 -1000 0 1 10 f
X SC 1 -400 -800 100 R 50 50 1 1 I
X DQ3 10 400 400 100 L 50 50 1 1 B
X VDD 11 400 900 100 L 50 50 1 1 W
X ~ME~/~WE~ 12 -400 -200 100 R 50 50 1 1 I
X ~RAS~ 14 -400 -100 100 R 50 50 1 1 I
X A8 16 -400 100 100 R 50 50 1 1 I
X A6 17 -400 300 100 R 50 50 1 1 I
X A5 18 -400 400 100 R 50 50 1 1 I
X A4 19 -400 500 100 R 50 50 1 1 I
X SQ0 2 400 -200 100 L 50 50 1 1 B
X VDD 20 400 900 100 L 50 50 1 1 W N
X A7 21 -400 200 100 R 50 50 1 1 I
X A3 22 -400 600 100 R 50 50 1 1 I
X A2 23 -400 700 100 R 50 50 1 1 I
X A1 24 -400 800 100 R 50 50 1 1 I
X A0 25 -400 900 100 R 50 50 1 1 I
X QSF 26 -400 -600 100 R 50 50 1 1 O
X ~CAS~ 27 -400 0 100 R 50 50 1 1 I
X DSF 29 -400 -500 100 R 50 50 1 1 I
X SQ1 3 400 -300 100 L 50 50 1 1 B
X GND 30 -400 -900 100 R 50 50 1 1 W N
X DQ4 31 400 300 100 L 50 50 1 1 B
X DQ5 32 400 200 100 L 50 50 1 1 B
X DQ6 33 400 100 100 L 50 50 1 1 B
X DQ7 34 400 0 100 L 50 50 1 1 B
X ~SE~ 35 -400 -400 100 R 50 50 1 1 I
X SQ4 36 400 -600 100 L 50 50 1 1 B
X SQ5 37 400 -700 100 L 50 50 1 1 B
X SQ6 38 400 -800 100 L 50 50 1 1 B
X SQ7 39 400 -900 100 L 50 50 1 1 B
X SQ2 4 400 -400 100 L 50 50 1 1 B
X GND 40 -400 -900 100 R 50 50 1 1 W
X SQ3 5 400 -500 100 L 50 50 1 1 B
X ~TR~/~OE~ 6 -400 -300 100 R 50 50 1 1 I
X DQ0 7 400 700 100 L 50 50 1 1 B
X DQ1 8 400 600 100 L 50 50 1 1 B
X DQ2 9 400 500 100 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# VRAM-256kx8-SOP-40
#
DEF VRAM-256kx8-SOP-40 U 0 20 Y Y 1 F N