mirror of
https://github.com/MiSTer-devel/MacPlus_MiSTer.git
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98 lines
2.7 KiB
Tcl
98 lines
2.7 KiB
Tcl
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# TCL File Generated by Component Editor 17.0
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# Thu Jan 25 06:51:26 CST 2018
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# DO NOT MODIFY
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#
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# out_mix "Output Mixer" v1.0
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# Sorgelig 2018.01.25.06:51:26
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#
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#
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#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module out_mix
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME out_mix
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set_module_property VERSION 17.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property AUTHOR Sorgelig
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set_module_property DISPLAY_NAME "Output Mixer"
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL out_mix
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
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add_fileset_file out_mix.v VERILOG PATH out_mix.v TOP_LEVEL_FILE
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point Output
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#
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add_interface Output conduit end
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set_interface_property Output associatedClock ""
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set_interface_property Output associatedReset ""
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set_interface_property Output ENABLED true
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set_interface_property Output EXPORT_OF ""
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set_interface_property Output PORT_NAME_MAP ""
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set_interface_property Output CMSIS_SVD_VARIABLES ""
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set_interface_property Output SVD_ADDRESS_GROUP ""
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add_interface_port Output clk clk Input 1
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add_interface_port Output de de Output 1
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add_interface_port Output h_sync h_sync Output 1
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add_interface_port Output v_sync v_sync Output 1
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add_interface_port Output data data Output 24
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#
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# connection point input
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#
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add_interface input conduit end
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set_interface_property input associatedClock ""
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set_interface_property input associatedReset ""
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set_interface_property input ENABLED true
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set_interface_property input EXPORT_OF ""
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set_interface_property input PORT_NAME_MAP ""
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set_interface_property input CMSIS_SVD_VARIABLES ""
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set_interface_property input SVD_ADDRESS_GROUP ""
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add_interface_port input vid_clk vid_clk Output 1
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add_interface_port input vid_datavalid vid_datavalid Input 2
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add_interface_port input vid_h_sync vid_h_sync Input 2
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add_interface_port input vid_v_sync vid_v_sync Input 2
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add_interface_port input vid_data vid_data Input 48
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add_interface_port input underflow underflow Input 1
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add_interface_port input vid_mode_change vid_mode_change Input 1
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add_interface_port input vid_std vid_std Input 2
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add_interface_port input vid_f vid_f Input 2
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add_interface_port input vid_h vid_h Input 2
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add_interface_port input vid_v vid_v Input 2
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