diff --git a/MacPlus.sdc b/MacPlus.sdc deleted file mode 100644 index 6372c8e..0000000 --- a/MacPlus.sdc +++ /dev/null @@ -1,5 +0,0 @@ -derive_pll_clocks -derive_clock_uncertainty - -set_multicycle_path -from {emu|m68k|*} -setup 2 -set_multicycle_path -from {emu|m68k|*} -hold 1 diff --git a/MacPlus.sv b/MacPlus.sv index 1de5d97..44cdb8a 100644 --- a/MacPlus.sv +++ b/MacPlus.sv @@ -206,91 +206,79 @@ localparam CONF_STR = { "F1,DSK,Mount Pri Floppy;", "F2,DSK,Mount Sec Floppy;", "-;", - "S0,VHD,Mount HDD;", + "S0,IMGVHD,Mount SCSI6;", + "S1,IMGVHD,Mount SCSI2;", "-;", "O78,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];", "OBC,Scale,Normal,V-Integer,Narrower HV-Integer,Wider HV-Integer;", "-;", - "O9A,Memory,512KB,1MB,4MB;", - "O5,Speed,Normal,Turbo;", + "O4,Memory,1MB,4MB;", + "O5,Speed,8MHz,16MHz;", + "ODE,CPU,FX68K-68000,TG68K-68010,TG68K-68020;", "-;", - "R6,Reset;", + "R0,Reset;", "V,v",`BUILD_DATE }; +wire status_mem = status[4]; +wire status_turbo = status[5]; +wire [1:0] status_cpu = status[14:13]; +wire status_reset = status[0]; + //////////////////// CLOCKS /////////////////// -wire clk_sys; +wire clk_sys, clk_mem; wire pll_locked; pll pll ( .refclk(CLK_50M), - .rst(0), - .outclk_0(clk_sys), + .outclk_0(clk_mem), + .outclk_1(clk_sys), .locked(pll_locked) ); -reg cep,cen,cel,cepix; +reg n_reset = 0; +reg last_mem_config; +reg [1:0] last_cpu_config; always @(posedge clk_sys) begin - reg [2:0] div; + reg [15:0] rst_cnt; - div <= div + 1'd1; + if (clk8_en_p) begin + last_mem_config <= status_mem; + last_cpu_config <= status_cpu; - cep <= (div == 0); - cen <= (div == 4); - cel <= (div == 7); - cepix <= !div[1:0]; + // various sources can reset the mac + if(!pll_locked || status_reset || buttons[1] || RESET || + (last_mem_config != status_mem) || (last_cpu_config != status_cpu) || !_cpuReset_o) begin + rst_cnt <= '1; + n_reset <= 0; + end + else if(rst_cnt) begin + rst_cnt <= rst_cnt - 1'd1; + end + else begin + n_reset <= 1; + end + end end /////////////////////////////////////////////////// -// interconnects -// CPU -wire _cpuReset, _cpuResetOut, _cpuUDS, _cpuLDS, _cpuRW; -wire [2:0] _cpuIPL; -wire [7:0] cpuAddrHi; -wire [23:0] cpuAddr; -wire [15:0] cpuDataOut; - -// RAM/ROM -wire _romOE; -wire _ramOE, _ramWE; -wire _memoryUDS, _memoryLDS; -wire videoBusControl; -wire dioBusControl; -wire cpuBusControl; -wire [21:0] memoryAddr; -wire [15:0] memoryDataOut; - -// peripherals -wire memoryOverlayOn, selectSCSI, selectSCC, selectIWM, selectVIA; -wire [15:0] dataControllerDataOut; - -// audio -wire snd_alt; -wire loadSound; - -// floppy disk image interface -wire dskReadAckInt; -wire [21:0] dskReadAddrInt; -wire dskReadAckExt; -wire [21:0] dskReadAddrExt; -wire [1:0] diskMotor, diskAct, diskEject; - // the status register is controlled by the on screen display (OSD) wire [31:0] status; wire [1:0] buttons; wire [31:0] sd_lba; -wire sd_rd; -wire sd_wr; +wire [1:0] sd_rd; +wire [1:0] sd_wr; wire sd_ack; wire [8:0] sd_buff_addr; wire [7:0] sd_buff_dout; wire [7:0] sd_buff_din; wire sd_buff_wr; +wire [1:0] img_mounted; +wire [31:0] img_size; -reg ioctl_wr; wire ioctl_write; reg ioctl_wait = 0; @@ -301,20 +289,9 @@ wire capslock; wire [24:0] ioctl_addr; wire [7:0] ioctl_data; -always @(posedge clk_sys) begin - reg [7:0] temp; - - ioctl_wr <= 0; - if(ioctl_write) begin - if(~ioctl_addr[0]) temp <= ioctl_data; - else begin - dio_data <= {temp, ioctl_data}; - ioctl_wr <= 1; - end - end -end +wire [32:0] TIMESTAMP; -hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io +hps_io #(.STRLEN($size(CONF_STR)>>3), .VDNUM(2)) hps_io ( .clk_sys(clk_sys), .HPS_BUS(HPS_BUS), @@ -335,14 +312,18 @@ hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io .sd_buff_din(sd_buff_din), .sd_buff_wr(sd_buff_wr), + .img_mounted(img_mounted), + .img_size(img_size), + .ioctl_download(dio_download), .ioctl_index(dio_index), .ioctl_wr(ioctl_write), .ioctl_addr(ioctl_addr), .ioctl_dout(ioctl_data), - .ioctl_wait(ioctl_wait), + .TIMESTAMP(TIMESTAMP), + .ps2_key(ps2_key), .ps2_kbd_led_use(3'b001), .ps2_kbd_led_status({2'b00, capslock}), @@ -350,122 +331,251 @@ hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io .ps2_mouse(ps2_mouse) ); -wire [1:0] cpu_busstate; -wire cpu_clkena = cep && (cpuBusControl || (cpu_busstate == 2'b01)); -reg [15:0] cpuDataIn; -always @(posedge clk_sys) if(cel && cpuBusControl && ~cpu_busstate[0] && _cpuRW) cpuDataIn <= dataControllerDataOut; - -TG68KdotC_Kernel #(0,0,0,0,0,0, 0,1) m68k -( - .clk ( clk_sys ), - .nReset ( _cpuReset ), - .clkena_in ( cpu_clkena ), - .data_in ( cpuDataIn ), - .IPL ( _cpuIPL ), - .IPL_autovector ( 1'b1 ), - .berr ( 1'b0 ), - .clr_berr ( 1'b0 ), - .CPU ( 2'b00 ), // 00=68000 - .addr_out ( {cpuAddrHi, cpuAddr} ), - .data_write ( cpuDataOut ), - .nUDS ( _cpuUDS ), - .nLDS ( _cpuLDS ), - .nWr ( _cpuRW ), - .busstate ( cpu_busstate ), // 00-> fetch code 10->read data 11->write data 01->no memaccess - .nResetOut ( _cpuResetOut ), - .FC ( ) -); - -assign VGA_R = {8{pixelOut}}; -assign VGA_G = {8{pixelOut}}; -assign VGA_B = {8{pixelOut}}; assign CLK_VIDEO = clk_sys; -assign CE_PIXEL = cepix; +assign CE_PIXEL = 1; + +assign VGA_R = {8{pixelOut}}; +assign VGA_G = {8{pixelOut}}; +assign VGA_B = {8{pixelOut}}; +assign VGA_DE = _vblank & _hblank; +assign VGA_VS = vsync; +assign VGA_HS = hsync; assign VGA_F1 = 0; assign VGA_SL = 0; -wire screenWrite; -always @(*) begin - case(configRAMSize) - 0: screenWrite = ~_ramWE && &memoryAddr[16:15]; // 01A700 (018000) - 1: screenWrite = ~_ramWE && &memoryAddr[18:15]; // 07A700 (078000) - 2: screenWrite = ~_ramWE && &memoryAddr[19:15]; // 0FA700 (0F8000) - 3: screenWrite = ~_ramWE && &memoryAddr[21:15]; // 3FA700 (3F8000) - endcase -end - -wire pixelOut, _hblank, _vblank; -video video -( - .clk(clk_sys), - .ce(cepix), - - .addr(cpuAddr[15:1]), - .dataIn(cpuDataOut), - .wr({~_cpuUDS & screenWrite, ~_cpuLDS & screenWrite}), - - ._hblank(_hblank), - ._vblank(_vblank), - - .hsync(VGA_HS), - .vsync(VGA_VS), - .video_en(VGA_DE), - .pixelOut(pixelOut) -); - wire [10:0] audio; assign AUDIO_L = {audio[10:0], 5'b00000}; assign AUDIO_R = {audio[10:0], 5'b00000}; assign AUDIO_S = 0; assign AUDIO_MIX = 0; -wire status_turbo = status[5]; -wire status_reset = status[6]; -wire [1:0] status_mem = status[10:9]; // 128KB, 512KB, 1MB, 4MB -reg [1:0] configRAMSize= 3; +// ------------------------------ Plus Too Bus Timing --------------------------------- +// for stability and maintainability reasons the whole timing has been simplyfied: +// 00 01 10 11 +// ______ _____________ _____________ _____________ _____________ ___ +// ______X_video_cycle_X__cpu_cycle__X__IO_cycle___X__cpu_cycle__X___ +// ^ ^ ^ ^ ^ +// | | | | | +// video | CPU| | CPU| +// read write read write read -reg n_reset = 0; + + +// set the real-world inputs to sane defaults +localparam serialIn = 1'b0, + configROMSize = 1'b1; // 128K ROM + +wire [1:0] configRAMSize = status_mem?2'b11:2'b10; // 1MB/4MB + +// interconnects +// CPU +wire clk8, _cpuReset, _cpuReset_o, _cpuUDS, _cpuLDS, _cpuRW, _cpuAS; +wire clk8_en_p, clk8_en_n; +wire clk16_en_p, clk16_en_n; +wire _cpuVMA, _cpuVPA, _cpuDTACK; +wire E_rising, E_falling; +wire [2:0] _cpuIPL; +wire [2:0] cpuFC; +wire [7:0] cpuAddrHi; +wire [23:0] cpuAddr; +wire [15:0] cpuDataOut; + +// RAM/ROM +wire _romOE; +wire _ramOE, _ramWE; +wire _memoryUDS, _memoryLDS; +wire videoBusControl; +wire dioBusControl; +wire cpuBusControl; +wire [21:0] memoryAddr; +wire [15:0] memoryDataOut; +wire memoryLatch; + +// peripherals +wire vid_alt, loadPixels, pixelOut, _hblank, _vblank, hsync, vsync; +wire memoryOverlayOn, selectSCSI, selectSCC, selectIWM, selectVIA, selectRAM, selectROM; +wire [15:0] dataControllerDataOut; + +// audio +wire snd_alt; +wire loadSound; + +// floppy disk image interface +wire dskReadAckInt; +wire [21:0] dskReadAddrInt; +wire dskReadAckExt; +wire [21:0] dskReadAddrExt; + +// dtack generation in turbo mode +reg turbo_dtack_en, cpuBusControl_d; always @(posedge clk_sys) begin - reg [15:0] rst_cnt; - - // various sources can reset the mac - if(!pll_locked || status[0] || status_reset || buttons[1] || RESET || ~_cpuResetOut) begin - rst_cnt <= '1; - n_reset <= 0; - end else if(rst_cnt) begin - if(cen) rst_cnt <= rst_cnt - 1'd1; - configRAMSize <= status_mem + 1'd1; - end else n_reset <= 1; + if (!_cpuReset) begin + turbo_dtack_en <= 0; + end + else begin + cpuBusControl_d <= cpuBusControl; + if (_cpuAS) turbo_dtack_en <= 0; + if (!_cpuAS & ((!cpuBusControl_d & cpuBusControl) | (!selectROM & !selectRAM))) turbo_dtack_en <= 1; + end end +assign _cpuVPA = (cpuFC == 3'b111) ? 1'b0 : ~(!_cpuAS && cpuAddr[23:21] == 3'b111); +assign _cpuDTACK = ~(!_cpuAS && cpuAddr[23:21] != 3'b111) | (status_turbo & !turbo_dtack_en); + +wire cpu_en_p = status_turbo ? clk16_en_p : clk8_en_p; +wire cpu_en_n = status_turbo ? clk16_en_n : clk8_en_n; + +wire is68000 = status_cpu == 0; +assign _cpuReset_o = is68000 ? fx68_reset_n : tg68_reset_n; +assign _cpuRW = is68000 ? fx68_rw : tg68_rw; +assign _cpuAS = is68000 ? fx68_as_n : tg68_as_n; +assign _cpuUDS = is68000 ? fx68_uds_n : tg68_uds_n; +assign _cpuLDS = is68000 ? fx68_lds_n : tg68_lds_n; +assign E_falling = is68000 ? fx68_E_falling : tg68_E_falling; +assign E_rising = is68000 ? fx68_E_rising : tg68_E_rising; +assign _cpuVMA = is68000 ? fx68_vma_n : tg68_vma_n; +assign cpuFC[0] = is68000 ? fx68_fc0 : tg68_fc0; +assign cpuFC[1] = is68000 ? fx68_fc1 : tg68_fc1; +assign cpuFC[2] = is68000 ? fx68_fc2 : tg68_fc2; +assign cpuAddr[23:1] = is68000 ? fx68_a : tg68_a[23:1]; +assign cpuDataOut = is68000 ? fx68_dout : tg68_dout; + +wire fx68_rw; +wire fx68_as_n; +wire fx68_uds_n; +wire fx68_lds_n; +wire fx68_E_falling; +wire fx68_E_rising; +wire fx68_vma_n; +wire fx68_fc0; +wire fx68_fc1; +wire fx68_fc2; +wire [15:0] fx68_dout; +wire [23:1] fx68_a; +wire fx68_reset_n; + +fx68k fx68k ( + .clk ( clk_sys ), + .extReset ( !_cpuReset ), + .pwrUp ( !_cpuReset ), + .enPhi1 ( cpu_en_p ), + .enPhi2 ( cpu_en_n ), + + .eRWn ( fx68_rw ), + .ASn ( fx68_as_n ), + .LDSn ( fx68_lds_n ), + .UDSn ( fx68_uds_n ), + .E ( ), + .E_div ( status_turbo ), + .E_PosClkEn ( fx68_E_falling ), + .E_NegClkEn ( fx68_E_rising ), + .VMAn ( fx68_vma_n ), + .FC0 ( fx68_fc0 ), + .FC1 ( fx68_fc1 ), + .FC2 ( fx68_fc2 ), + .BGn ( ), + .oRESETn ( fx68_reset_n ), + .oHALTEDn ( ), + .DTACKn ( _cpuDTACK ), + .VPAn ( _cpuVPA ), + .HALTn ( 1'b1 ), + .BERRn ( 1'b1 ), + .BRn ( 1'b1 ), + .BGACKn ( 1'b1 ), + .IPL0n ( _cpuIPL[0] ), + .IPL1n ( _cpuIPL[1] ), + .IPL2n ( _cpuIPL[2] ), + .iEdb ( dataControllerDataOut ), + .oEdb ( fx68_dout ), + .eab ( fx68_a ) +); + +wire tg68_rw; +wire tg68_as_n; +wire tg68_uds_n; +wire tg68_lds_n; +wire tg68_E_rising; +wire tg68_E_falling; +wire tg68_vma_n; +wire tg68_fc0; +wire tg68_fc1; +wire tg68_fc2; +wire [15:0] tg68_dout; +wire [31:0] tg68_a; +wire tg68_reset_n; + +tg68k tg68k ( + .clk ( clk_sys ), + .reset ( !_cpuReset ), + .phi1 ( clk8_en_p ), + .phi2 ( clk8_en_n ), + .cpu ( {status_cpu[1], |status_cpu} ), + + .dtack_n ( _cpuDTACK ), + .rw_n ( tg68_rw ), + .as_n ( tg68_as_n ), + .uds_n ( tg68_uds_n ), + .lds_n ( tg68_lds_n ), + .fc ( { tg68_fc2, tg68_fc1, tg68_fc0 } ), + .reset_n ( tg68_reset_n ), + + .E ( ), + .E_div ( status_turbo ), + .E_PosClkEn ( tg68_E_falling ), + .E_NegClkEn ( tg68_E_rising ), + .vma_n ( tg68_vma_n ), + .vpa_n ( _cpuVPA ), + + .br_n ( 1'b1 ), + .bg_n ( ), + .bgack_n ( 1'b1 ), + + .ipl ( _cpuIPL ), + .berr ( 1'b0 ), + .din ( dataControllerDataOut ), + .dout ( tg68_dout ), + .addr ( tg68_a ) +); + addrController_top ac0 ( .clk(clk_sys), - .cep(cep), - .cen(cen), - - .cpuAddr(cpuAddr), + .clk8(clk8), + .clk8_en_p(clk8_en_p), + .clk8_en_n(clk8_en_n), + .clk16_en_p(clk16_en_p), + .clk16_en_n(clk16_en_n), + .cpuAddr(cpuAddr), ._cpuUDS(_cpuUDS), ._cpuLDS(_cpuLDS), ._cpuRW(_cpuRW), - .turbo(real_turbo), - .configROMSize(1), // 128KB - .configRAMSize(configRAMSize), + ._cpuAS(_cpuAS), + .turbo(status_turbo), + .configROMSize(configROMSize), + .configRAMSize(configRAMSize), .memoryAddr(memoryAddr), + .memoryLatch(memoryLatch), ._memoryUDS(_memoryUDS), ._memoryLDS(_memoryLDS), - ._romOE(_romOE), - ._ramOE(_ramOE), + ._romOE(_romOE), + ._ramOE(_ramOE), ._ramWE(_ramWE), - .dioBusControl(dioBusControl), - .cpuBusControl(cpuBusControl), + .videoBusControl(videoBusControl), + .dioBusControl(dioBusControl), + .cpuBusControl(cpuBusControl), .selectSCSI(selectSCSI), .selectSCC(selectSCC), .selectIWM(selectIWM), .selectVIA(selectVIA), - ._vblank(_vblank), + .selectRAM(selectRAM), + .selectROM(selectROM), + .hsync(hsync), + .vsync(vsync), ._hblank(_hblank), + ._vblank(_vblank), + .loadPixels(loadPixels), + .vid_alt(vid_alt), .memoryOverlayOn(memoryOverlayOn), .snd_alt(snd_alt), @@ -477,18 +587,23 @@ addrController_top ac0 .dskReadAckExt(dskReadAckExt) ); +wire [1:0] diskEject; +wire [1:0] diskMotor, diskAct; + dataController_top dc0 ( - .clk(clk_sys), - .cep(cep), - .cen(cen), - + .clk32(clk_sys), + .clk8_en_p(clk8_en_p), + .clk8_en_n(clk8_en_n), + .E_rising(E_rising), + .E_falling(E_falling), ._systemReset(n_reset), ._cpuReset(_cpuReset), ._cpuIPL(_cpuIPL), ._cpuUDS(_cpuUDS), ._cpuLDS(_cpuLDS), ._cpuRW(_cpuRW), + ._cpuVMA(_cpuVMA), .cpuDataIn(cpuDataOut), .cpuDataOut(dataControllerDataOut), .cpuAddrRegHi(cpuAddr[12:9]), @@ -499,25 +614,31 @@ dataController_top dc0 .selectIWM(selectIWM), .selectVIA(selectVIA), .cpuBusControl(cpuBusControl), + .videoBusControl(videoBusControl), .memoryDataOut(memoryDataOut), .memoryDataIn(sdram_do), + .memoryLatch(memoryLatch), // peripherals - .ps2_key(ps2_key), + .ps2_key(ps2_key), .capslock(capslock), .ps2_mouse(ps2_mouse), - .serialIn(0), + .serialIn(serialIn), + .timestamp(TIMESTAMP), // video ._hblank(_hblank), - ._vblank(_vblank), + ._vblank(_vblank), + .pixelOut(pixelOut), + .loadPixels(loadPixels), + .vid_alt(vid_alt), .memoryOverlayOn(memoryOverlayOn), .audioOut(audio), .snd_alt(snd_alt), .loadSound(loadSound), - + // floppy disk interface .insertDisk({dsk_ext_ins, dsk_int_ins}), .diskSides({dsk_ext_ds, dsk_int_ds}), @@ -526,11 +647,12 @@ dataController_top dc0 .dskReadAckInt(dskReadAckInt), .dskReadAddrExt(dskReadAddrExt), .dskReadAckExt(dskReadAckExt), - .diskMotor(diskMotor), .diskAct(diskAct), - + // block device interface for scsi disk + .img_mounted(img_mounted), + .img_size(img_size), .io_lba(sd_lba), .io_rd(sd_rd), .io_wr(sd_wr), @@ -553,17 +675,15 @@ always @(posedge clk_sys) begin disk_act <= 0; end - if(|diskAct) timeout <= 1000000; + if(|diskAct) timeout <= 500000; end //////////////////////// DOWNLOADING /////////////////////////// // include ROM download helper -wire dio_download; -reg dio_write; +wire dio_download; wire [23:0] dio_addr = ioctl_addr[24:1]; wire [7:0] dio_index; -reg [15:0] dio_data; // good floppy image sizes are 819200 bytes and 409600 bytes reg dsk_int_ds, dsk_ext_ds; // double sided image inserted @@ -588,7 +708,7 @@ always @(posedge clk_sys) begin dsk_int_ds <= 0; dsk_int_ss <= 0; end -end +end always @(posedge clk_sys) begin reg old_down; @@ -606,33 +726,42 @@ always @(posedge clk_sys) begin end // disk images are being stored right after os rom at word offset 0x80000 and 0x100000 -wire [20:0] dio_a = - (dio_index == 0)?dio_addr[20:0]: // os rom - (dio_index == 1)?{21'h80000 + dio_addr[20:0]}: // first dsk image at 512k word addr - {21'h100000 + dio_addr[20:0]}; // second dsk image at 1M word addr +reg [20:0] dio_a; +reg [15:0] dio_data; +reg dio_write; always @(posedge clk_sys) begin + reg [7:0] temp; reg old_cyc = 0; + if(ioctl_write) begin + if(~ioctl_addr[0]) temp <= ioctl_data; + else begin + dio_data <= {temp, ioctl_data}; + dio_a <= {dio_index[1:0], dio_addr[18:0]}; + ioctl_wait <= 1; + end + end + old_cyc <= dioBusControl; - if(ioctl_wr) ioctl_wait <= 1; - if(~dioBusControl) dio_write <= ioctl_wait; if(old_cyc & ~dioBusControl & dio_write) ioctl_wait <= 0; end + // sdram used for ram/rom maps directly into 68k address space wire download_cycle = dio_download && dioBusControl; ////////////////////////// SDRAM ///////////////////////////////// wire [24:0] sdram_addr = download_cycle ? { 4'b0001, dio_a[20:0] } : { 3'b000, ~_romOE, memoryAddr[21:1] }; -wire [15:0] sdram_din = download_cycle ? dio_data : memoryDataOut; -wire [1:0] sdram_ds = download_cycle ? 2'b11 : { !_memoryUDS, !_memoryLDS }; -wire sdram_we = download_cycle ? dio_write : !_ramWE; -wire sdram_oe = download_cycle ? 1'b0 : (!_ramOE || !_romOE); +wire [15:0] sdram_din = download_cycle ? dio_data : memoryDataOut; +wire [1:0] sdram_ds = download_cycle ? 2'b11 : { !_memoryUDS, !_memoryLDS }; +wire sdram_we = download_cycle ? dio_write : !_ramWE; +wire sdram_oe = download_cycle ? 1'b0 : (!_ramOE || !_romOE); wire [15:0] sdram_do = download_cycle ? 16'hffff : (dskReadAckInt || dskReadAckExt) ? extra_rom_data_demux : sdram_out; +// during rom/disk download ffff is returned so the screen is black during download // "extra rom" is used to hold the disk image. It's expected to be byte wide and // we thus need to properly demultiplex the word returned from sdram in that case wire [15:0] extra_rom_data_demux = memoryAddr[0]? {sdram_out[7:0],sdram_out[7:0]}:{sdram_out[15:8],sdram_out[15:8]}; @@ -643,51 +772,28 @@ assign SDRAM_CKE = 1; sdram sdram ( // system interface - .init ( !pll_locked ), - .clk ( clk_sys ), - .sync ( cep ), + .init ( !pll_locked ), + .clk_64 ( clk_mem ), + .clk_8 ( clk8 ), - .sd_clk ( SDRAM_CLK ), - .sd_data ( SDRAM_DQ ), - .sd_addr ( SDRAM_A ), - .sd_dqm ( {SDRAM_DQMH, SDRAM_DQML} ), - .sd_cs ( SDRAM_nCS ), - .sd_ba ( SDRAM_BA ), - .sd_we ( SDRAM_nWE ), - .sd_ras ( SDRAM_nRAS ), - .sd_cas ( SDRAM_nCAS ), + .sd_clk ( SDRAM_CLK ), + .sd_data ( SDRAM_DQ ), + .sd_addr ( SDRAM_A ), + .sd_dqm ( {SDRAM_DQMH, SDRAM_DQML} ), + .sd_cs ( SDRAM_nCS ), + .sd_ba ( SDRAM_BA ), + .sd_we ( SDRAM_nWE ), + .sd_ras ( SDRAM_nRAS ), + .sd_cas ( SDRAM_nCAS ), // cpu/chipset interface // map rom to sdram word address $200000 - $20ffff - .din ( sdram_din ), - .addr ( sdram_addr ), - .ds ( sdram_ds ), - .we ( sdram_we ), - .oe ( sdram_oe ), - .dout ( sdram_out ) + .din ( sdram_din ), + .addr ( sdram_addr ), + .ds ( sdram_ds ), + .we ( sdram_we ), + .oe ( sdram_oe ), + .dout ( sdram_out ) ); - -//////////////////////// TURBO HANDLING ////////////////////////// - -// cannot boot from SCSI if turbo enabled -// delay the turbo. -reg real_turbo = 0; -always @(posedge clk_sys) begin - reg old_ack; - integer ack_cnt = 0; - - old_ack <= sd_ack; - if(old_ack && ~sd_ack && ack_cnt) ack_cnt <= ack_cnt - 1'd1; - - //Cancel delay if FDD is accesed. - if(diskMotor) ack_cnt <= 0; - if(!ack_cnt && dioBusControl) real_turbo <= status_turbo; - - if(~n_reset) begin - real_turbo <= 0; - ack_cnt <= 20; - end -end - endmodule diff --git a/files.qip b/files.qip index 0467d09..c76b310 100644 --- a/files.qip +++ b/files.qip @@ -1,5 +1,6 @@ set_global_assignment -name QIP_FILE rtl/tg68k/TG68K.qip -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv +set_global_assignment -name QIP_FILE rtl/fx68k/fx68k.qip +set_global_assignment -name VERILOG_FILE rtl/sdram.v set_global_assignment -name VERILOG_FILE rtl/scsi.v set_global_assignment -name VERILOG_FILE rtl/ncr5380.v set_global_assignment -name VERILOG_FILE rtl/floppy_track_encoder.v @@ -8,10 +9,11 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/ps2_kbd.sv set_global_assignment -name VERILOG_FILE rtl/ps2_mouse.v set_global_assignment -name VERILOG_FILE rtl/scc.v set_global_assignment -name VERILOG_FILE rtl/iwm.v -set_global_assignment -name VERILOG_FILE rtl/via.v +set_global_assignment -name VHDL_FILE rtl/via6522.vhd set_global_assignment -name VERILOG_FILE rtl/addrDecoder.v set_global_assignment -name VERILOG_FILE rtl/addrController_top.v set_global_assignment -name VERILOG_FILE rtl/dataController_top.v -set_global_assignment -name VERILOG_FILE rtl/video.v -set_global_assignment -name SDC_FILE MacPlus.sdc +set_global_assignment -name VERILOG_FILE rtl/videoTimer.v +set_global_assignment -name VERILOG_FILE rtl/videoShifter.v +set_global_assignment -name VERILOG_FILE rtl/rtc.v set_global_assignment -name SYSTEMVERILOG_FILE MacPlus.sv diff --git a/rtl/addrController_top.v b/rtl/addrController_top.v index cccb40f..5c07978 100644 --- a/rtl/addrController_top.v +++ b/rtl/addrController_top.v @@ -1,9 +1,11 @@ -module addrController_top -( +module addrController_top( // clocks: input clk, - input cep, // 8.125 MHz CPU clock - input cen, // 8.125 MHz CPU clock + output clk8, // 8.125 MHz CPU clock + output clk8_en_p, + output clk8_en_n, + output clk16_en_p, + output clk16_en_n, // system config: input turbo, // 0 = normal, 1 = faster @@ -15,7 +17,8 @@ module addrController_top input _cpuUDS, input _cpuLDS, input _cpuRW, - + input _cpuAS, + // RAM/ROM: output [21:0] memoryAddr, output _memoryUDS, @@ -23,25 +26,33 @@ module addrController_top output _romOE, output _ramOE, output _ramWE, + output videoBusControl, output dioBusControl, output cpuBusControl, - + output memoryLatch, + // peripherals: output selectSCSI, output selectSCC, output selectIWM, output selectVIA, - + output selectRAM, + output selectROM, + // video: - input _vblank, - input _hblank, - + output hsync, + output vsync, + output _hblank, + output _vblank, + output loadPixels, + input vid_alt, + input snd_alt, output loadSound, - + // misc input memoryOverlayOn, - + // interface to read dsk image from ram input [21:0] dskReadAddrInt, output dskReadAckInt, @@ -49,103 +60,155 @@ module addrController_top output dskReadAckExt ); -// -------------- audio engine (may be moved into seperate module) --------------- -assign loadSound = audioReq & sndReadAck; + // -------------- audio engine (may be moved into seperate module) --------------- + assign loadSound = sndReadAck; -reg [21:0] audioAddr; -reg audioReq; -always @(posedge clk) begin - reg vblankD; - reg hblankD; - reg swap; + localparam SIZE = 20'd135408; // 168*806 clk8 events per frame + localparam STEP = 20'd5920; // one step every 16*370 clk8 events + + reg [21:0] audioAddr; + reg [19:0] snd_div; + reg sndReadAckD; - - sndReadAckD <= sndReadAck; - if(sndReadAckD & ~sndReadAck) begin // prepare for next audio cycle - vblankD <= _vblank; - hblankD <= _hblank; - audioReq <= 0; - - // falling adge of _vblank = begin of vblank phase - if(vblankD && !_vblank) swap <= 1; - - if(hblankD && !_hblank) begin - if(swap) audioAddr <= snd_alt ? 22'h3FA100 : 22'h3FFD00; - else audioAddr <= audioAddr + 22'd2; - swap <= 0; - audioReq <= 1; + always @(posedge clk) + if (clk8_en_n) sndReadAckD <= sndReadAck; + + reg vblankD, vblankD2; + always @(posedge clk) begin + if(clk8_en_p && sndReadAckD) begin + vblankD <= _vblank; + vblankD2 <= vblankD; + + // falling adge of _vblank = begin of vblank phase + if(vblankD2 && !vblankD) begin + audioAddr <= snd_alt?22'h3FA100:22'h3FFD00; + snd_div <= 20'd0; + end else begin + if(snd_div >= SIZE-1) begin + snd_div <= snd_div - SIZE + STEP; + audioAddr <= audioAddr + 22'd2; + end else + snd_div <= snd_div + STEP; + end end end -end -// interleaved RAM access for CPU and periphery -reg [3:0] cycle; -wire [1:0] busCycle = cycle[1:0]; -wire [1:0] subCycle = cycle[3:2]; -always @(posedge clk) if(cep) cycle <= cycle + 2'd1; + assign dioBusControl = extraBusControl; -assign cpuBusControl = turbo ? busCycle[0] : (busCycle == 1); -assign dioBusControl = (busCycle == 2); + // interleaved RAM access for CPU and video + reg [1:0] busCycle; + reg [1:0] busPhase; + reg [1:0] extra_slot_count; -assign dskReadAckInt = dioBusControl && (subCycle == 0); -assign dskReadAckExt = dioBusControl && (subCycle == 1); -wire sndReadAck = (busCycle == 0); + always @(posedge clk) begin + busPhase <= busPhase + 1'd1; + if (busPhase == 2'b11) + busCycle <= busCycle + 2'd1; + end + assign memoryLatch = busPhase == 2'd3; + assign clk8 = !busPhase[1]; + assign clk8_en_p = busPhase == 2'b11; + assign clk8_en_n = busPhase == 2'b01; + assign clk16_en_p = !busPhase[0]; + assign clk16_en_n = busPhase[0]; + reg extra_slot_advance; + always @(posedge clk) + if (clk8_en_n) extra_slot_advance <= (busCycle == 2'b11); -// interconnects -wire selectRAM, selectROM; + // allocate memory slots in the extra cycle + always @(posedge clk) begin + if(clk8_en_p && extra_slot_advance) begin + extra_slot_count <= extra_slot_count + 2'd1; + end + end -// RAM/ROM control signals -wire extraRomRead = dskReadAckInt || dskReadAckExt; -assign _romOE = ~(extraRomRead || (cpuBusControl && selectROM && _cpuRW)); + // video controls memory bus during the first clock of the four-clock cycle + assign videoBusControl = (busCycle == 2'b00); + // cpu controls memory bus during the second and fourth clock of the four-clock cycle + assign cpuBusControl = (busCycle == 2'b01) || (busCycle == 2'b11); + // IWM/audio gets 3rd cycle + wire extraBusControl = (busCycle == 2'b10); -assign _ramOE = ~(loadSound || (cpuBusControl && selectRAM && _cpuRW)); -assign _ramWE = ~(cpuBusControl && selectRAM && !_cpuRW); + // interconnects + wire [21:0] videoAddr; + + // RAM/ROM control signals + wire videoControlActive = _hblank; -assign _memoryUDS = cpuBusControl ? _cpuUDS : 1'b0; -assign _memoryLDS = cpuBusControl ? _cpuLDS : 1'b0; -wire [21:0] addrMux = loadSound ? audioAddr : cpuAddr[21:0]; -wire [21:0] macAddr; -assign macAddr[15:0] = addrMux[15:0]; + wire extraRomRead = dskReadAckInt || dskReadAckExt; + assign _romOE = ~(extraRomRead || (cpuBusControl && selectROM && _cpuRW)); + + wire extraRamRead = sndReadAck; + assign _ramOE = ~((videoBusControl && videoControlActive) || (extraRamRead) || + (cpuBusControl && selectRAM && _cpuRW)); + assign _ramWE = ~(cpuBusControl && selectRAM && !_cpuRW); + + assign _memoryUDS = cpuBusControl ? _cpuUDS : 1'b0; + assign _memoryLDS = cpuBusControl ? _cpuLDS : 1'b0; + wire [21:0] addrMux = sndReadAck ? audioAddr : videoBusControl ? videoAddr : cpuAddr[21:0]; + wire [21:0] macAddr; + assign macAddr[15:0] = addrMux[15:0]; -// video and sound always addresses ram -wire ram_access = (cpuBusControl && selectRAM) || loadSound; -wire rom_access = (cpuBusControl && selectROM); + // video and sound always addresses ram + wire ram_access = (cpuBusControl && selectRAM) || videoBusControl || sndReadAck; + wire rom_access = (cpuBusControl && selectROM); + + // simulate smaller RAM/ROM sizes + assign macAddr[16] = rom_access && configROMSize == 1'b0 ? 1'b0 : // force A16 to 0 for 64K ROM access + addrMux[16]; + assign macAddr[17] = ram_access && configRAMSize == 2'b00 ? 1'b0 : // force A17 to 0 for 128K RAM access + rom_access && configROMSize == 1'b1 ? 1'b0 : // force A17 to 0 for 128K ROM access + rom_access && configROMSize == 1'b0 ? 1'b1 : // force A17 to 1 for 64K ROM access (64K ROM image is at $20000) + addrMux[17]; + assign macAddr[18] = ram_access && configRAMSize == 2'b00 ? 1'b0 : // force A18 to 0 for 128K RAM access + rom_access ? 1'b0 : // force A18 to 0 for ROM access + addrMux[18]; + assign macAddr[19] = ram_access && configRAMSize[1] == 1'b0 ? 1'b0 : // force A19 to 0 for 128K or 512K RAM access + rom_access ? 1'b0 : // force A19 to 0 for ROM access + addrMux[19]; + assign macAddr[20] = ram_access && configRAMSize != 2'b11 ? 1'b0 : // force A20 to 0 for all but 4MB RAM access + rom_access ? 1'b0 : // force A20 to 0 for ROM access + addrMux[20]; + assign macAddr[21] = ram_access && configRAMSize != 2'b11 ? 1'b0 : // force A21 to 0 for all but 4MB RAM access + rom_access ? 1'b0 : // force A21 to 0 for ROM access + addrMux[21]; + + + // floppy emulation gets extra slots 0 and 1 + assign dskReadAckInt = (extraBusControl == 1'b1) && (extra_slot_count == 0); + assign dskReadAckExt = (extraBusControl == 1'b1) && (extra_slot_count == 1); + // audio gets extra slot 2 + wire sndReadAck = (extraBusControl == 1'b1) && (extra_slot_count == 2); -// simulate smaller RAM/ROM sizes -assign macAddr[16] = rom_access && configROMSize == 1'b0 ? 1'b0 : // force A16 to 0 for 64K ROM access - addrMux[16]; -assign macAddr[17] = ram_access && configRAMSize == 2'b00 ? 1'b0 : // force A17 to 0 for 128K RAM access - rom_access && configROMSize == 1'b1 ? 1'b0 : // force A17 to 0 for 128K ROM access - rom_access && configROMSize == 1'b0 ? 1'b1 : // force A17 to 1 for 64K ROM access (64K ROM image is at $20000) - addrMux[17]; -assign macAddr[18] = ram_access && configRAMSize == 2'b00 ? 1'b0 : // force A18 to 0 for 128K RAM access - rom_access ? 1'b0 : // force A18 to 0 for ROM access - addrMux[18]; -assign macAddr[19] = ram_access && configRAMSize[1] == 1'b0 ? 1'b0 : // force A19 to 0 for 128K or 512K RAM access - rom_access ? 1'b0 : // force A19 to 0 for ROM access - addrMux[19]; -assign macAddr[20] = ram_access && configRAMSize != 2'b11 ? 1'b0 : // force A20 to 0 for all but 4MB RAM access - rom_access ? 1'b0 : // force A20 to 0 for ROM access - addrMux[20]; -assign macAddr[21] = ram_access && configRAMSize != 2'b11 ? 1'b0 : // force A21 to 0 for all but 4MB RAM access - rom_access ? 1'b0 : // force A21 to 0 for ROM access - addrMux[21]; + assign memoryAddr = + dskReadAckInt ? dskReadAddrInt + 22'h100000: // first dsk image at 1MB + dskReadAckExt ? dskReadAddrExt + 22'h200000: // second dsk image at 2MB + macAddr; -assign memoryAddr = - dskReadAckInt ? dskReadAddrInt + 22'h100000: // first dsk image at 1MB - dskReadAckExt ? dskReadAddrExt + 22'h200000: // second dsk image at 2MB - macAddr; - -// address decoding -addrDecoder ad( - .address(cpuAddr), - .memoryOverlayOn(memoryOverlayOn), - .selectRAM(selectRAM), - .selectROM(selectROM), - .selectSCSI(selectSCSI), - .selectSCC(selectSCC), - .selectIWM(selectIWM), - .selectVIA(selectVIA)); + // address decoding + addrDecoder ad( + .address(cpuAddr), + ._cpuAS(_cpuAS), + .memoryOverlayOn(memoryOverlayOn), + .selectRAM(selectRAM), + .selectROM(selectROM), + .selectSCSI(selectSCSI), + .selectSCC(selectSCC), + .selectIWM(selectIWM), + .selectVIA(selectVIA)); + // video + videoTimer vt( + .clk(clk), + .clk_en(clk8_en_p), + .busCycle(busCycle), + .vid_alt(vid_alt), + .videoAddr(videoAddr), + .hsync(hsync), + .vsync(vsync), + ._hblank(_hblank), + ._vblank(_vblank), + .loadPixels(loadPixels)); + endmodule diff --git a/rtl/addrDecoder.v b/rtl/addrDecoder.v index 41d6083..ef2ffc1 100644 --- a/rtl/addrDecoder.v +++ b/rtl/addrDecoder.v @@ -81,6 +81,7 @@ module addrDecoder( input [23:0] address, + input _cpuAS, input memoryOverlayOn, output reg selectRAM, output reg selectROM, @@ -101,30 +102,30 @@ module addrDecoder( casez (address[23:20]) 4'b00??: begin if (memoryOverlayOn == 0) - selectRAM = 1'b1; + selectRAM = !_cpuAS; else begin if (address[23:20] == 0) begin // Mac Plus: repeated images of overlay ROM only extend to $0F0000 // Mac 512K: more repeated ROM images at $020000-$02FFFF - selectROM = 1'b1; + selectROM = !_cpuAS; end end end 4'b0100: if( address[17] == 1'b0) // <- this detects SCSI!!! - selectROM = 1'b1; + selectROM = !_cpuAS; 4'b0101: if (address[19:12] == 8'h80) - selectSCSI = 1'b1; + selectSCSI = !_cpuAS; 4'b0110: if (memoryOverlayOn) - selectRAM = 1'b1; + selectRAM = !_cpuAS; 4'b10?1: - selectSCC = 1'b1; + selectSCC = !_cpuAS; 4'b1101: - selectIWM = 1'b1; + selectIWM = !_cpuAS; 4'b1110: - selectVIA = 1'b1; + selectVIA = !_cpuAS; default: ; // select nothing endcase diff --git a/rtl/dataController_top.v b/rtl/dataController_top.v index 4523a6a..476b490 100644 --- a/rtl/dataController_top.v +++ b/rtl/dataController_top.v @@ -1,9 +1,11 @@ module dataController_top( // clocks: - input clk, - input cep, - input cen, - + input clk32, // 32.5 MHz pixel clock + input clk8_en_p, + input clk8_en_n, + input E_rising, + input E_falling, + // system control: input _systemReset, @@ -19,45 +21,53 @@ module dataController_top( input _cpuUDS, input _cpuLDS, input _cpuRW, - output reg [15:0] cpuDataOut, - + output [15:0] cpuDataOut, + // peripherals: input selectSCSI, input selectSCC, input selectIWM, input selectVIA, - + input _cpuVMA, + // RAM/ROM: + input videoBusControl, input cpuBusControl, input [15:0] memoryDataIn, output [15:0] memoryDataOut, - + input memoryLatch, + // keyboard: input [10:0] ps2_key, - output capslock, - + output capslock, + // mouse: input [24:0] ps2_mouse, - + // serial: input serialIn, output serialOut, + // RTC + input [32:0] timestamp, + // video: + output pixelOut, input _hblank, input _vblank, + input loadPixels, + output vid_alt, // audio output [10:0] audioOut, // 8 bit audio + 3 bit volume output snd_alt, input loadSound, - + // misc output memoryOverlayOn, input [1:0] insertDisk, input [1:0] diskSides, output [1:0] diskEject, - output [1:0] diskMotor, output [1:0] diskAct, @@ -67,233 +77,376 @@ module dataController_top( input dskReadAckExt, // connections to io controller + input [1:0] img_mounted, + input [31:0] img_size, output [31:0] io_lba, - output io_rd, - output io_wr, - input io_ack, - + output [1:0] io_rd, + output [1:0] io_wr, + input io_ack, input [8:0] sd_buff_addr, input [7:0] sd_buff_dout, output [7:0] sd_buff_din, input sd_buff_wr ); + + // add binary volume levels according to volume setting + assign audioOut = + (snd_vol[0]?audio_x1:11'd0) + + (snd_vol[1]?audio_x2:11'd0) + + (snd_vol[2]?audio_x4:11'd0); -// add binary volume levels according to volume setting -assign audioOut = - (snd_vol[0] ? audio_latch : 11'd0) + - (snd_vol[1] ? audio_latch<<1 : 11'd0) + - (snd_vol[2] ? audio_latch<<2 : 11'd0); - -reg [10:0] audio_latch; -always @(posedge clk) begin + // three binary volume levels *1, *2 and *4, sign expanded + wire [10:0] audio_x1 = { {3{audio_latch[7]}}, audio_latch }; + wire [10:0] audio_x2 = { {2{audio_latch[7]}}, audio_latch, 1'b0 }; + wire [10:0] audio_x4 = { audio_latch[7] , audio_latch, 2'b00}; + reg loadSoundD; - if(cen) loadSoundD <= loadSound; - if(cep && loadSoundD) begin - if(snd_ena) audio_latch <= 0; - else audio_latch <= memoryDataIn[15:8]; + always @(posedge clk32) + if (clk8_en_n) loadSoundD <= loadSound; + + // read audio data and convert to signed for further volume adjustment + reg [7:0] audio_latch; + always @(posedge clk32) begin + if(clk8_en_p && loadSoundD) begin + if(snd_ena) audio_latch <= 8'h00; + else audio_latch <= memoryDataIn[15:8] - 8'd128; + end end -end + + // CPU reset generation + // For initial CPU reset, RESET and HALT must be asserted for at least 100ms = 800,000 clocks of clk8 + reg [19:0] resetDelay; // 20 bits = 1 million + wire isResetting = resetDelay != 0; -// CPU reset generation -// For initial CPU reset, RESET and HALT must be asserted for at least 100ms = 800,000 clocks of clk8 -reg [19:0] resetDelay; // 20 bits = 1 million -wire isResetting = resetDelay != 0; - -initial begin - // force a reset when the FPGA configuration is completed - resetDelay <= 20'hFFFFF; -end - -always @(posedge clk or negedge _systemReset) begin - if (_systemReset == 1'b0) begin + initial begin + // force a reset when the FPGA configuration is completed resetDelay <= 20'hFFFFF; end - else if(cep && isResetting) begin - resetDelay <= resetDelay - 1'b1; + + always @(posedge clk32 or negedge _systemReset) begin + if (_systemReset == 1'b0) begin + resetDelay <= 20'hFFFFF; + end + else if (clk8_en_p && isResetting) begin + resetDelay <= resetDelay - 1'b1; + end end -end -assign _cpuReset = isResetting ? 1'b0 : 1'b1; + assign _cpuReset = isResetting ? 1'b0 : 1'b1; + + // interconnects + wire SEL; + wire _viaIrq, _sccIrq, sccWReq; + wire [15:0] viaDataOut; + wire [15:0] iwmDataOut; + wire [7:0] sccDataOut; + wire [7:0] scsiDataOut; + wire mouseX1, mouseX2, mouseY1, mouseY2, mouseButton; + + // interrupt control + assign _cpuIPL = + !_viaIrq?3'b110: + !_sccIrq?3'b101: + 3'b111; + + // Serial port + assign serialOut = 0; -// interconnects -wire SEL; -wire _viaIrq, _sccIrq, sccWReq; -wire [15:0] viaDataOut; -wire [15:0] iwmDataOut; -wire [7:0] sccDataOut; -wire [7:0] scsiDataOut; -wire mouseX1, mouseX2, mouseY1, mouseY2, mouseButton; + reg [15:0] cpu_data; + always @(posedge clk32) if (cpuBusControl && memoryLatch) cpu_data <= memoryDataIn; -// interrupt control -assign _cpuIPL = - !_viaIrq?3'b110: - !_sccIrq?3'b101: - 3'b111; + // CPU-side data output mux + assign cpuDataOut = selectIWM ? iwmDataOut : + selectVIA ? viaDataOut : + selectSCC ? { sccDataOut, 8'hEF } : + selectSCSI ? { scsiDataOut, 8'hEF } : + (cpuBusControl && memoryLatch) ? memoryDataIn : cpu_data; + + // Memory-side + assign memoryDataOut = cpuDataIn; -// Serial port -assign serialOut = 0; + // SCSI + ncr5380 scsi( + .clk(clk32), + .ce(clk8_en_p), + .reset(!_cpuReset), + .bus_cs(selectSCSI), + .bus_we(!_cpuRW), + .bus_rs(cpuAddrRegMid), + .dack(cpuAddrRegHi[0]), // A9 + .wdata(cpuDataIn[15:8]), + .rdata(scsiDataOut), -// CPU-side data output mux -always @(*) begin - casex({selectIWM, selectVIA, selectSCC, selectSCSI}) - 'b1xxx: cpuDataOut = iwmDataOut; - 'b01xx: cpuDataOut = viaDataOut; - 'b001x: cpuDataOut = { sccDataOut, 8'hEF }; - 'b0001: cpuDataOut = { scsiDataOut, 8'hEF }; - 'b0000: cpuDataOut = memoryDataIn; - endcase -end + // connections to io controller + .img_mounted( img_mounted ), + .img_size( img_size ), + .io_lba ( io_lba ), + .io_rd ( io_rd ), + .io_wr ( io_wr ), + .io_ack ( io_ack ), -// Memory-side -assign memoryDataOut = cpuDataIn; + .sd_buff_addr(sd_buff_addr), + .sd_buff_dout(sd_buff_dout), + .sd_buff_din(sd_buff_din), + .sd_buff_wr(sd_buff_wr) + ); -// SCSI -ncr5380 scsi -( - .clk(clk), - .ce(cep), + // count vblanks, and set 1 second interrupt after 60 vblanks + reg [5:0] vblankCount; + reg _lastVblank; + always @(posedge clk32) begin + if (clk8_en_n) begin + _lastVblank <= _vblank; + if (_vblank == 1'b0 && _lastVblank == 1'b1) begin + if (vblankCount != 59) begin + vblankCount <= vblankCount + 1'b1; + end + else begin + vblankCount <= 6'h0; + end + end + end + end + wire onesec = vblankCount == 59; - .reset(!_cpuReset), - .bus_cs(selectSCSI && cpuBusControl), - .bus_we(!_cpuRW), - .bus_rs(cpuAddrRegMid), - .dack(cpuAddrRegHi[0]), // A9 - .wdata(cpuDataIn[15:8]), - .rdata(scsiDataOut), + // VIA + wire [2:0] snd_vol; + wire snd_ena; - // connections to io controller - .io_lba ( io_lba ), - .io_rd ( io_rd ), - .io_wr ( io_wr ), - .io_ack ( io_ack ), + wire [7:0] via_pa_i, via_pa_o, via_pa_oe; + wire [7:0] via_pb_i, via_pb_o, via_pb_oe; + wire viaIrq; - .sd_buff_addr(sd_buff_addr), - .sd_buff_dout(sd_buff_dout), - .sd_buff_din(sd_buff_din), - .sd_buff_wr(sd_buff_wr) -); + assign _viaIrq = ~viaIrq; + //port A + assign via_pa_i = {sccWReq, ~via_pa_oe[6:0] | via_pa_o[6:0]}; + assign snd_vol = ~via_pa_oe[2:0] | via_pa_o[2:0]; + assign snd_alt = ~(~via_pa_oe[3] | via_pa_o[3]); + assign memoryOverlayOn = ~via_pa_oe[4] | via_pa_o[4]; + assign SEL = ~via_pa_oe[5] | via_pa_o[5]; + assign vid_alt = ~via_pa_oe[6] | via_pa_o[6]; -// VIA -wire [2:0] snd_vol; -wire snd_ena; + //port B + assign via_pb_i = {1'b1, _hblank, mouseY2, mouseX2, mouseButton, 2'b11, rtcdat_o}; + assign snd_ena = ~via_pb_oe[7] | via_pb_o[7]; -via v -( - .clk(clk), - .cep(cep), - .cen(cen), + assign viaDataOut[7:0] = 8'hEF; - ._reset(_cpuReset), - .selectVIA(selectVIA && cpuBusControl), - ._cpuRW(_cpuRW), - ._cpuUDS(_cpuUDS), - .dataIn(cpuDataIn), - .cpuAddrRegHi(cpuAddrRegHi), - ._hblank(_hblank), - ._vblank(_vblank), - .mouseY2(mouseY2), - .mouseX2(mouseX2), - .mouseButton(mouseButton), - .sccWReq(sccWReq), - ._irq(_viaIrq), - .dataOut(viaDataOut), - .memoryOverlayOn(memoryOverlayOn), - .SEL(SEL), + via6522 via( + .clock (clk32), + .rising (E_rising), + .falling (E_falling), + .reset (!_cpuReset), - .snd_vol(snd_vol), - .snd_ena(snd_ena), - .snd_alt(snd_alt), + .addr (cpuAddrRegHi), + .wen (selectVIA && !_cpuVMA && !_cpuRW), + .ren (selectVIA && !_cpuVMA && _cpuRW), + .data_in (cpuDataIn[15:8]), + .data_out (viaDataOut[15:8]), - .kbd_in_data(kbd_in_data), - .kbd_in_strobe(kbd_in_strobe), - .kbd_out_data(kbd_out_data), - .kbd_out_strobe(kbd_out_strobe) -); + .phi2_ref (), -// IWM -iwm i -( - .clk(clk), - .cep(cep), - .cen(cen), + //-- pio -- + .port_a_o (via_pa_o), + .port_a_t (via_pa_oe), + .port_a_i (via_pa_i), - ._reset(_cpuReset), - .selectIWM(selectIWM && cpuBusControl), - ._cpuRW(_cpuRW), - ._cpuLDS(_cpuLDS), - .dataIn(cpuDataIn), - .cpuAddrRegHi(cpuAddrRegHi), - .SEL(SEL), - .dataOut(iwmDataOut), - .insertDisk(insertDisk), - .diskSides(diskSides), - .diskEject(diskEject), - .diskMotor(diskMotor), - .diskAct(diskAct), + .port_b_o (via_pb_o), + .port_b_t (via_pb_oe), + .port_b_i (via_pb_i), - .dskReadAddrInt(dskReadAddrInt), - .dskReadAckInt(dskReadAckInt), - .dskReadAddrExt(dskReadAddrExt), - .dskReadAckExt(dskReadAckExt), - .dskReadData(memoryDataIn[7:0]) -); + //-- handshake pins + .ca1_i (_vblank), + .ca2_i (onesec), -// SCC -scc s -( - .clk(clk), - .cep(cep), - .cen(cen), + .cb1_i (kbdclk), + .cb2_i (cb2_i), + .cb2_o (cb2_o), + .cb2_t (cb2_t), - .reset_hw(~_cpuReset), - .cs(selectSCC && (_cpuLDS == 1'b0 || _cpuUDS == 1'b0) && cpuBusControl), - .we(!_cpuRW), - .rs(cpuAddrRegLo), - .wdata(cpuDataIn[15:8]), - .rdata(sccDataOut), - ._irq(_sccIrq), - .dcd_a(mouseX1), - .dcd_b(mouseY1), - .wreq(sccWReq) -); + .irq (viaIrq) + ); -// Mouse -ps2_mouse mouse -( - .reset(~_cpuReset), + wire _rtccs = ~via_pb_oe[2] | via_pb_o[2]; + wire rtcck = ~via_pb_oe[1] | via_pb_o[1]; + wire rtcdat_i = ~via_pb_oe[0] | via_pb_o[0]; + wire rtcdat_o; - .clk(clk), - .ce(cep), + rtc pram ( + .clk (clk32), + .reset (!_cpuReset), + .timestamp (timestamp), + ._cs (_rtccs), + .ck (rtcck), + .dat_i (rtcdat_i), + .dat_o (rtcdat_o) + ); - .ps2_mouse(ps2_mouse), + reg kbdclk; + reg [10:0] kbdclk_count; + reg kbd_transmitting, kbd_wait_receiving, kbd_receiving; + reg [2:0] kbd_bitcnt; - .x1(mouseX1), - .y1(mouseY1), - .x2(mouseX2), - .y2(mouseY2), - .button(mouseButton) -); + wire cb2_i = kbddata_o; + wire cb2_o, cb2_t; + wire kbddat_i = ~cb2_t | cb2_o; + reg kbddata_o; + reg [7:0] kbd_to_mac; + reg kbd_data_valid; -wire [7:0] kbd_in_data; -wire kbd_in_strobe; -wire [7:0] kbd_out_data; -wire kbd_out_strobe; + // Keyboard transmitter-receiver + always @(posedge clk32) begin + if (clk8_en_p) begin + if ((kbd_transmitting && !kbd_wait_receiving) || kbd_receiving) begin + kbdclk_count <= kbdclk_count + 1'd1; + if (kbdclk_count == 12'd1300) begin // ~165usec + kbdclk <= ~kbdclk; + kbdclk_count <= 0; + if (kbdclk) begin + // shift before the falling edge + if (kbd_transmitting) kbd_out_data <= { kbd_out_data[6:0], kbddat_i }; + if (kbd_receiving) kbddata_o <= kbd_to_mac[7-kbd_bitcnt]; + end + end + end else begin + kbdclk_count <= 0; + kbdclk <= 1; + end + end + end -// Keyboard -ps2_kbd kbd -( - .reset(~_cpuReset), + // Keyboard control + always @(posedge clk32) begin + reg kbdclk_d; + if (!_cpuReset) begin + kbd_bitcnt <= 0; + kbd_transmitting <= 0; + kbd_wait_receiving <= 0; + kbd_data_valid <= 0; + end else if (clk8_en_p) begin + if (kbd_in_strobe) begin + kbd_to_mac <= kbd_in_data; + kbd_data_valid <= 1; + end - .clk(clk), - .ce(cep), + kbd_out_strobe <= 0; + kbdclk_d <= kbdclk; - .ps2_key(ps2_key), - .capslock(capslock), + // Only the Macintosh can initiate communication over the keyboard lines. On + // power-up of either the Macintosh or the keyboard, the Macintosh is in + // charge, and the external device is passive. The Macintosh signals that it's + // ready to begin communication by pulling the keyboard data line low. + if (!kbd_transmitting && !kbd_receiving && !kbddat_i) begin + kbd_transmitting <= 1; + kbd_bitcnt <= 0; + end + // The last bit of the command leaves the keyboard data line low; the + // Macintosh then indicates it's ready to receive the keyboard's response by + // setting the data line high. + if (kbd_wait_receiving && kbddat_i && kbd_data_valid) begin + kbd_wait_receiving <= 0; + kbd_receiving <= 1; + kbd_transmitting <= 0; + end - .data_out(kbd_out_data), // data from mac - .strobe_out(kbd_out_strobe), - .data_in(kbd_in_data), // data to mac - .strobe_in(kbd_in_strobe) -); + // send/receive bits at rising edge of the keyboard clock + if (~kbdclk_d & kbdclk) begin + kbd_bitcnt <= kbd_bitcnt + 1'd1; + if (kbd_bitcnt == 3'd7) begin + if (kbd_transmitting) begin + kbd_out_strobe <= 1; + kbd_wait_receiving <= 1; + end + if (kbd_receiving) begin + kbd_receiving <= 0; + kbd_data_valid <= 0; + end + end + end + end + end + + // IWM + iwm i( + .clk(clk32), + .cep(clk8_en_p), + .cen(clk8_en_n), + ._reset(_cpuReset), + .selectIWM(selectIWM), + ._cpuRW(_cpuRW), + ._cpuLDS(_cpuLDS), + .dataIn(cpuDataIn), + .cpuAddrRegHi(cpuAddrRegHi), + .SEL(SEL), + .dataOut(iwmDataOut), + .insertDisk(insertDisk), + .diskSides(diskSides), + .diskEject(diskEject), + .diskMotor(diskMotor), + .diskAct(diskAct), + + .dskReadAddrInt(dskReadAddrInt), + .dskReadAckInt(dskReadAckInt), + .dskReadAddrExt(dskReadAddrExt), + .dskReadAckExt(dskReadAckExt), + .dskReadData(memoryDataIn[7:0]) + ); + + // SCC + scc s( + .clk(clk32), + .cep(clk8_en_p), + .cen(clk8_en_n), + .reset_hw(~_cpuReset), + .cs(selectSCC && (_cpuLDS == 1'b0 || _cpuUDS == 1'b0)), +// .cs(selectSCC && (_cpuLDS == 1'b0 || _cpuUDS == 1'b0) && cpuBusControl), +// .we(!_cpuRW), + .we(!_cpuLDS), + .rs(cpuAddrRegLo), + .wdata(cpuDataIn[15:8]), + .rdata(sccDataOut), + ._irq(_sccIrq), + .dcd_a(mouseX1), + .dcd_b(mouseY1), + .wreq(sccWReq)); + + // Video + videoShifter vs( + .clk32(clk32), + .memoryLatch(memoryLatch), + .dataIn(memoryDataIn), + .loadPixels(loadPixels), + .pixelOut(pixelOut)); + + // Mouse + ps2_mouse mouse( + .clk(clk32), + .ce(clk8_en_p), + .reset(~_cpuReset), + .ps2_mouse(ps2_mouse), + .x1(mouseX1), + .y1(mouseY1), + .x2(mouseX2), + .y2(mouseY2), + .button(mouseButton)); + + wire [7:0] kbd_in_data; + wire kbd_in_strobe; + reg [7:0] kbd_out_data; + reg kbd_out_strobe; + + // Keyboard + ps2_kbd kbd( + .clk(clk32), + .ce(clk8_en_p), + .reset(~_cpuReset), + .ps2_key(ps2_key), + .data_out(kbd_out_data), // data from mac + .strobe_out(kbd_out_strobe), + .data_in(kbd_in_data), // data to mac + .strobe_in(kbd_in_strobe), + .capslock(capslock) + ); + endmodule diff --git a/rtl/floppy.v b/rtl/floppy.v index 1e12c85..3371c90 100644 --- a/rtl/floppy.v +++ b/rtl/floppy.v @@ -170,34 +170,34 @@ module floppy // at time 0, latch a new byte and advance the drive head if (diskDataByteTimer == 0 && readyToAdvanceHead && diskImageData != 0) begin diskDataIn <= diskImageData; - newByteReady <= 1; + newByteReady <= 1; diskDataByteTimer <= 1; // make timer run again - + // clear diskImageData after it's used, so we can tell when we get a new one from the disk diskImageData <= 0; - + // for debugging, don't advance the head until the IWM says it's ready readyToAdvanceHead <= 1'b1; // TEMP: treat IWM as always ready end - + // extraRomReadAck comes every hsync which is every 21us. The iwm data rates // is 8MHZ/128 = 16us else begin // a timer governs when the next disk byte will become available diskDataByteTimer <= diskDataByteTimer + 1'b1; - + newByteReady <= 1'b0; - + if (dskReadAck) begin // whenever ACK is received, store the data from the current diskImageAddr diskImageData <= dskReadDataEnc; // xyz end - + if (advanceDriveHead) begin readyToAdvanceHead <= 1'b1; end end - + // switch drive sides if DRIVE_REG_RDDATA0 or DRIVE_REG_RDDATA1 are read // TODO: we don't know if this is a true read, since we don't know if IWM is selected or // could be bad if we use this test to flush a cache of encoded disk data @@ -208,13 +208,13 @@ module floppy end end end - + // create a signal on the falling edge of lstrb reg lstrbPrev; always @(posedge clk) if(cep) lstrbPrev <= lstrb; - + wire lstrbEdge = lstrb == 1'b0 && lstrbPrev == 1'b1; - + assign readData = (driveReadAddr == `DRIVE_REG_RDDATA0 || driveReadAddr == `DRIVE_REG_RDDATA1) ? diskDataIn : { driveRegsAsRead[driveReadAddr], 7'h00 }; diff --git a/rtl/fx68k/LICENSE b/rtl/fx68k/LICENSE new file mode 100644 index 0000000..f288702 --- /dev/null +++ b/rtl/fx68k/LICENSE @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/rtl/fx68k/README.md b/rtl/fx68k/README.md new file mode 100644 index 0000000..b1c8017 --- /dev/null +++ b/rtl/fx68k/README.md @@ -0,0 +1,17 @@ +# fx68k +FX68K 68000 cycle accurate SystemVerilog core + +Copyright (c) 2018 by Jorge Cwik +fx68k@fxatari.com + +FX68K is a 68000 cycle exact compatible core. At least in theory, it should be impossible to distinguish functionally from a real 68K processor. + +On Cyclone families it uses just over 5,100 LEs and about 5KB internal ram, reaching a max effective clock frequency close to 40MHz. Some optimizations are still possible to implement and increase the performance. + +The core is fully synchronous. Considerable effort was made to avoid any asynchronous logic. + +Written in SystemVerilog. + +The timing of the external bus signals is exactly as the original processor. The only feature that is not implemented yet is bus retry using the external HALT input signal. + +It was designed to replace an actual chip on a real board. This wasn't yet tested however and not all necessary output enable control signals are fully implemented. diff --git a/rtl/fx68k/fx68k.qip b/rtl/fx68k/fx68k.qip new file mode 100644 index 0000000..756c1c9 --- /dev/null +++ b/rtl/fx68k/fx68k.qip @@ -0,0 +1,4 @@ +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) fx68k.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) fx68kAlu.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) uaddrPla.sv ] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) fx68k.sdc ] \ No newline at end of file diff --git a/rtl/fx68k/fx68k.sdc b/rtl/fx68k/fx68k.sdc new file mode 100644 index 0000000..b2089ca --- /dev/null +++ b/rtl/fx68k/fx68k.sdc @@ -0,0 +1,9 @@ +set_multicycle_path -start -setup -from [get_keepers *fx68k:*|Ir[*]] -to [get_keepers *fx68k:*|microAddr[*]] 2 +set_multicycle_path -start -hold -from [get_keepers *fx68k:*|Ir[*]] -to [get_keepers *fx68k:*|microAddr[*]] 1 +set_multicycle_path -start -setup -from [get_keepers *fx68k:*|Ir[*]] -to [get_keepers *fx68k:*|nanoAddr[*]] 2 +set_multicycle_path -start -hold -from [get_keepers *fx68k:*|Ir[*]] -to [get_keepers *fx68k:*|nanoAddr[*]] 1 + +set_multicycle_path -start -setup -from {*|nanoLatch[*]} -to {*|excUnit|alu|pswCcr[*]} 2 +set_multicycle_path -start -hold -from {*|nanoLatch[*]} -to {*|excUnit|alu|pswCcr[*]} 1 +set_multicycle_path -start -setup -from {*|excUnit|alu|oper[*]} -to {*|excUnit|alu|pswCcr[*]} 2 +set_multicycle_path -start -hold -from {*|excUnit|alu|oper[*]} -to {*|excUnit|alu|pswCcr[*]} 1 diff --git a/rtl/fx68k/fx68k.sv b/rtl/fx68k/fx68k.sv new file mode 100644 index 0000000..0b9d0c0 --- /dev/null +++ b/rtl/fx68k/fx68k.sv @@ -0,0 +1,2718 @@ +// +// FX68K +// +// M68000 cycle accurate, fully synchronous +// Copyright (c) 2018,2021 by Jorge Cwik +// +// TODO: +// - Everything except bus retry already implemented. + +// altera message_off 10030 +// altera message_off 10230 + +`timescale 1 ns / 1 ns + +`define USE_E_CLKEN +/* + Define USE_E_CLKEN will output two signals that generate a single cycle pulse just before the raising and falling edges of E. + Use this when you need to generate changes that must be simultaneous with these edges. + Most systems don't need this. Note that these signals are not registered. + */ + +// Define this to run a self contained compilation test build +// `define FX68K_TEST + +localparam CF = 0, VF = 1, ZF = 2, NF = 3, XF = 4, SF = 13; + +localparam UADDR_WIDTH = 10; +localparam UROM_WIDTH = 17; +localparam UROM_DEPTH = 1024; + +localparam NADDR_WIDTH = 9; +localparam NANO_WIDTH = 68; +localparam NANO_DEPTH = 336; + +localparam BSER1_NMA = 'h003; +localparam RSTP0_NMA = 'h002; +localparam HALT1_NMA = 'h001; +localparam TRAC1_NMA = 'h1C0; +localparam ITLX1_NMA = 'h1C4; + +localparam TVN_SPURIOUS = 12; +localparam TVN_AUTOVEC = 13; +localparam TVN_INTERRUPT = 15; + +localparam NANO_DOB_DBD = 2'b01; +localparam NANO_DOB_ADB = 2'b10; +localparam NANO_DOB_ALU = 2'b11; + + +// Clocks, phases and resets +typedef struct { + logic clk; + logic extReset; // External sync reset on emulated system + logic pwrUp; // Asserted together with reset on emulated system coldstart + logic enPhi1, enPhi2; // Clock enables. Next cycle is PHI1 or PHI2 +} s_clks; + +// IRD decoded signals +typedef struct { + logic isPcRel; + logic isTas; + logic implicitSp; + logic toCcr; + logic rxIsDt, ryIsDt; + logic rxIsUsp, rxIsMovem, movemPreDecr; + logic isByte; + logic isMovep; + logic [2:0] rx, ry; + logic rxIsAreg, ryIsAreg; + logic [15:0] ftuConst; + logic [5:0] macroTvn; + logic inhibitCcr; +} s_irdecod; + +// Nano code decoded signals +typedef struct { + logic permStart; + logic waitBusFinish; + logic isWrite; + logic busByte; + logic isRmc; + logic noLowByte, noHighByte; + + logic updTpend, clrTpend; + logic tvn2Ftu, const2Ftu; + logic ftu2Dbl, ftu2Abl; + logic abl2Pren, updPren; + logic inl2psw, ftu2Sr, sr2Ftu, ftu2Ccr, pswIToFtu; + logic ird2Ftu, ssw2Ftu; + logic initST; + logic Ir2Ird; + + logic auClkEn, noSpAlign; + logic [2:0] auCntrl; + logic todbin, toIrc; + logic dbl2Atl, abl2Atl, atl2Abl, atl2Dbl; + logic abh2Ath, dbh2Ath; + logic ath2Dbh, ath2Abh; + + logic db2Aob, ab2Aob, au2Aob; + logic aob2Ab, updSsw; + // logic adb2Dob, dbd2Dob, alu2Dob; + logic [1:0] dobCtrl; + + logic abh2reg, abl2reg; + logic reg2abl, reg2abh; + logic dbh2reg, dbl2reg; + logic reg2dbl, reg2dbh; + logic ssp, pchdbh, pcldbl, pclabl, pchabh; + + logic rxh2dbh, rxh2abh; + logic dbl2rxl, dbh2rxh; + logic rxl2db, rxl2ab; + logic abl2rxl, abh2rxh; + logic dbh2ryh, abh2ryh; + logic ryl2db, ryl2ab; + logic ryh2dbh, ryh2abh; + logic dbl2ryl, abl2ryl; + logic rz; + logic rxlDbl; + + logic [2:0] aluColumn; + logic [1:0] aluDctrl; + logic aluActrl; + logic aluInit, aluFinish; + logic abd2Dcr, dcr2Dbd; + logic dbd2Alue, alue2Dbd; + logic dbd2Alub, abd2Alub; + + logic alu2Dbd, alu2Abd; + logic au2Db, au2Ab, au2Pc; + logic dbin2Abd, dbin2Dbd; + logic extDbh, extAbh; + logic ablAbd, ablAbh; + logic dblDbd, dblDbh; + logic abdIsByte; +} s_nanod; + +module fx68k( + input clk, + input HALTn, // Used for single step only. Force high if not used + // input logic HALTn = 1'b1, // Not all tools support default port values + + // These two signals don't need to be registered. They are not async reset. + input extReset, // External sync reset on emulated system + input pwrUp, // Asserted together with reset on emulated system coldstart + input enPhi1, enPhi2, // Clock enables. Next cycle is PHI1 or PHI2 + + output eRWn, output ASn, output LDSn, output UDSn, + output logic E, output VMAn, + +`ifdef USE_E_CLKEN + // divide the E clock by two + input E_div, + // Next cycle would be raising/falling edge of E output + output E_PosClkEn, E_NegClkEn, +`endif + + output FC0, output FC1, output FC2, + output BGn, + output oRESETn, output oHALTEDn, + input DTACKn, input VPAn, + input BERRn, + input BRn, BGACKn, + input IPL0n, input IPL1n, input IPL2n, + input [15:0] iEdb, output [15:0] oEdb, + output [23:1] eab + ); + + // wire clock = Clks.clk; + s_clks Clks; + + assign Clks.clk = clk; + assign Clks.extReset = extReset; + assign Clks.pwrUp = pwrUp; + assign Clks.enPhi1 = enPhi1; + assign Clks.enPhi2 = enPhi2; + + wire wClk; + + // Internal sub clocks T1-T4 + enum int unsigned { T0 = 0, T1, T2, T3, T4} tState; + wire enT1 = Clks.enPhi1 & (tState == T4) & ~wClk; + wire enT2 = Clks.enPhi2 & (tState == T1); + wire enT3 = Clks.enPhi1 & (tState == T2); + wire enT4 = Clks.enPhi2 & ((tState == T0) | (tState == T3)); + + // T4 continues ticking during reset and group0 exception. + // We also need it to erase ucode output latched on T4. + always_ff @( posedge Clks.clk) begin + if( Clks.pwrUp) + tState <= T0; + else begin + case( tState) + T0: if( Clks.enPhi2) tState <= T4; + T1: if( Clks.enPhi2) tState <= T2; + T2: if( Clks.enPhi1) tState <= T3; + T3: if( Clks.enPhi2) tState <= T4; + T4: if( Clks.enPhi1) tState <= wClk ? T0 : T1; + endcase + end + end + + // The following signals are synchronized with 3 couplers, phi1-phi2-phi1. + // Will be valid internally one cycle later if changed at the rasing edge of the clock. + // + // DTACK, BERR + + // DTACK valid at S6 if changed at the rasing edge of S4 to avoid wait states. + // SNC (sncClkEn) is deasserted together (unless DTACK asserted too early). + // + // We synchronize some signals half clock earlier. We compensate later + reg rDtack, rBerr; + reg [2:0] rIpl, iIpl; + reg Vpai, BeI, Halti, BRi, BgackI, BeiDelay; + // reg rBR, rHALT; + wire BeDebounced = ~( BeI | BeiDelay); + + always_ff @( posedge Clks.clk) begin + if( Clks.pwrUp) begin + rBerr <= 1'b0; + BeI <= 1'b0; + end + else if( Clks.enPhi2) begin + rDtack <= DTACKn; + rBerr <= BERRn; + rIpl <= ~{ IPL2n, IPL1n, IPL0n}; + iIpl <= rIpl; + + // Needed for cycle accuracy but only if BR or HALT are asserted on the wrong edge of the clock + // rBR <= BRn; + // rHALT <= HALTn; + end + else if( Clks.enPhi1) begin + Vpai <= VPAn; + BeI <= rBerr; + BeiDelay <= BeI; + BgackI <= BGACKn; + + BRi <= BRn; + Halti <= HALTn; + // BRi <= rBR; + // Halti <= rHALT; + end + end + + // Instantiate micro and nano rom + logic [NANO_WIDTH-1:0] nanoLatch; + logic [NANO_WIDTH-1:0] nanoOutput; + logic [UROM_WIDTH-1:0] microLatch; + logic [UROM_WIDTH-1:0] microOutput; + + logic [UADDR_WIDTH-1:0] microAddr, nma; + logic [NADDR_WIDTH-1:0] nanoAddr, orgAddr; + wire rstUrom; + + // For the time being, address translation is done for nanorom only. + microToNanoAddr microToNanoAddr( .uAddr( nma), .orgAddr); + + // Output of these modules will be updated at T2 at the latest (depending on clock division) + + nanoRom nanoRom( .clk( Clks.clk), .nanoAddr, .nanoOutput); + uRom uRom( .clk( Clks.clk), .microAddr, .microOutput); + + always_ff @( posedge Clks.clk) begin + // uaddr originally latched on T1, except bits 6 & 7, the conditional bits, on T2 + // Seems we can latch whole address at either T1 or T2 + + // Originally it's invalid on hardware reset, and forced later when coming out of reset + if( Clks.pwrUp) begin + microAddr <= RSTP0_NMA; + nanoAddr <= RSTP0_NMA; + end + else if( enT1) begin + microAddr <= nma; + nanoAddr <= orgAddr; // Register translated uaddr to naddr + end + + if( Clks.extReset) begin + microLatch <= '0; + nanoLatch <= '0; + end + else if( rstUrom) begin + // Originally reset these bits only. Not strictly needed like this. + // Can reset the whole register if it is important. + { microLatch[16], microLatch[15], microLatch[0]} <= '0; + nanoLatch <= '0; + end + else if( enT3) begin + microLatch <= microOutput; + nanoLatch <= nanoOutput; + end + + end + + + // Decoded nanocode signals + s_nanod Nanod; + // IRD decoded control signals + s_irdecod Irdecod; + + // + reg Tpend; + reg intPend; // Interrupt pending + reg pswT, pswS; + reg [ 2:0] pswI; + wire [7:0] ccr; + + wire [15:0] psw = { pswT, 1'b0, pswS, 2'b00, pswI, ccr}; + + reg [15:0] ftu; + reg [15:0] Irc, Ir, Ird; + + wire [15:0] alue; + wire [15:0] Abl; + wire prenEmpty, au05z, dcr4, ze; + + wire [UADDR_WIDTH-1:0] a1, a2, a3; + wire isPriv, isIllegal, isLineA, isLineF; + + + // IR & IRD forwarding + always_ff @( posedge Clks.clk) begin + if( enT1) begin + if( Nanod.Ir2Ird) + Ird <= Ir; + else if(microLatch[0]) // prevented by IR => IRD ! + Ir <= Irc; + end + end + + wire [3:0] tvn; + wire waitBusCycle, busStarting; + wire BusRetry = 1'b0; + wire busAddrErr; + wire bciWrite; // Last bus cycle was write + wire bgBlock, busAvail; + wire addrOe; + + wire busIsByte = Nanod.busByte & (Irdecod.isByte | Irdecod.isMovep); + wire aob0; + + reg iStop; // Internal signal for ending bus cycle + reg A0Err; // Force bus/address error ucode + reg excRst; // Signal reset exception to sequencer + reg BerrA; + reg Spuria, Avia; + wire Iac; + + reg rAddrErr, iBusErr, Err6591; + wire iAddrErr = rAddrErr & addrOe; // To simulate async reset + wire enErrClk; + + // Reset micro/nano latch after T4 of the current ublock. + assign rstUrom = Clks.enPhi1 & enErrClk; + + uaddrDecode uaddrDecode( .opcode( Ir), .a1, .a2, .a3, .isPriv, .isIllegal, .isLineA, .isLineF, .lineBmap()); + + sequencer sequencer( .Clks, .enT3, .microLatch, .Ird, + .A0Err, .excRst, .BerrA, .busAddrErr, .Spuria, .Avia, + .Tpend, .intPend, .isIllegal, .isPriv, .isLineA, .isLineF, + .nma, .a1, .a2, .a3, .tvn, + .psw, .prenEmpty, .au05z, .dcr4, .ze, .alue01( alue[1:0]), .i11( Irc[ 11]) ); + + excUnit excUnit( .Clks, .Nanod, .Irdecod, .enT1, .enT2, .enT3, .enT4, + .Ird, .ftu, .iEdb, .pswS, + .prenEmpty, .au05z, .dcr4, .ze, .AblOut( Abl), .eab, .aob0, .Irc, .oEdb, + .alue, .ccr); + + nDecoder3 nDecoder( .Clks, .Nanod, .Irdecod, .enT2, .enT4, .microLatch, .nanoLatch); + + irdDecode irdDecode( .ird( Ird), .Irdecod); + + busControl busControl( .Clks, .enT1, .enT4, .permStart( Nanod.permStart), .permStop( Nanod.waitBusFinish), .iStop, + .aob0, .isWrite( Nanod.isWrite), .isRmc( Nanod.isRmc), .isByte( busIsByte), .busAvail, + .bciWrite, .addrOe, .bgBlock, .waitBusCycle, .busStarting, .busAddrErr, + .rDtack, .BeDebounced, .Vpai, + .ASn, .LDSn, .UDSn, .eRWn); + + busArbiter busArbiter( .Clks, .BRi, .BgackI, .Halti, .bgBlock, .busAvail, .BGn); + + + // Output reset & halt control + wire [1:0] uFc = microLatch[ 16:15]; + logic oReset, oHalted; + assign oRESETn = !oReset; + assign oHALTEDn = !oHalted; + + // FC without permStart is special, either reset or halt + always_ff @( posedge Clks.clk) begin + if( Clks.pwrUp) begin + oReset <= 1'b0; + oHalted <= 1'b0; + end + else if( enT1) begin + oReset <= (uFc == 2'b01) & !Nanod.permStart; + oHalted <= (uFc == 2'b10) & !Nanod.permStart; + end + end + + logic [2:0] rFC; + assign { FC2, FC1, FC0} = rFC; // ~rFC; + assign Iac = {rFC == 3'b111}; // & Control output enable !! + + always_ff @( posedge Clks.clk) begin + if( Clks.extReset) + rFC <= '0; + else if( enT1 & Nanod.permStart) begin // S0 phase of bus cycle + rFC[2] <= pswS; + // If FC is type 'n' (0) at ucode, access type depends on PC relative mode + // We don't care about RZ in this case. Those uinstructions with RZ don't start a bus cycle. + rFC[1] <= microLatch[ 16] | ( ~microLatch[ 15] & Irdecod.isPcRel); + rFC[0] <= microLatch[ 15] | ( ~microLatch[ 16] & ~Irdecod.isPcRel); + end + end + + + // IPL interface + reg [2:0] inl; // Int level latch + reg updIll; + reg prevNmi; + + wire nmi = (iIpl == 3'b111); + wire iplStable = (iIpl == rIpl); + wire iplComp = iIpl > pswI; + + always_ff @( posedge Clks.clk) begin + if( Clks.extReset) begin + intPend <= 1'b0; + prevNmi <= 1'b0; + end + else begin + if( Clks.enPhi2) + prevNmi <= nmi; + + // Originally async RS-Latch on PHI2, followed by a transparent latch on T2 + // Tricky because they might change simultaneously + // Syncronous on PHI2 is equivalent as long as the output is read on T3! + + // Set on stable & NMI edge or compare + // Clear on: NMI Iack or (stable & !NMI & !Compare) + + if( Clks.enPhi2) begin + if( iplStable & ((nmi & ~prevNmi) | iplComp) ) + intPend <= 1'b1; + else if( ((inl == 3'b111) & Iac) | (iplStable & !nmi & !iplComp) ) + intPend <= 1'b0; + end + end + + if( Clks.extReset) begin + inl <= '1; + updIll <= 1'b0; + end + else if( enT4) + updIll <= microLatch[0]; // Update on any IRC->IR + else if( enT1 & updIll) + inl <= iIpl; // Timing is correct. + + // Spurious interrupt, BERR on Interrupt Ack. + // Autovector interrupt. VPA on IACK. + // Timing is tight. Spuria is deasserted just after exception exception is recorded. + if( enT4) begin + Spuria <= ~BeiDelay & Iac; + Avia <= ~Vpai & Iac; + end + + end + + assign enErrClk = iAddrErr | iBusErr; + assign wClk = waitBusCycle | ~BeI | iAddrErr | Err6591; + + // E clock and counter, VMA + reg [3:0] eCntr; + reg rVma; + + assign VMAn = rVma; + + // Internal stop just one cycle before E falling edge + wire xVma = ~rVma & (eCntr == 8) & en_E; + +`ifdef USE_E_CLKEN + assign E_PosClkEn = (Clks.enPhi2 & (eCntr == 5) & en_E); + assign E_NegClkEn = (Clks.enPhi2 & (eCntr == 9) & en_E); +`endif + + reg en_E; + + always_ff @( posedge Clks.clk) begin + if( Clks.pwrUp) begin + E <= 1'b0; + eCntr <='0; + rVma <= 1'b1; + en_E <= 1; + end + if( Clks.enPhi1) + if (E_div) en_E <= !en_E; else en_E <= 1'b1; + + if( Clks.enPhi2 & en_E) begin + if( eCntr == 9) + E <= 1'b0; + else if( eCntr == 5) + E <= 1'b1; + + if( eCntr == 9) + eCntr <= '0; + else + eCntr <= eCntr + 1'b1; + end + + if( Clks.enPhi2 & addrOe & ~Vpai & (eCntr == 3) & en_E) + rVma <= 1'b0; + else if( Clks.enPhi1 & eCntr == '0 & en_E) + rVma <= 1'b1; + end + + always_ff @( posedge Clks.clk) begin + + // This timing is critical to stop the clock phases at the exact point on bus/addr error. + // Timing should be such that current ublock completes (up to T3 or T4). + // But T1 for the next ublock shouldn't happen. Next T1 only after resetting ucode and ncode latches. + + if( Clks.extReset) + rAddrErr <= 1'b0; + else if( Clks.enPhi1) begin + if( busAddrErr & addrOe) // Not on T1 ?! + rAddrErr <= 1'b1; + else if( ~addrOe) // Actually async reset! + rAddrErr <= 1'b0; + end + + if( Clks.extReset) + iBusErr <= 1'b0; + else if( Clks.enPhi1) begin + iBusErr <= ( BerrA & ~BeI & ~Iac & !BusRetry); + end + + if( Clks.extReset) + BerrA <= 1'b0; + else if( Clks.enPhi2) begin + if( ~BeI & ~Iac & addrOe) + BerrA <= 1'b1; + // else if( BeI & addrOe) // Bad, async reset since addrOe raising edge + else if( BeI & busStarting) // So replaced with this that raises one cycle earlier + BerrA <= 1'b0; + end + + // Signal reset exception to sequencer. + // Originally cleared on 1st T2 after permstart. Must keep it until TVN latched. + if( Clks.extReset) + excRst <= 1'b1; + else if( enT2 & Nanod.permStart) + excRst <= 1'b0; + + if( Clks.extReset) + A0Err <= 1'b1; // A0 Reset + else if( enT3) // Keep set until new urom words are being latched + A0Err <= 1'b0; + else if( Clks.enPhi1 & enErrClk & (busAddrErr | BerrA)) // Check bus error timing + A0Err <= 1'b1; + + if( Clks.extReset) begin + iStop <= 1'b0; + Err6591 <= 1'b0; + end + else if( Clks.enPhi1) + Err6591 <= enErrClk; + else if( Clks.enPhi2) + iStop <= xVma | (Vpai & (iAddrErr | ~rBerr)); + end + + // PSW + logic irdToCcr_t4; + always_ff @( posedge Clks.clk) begin + if( Clks.pwrUp) begin + Tpend <= 1'b0; + {pswT, pswS, pswI } <= '0; + irdToCcr_t4 <= '0; + end + + else if( enT4) begin + irdToCcr_t4 <= Irdecod.toCcr; + end + + else if( enT3) begin + + // UNIQUE IF !! + if( Nanod.updTpend) + Tpend <= pswT; + else if( Nanod.clrTpend) + Tpend <= 1'b0; + + // UNIQUE IF !! + if( Nanod.ftu2Sr & !irdToCcr_t4) + {pswT, pswS, pswI } <= { ftu[ 15], ftu[13], ftu[10:8]}; + else begin + if( Nanod.initST) begin + pswS <= 1'b1; + pswT <= 1'b0; + end + if( Nanod.inl2psw) + pswI <= inl; + end + + end + end + + // FTU + reg [4:0] ssw; + reg [3:0] tvnLatch; + logic [15:0] tvnMux; + reg inExcept01; + + // Seems CPU has a buglet here. + // Flagging group 0 exceptions from TVN might not work because some bus cycles happen before TVN is updated. + // But doesn't matter because a group 0 exception inside another one will halt the CPU anyway and won't save the SSW. + + always_ff @( posedge Clks.clk) begin + + // Updated at the start of the exception ucode + if( Nanod.updSsw & enT3) begin + ssw <= { ~bciWrite, inExcept01, rFC}; + end + + // Update TVN on T1 & IR=>IRD + if( enT1 & Nanod.Ir2Ird) begin + tvnLatch <= tvn; + inExcept01 <= (tvn != 1); + end + + if( Clks.pwrUp) + ftu <= '0; + else if( enT3) begin + unique case( 1'b1) + Nanod.tvn2Ftu: ftu <= tvnMux; + + // 0 on unused bits seem to come from ftuConst PLA previously clearing FBUS + Nanod.sr2Ftu: ftu <= {pswT, 1'b0, pswS, 2'b00, pswI, 3'b000, ccr[4:0] }; + + Nanod.ird2Ftu: ftu <= Ird; + Nanod.ssw2Ftu: ftu[4:0] <= ssw; // Undoc. Other bits must be preserved from IRD saved above! + Nanod.pswIToFtu: ftu <= { 12'hFFF, pswI, 1'b0}; // Interrupt level shifted + Nanod.const2Ftu: ftu <= Irdecod.ftuConst; + Nanod.abl2Pren: ftu <= Abl; // From ALU or datareg. Used for SR modify + default: ftu <= ftu; + endcase + end + end + + always_comb begin + if( inExcept01) begin + // Unique IF !!! + if( tvnLatch == TVN_SPURIOUS) + tvnMux = {9'b0, 5'd24, 2'b00}; + else if( tvnLatch == TVN_AUTOVEC) + tvnMux = {9'b0, 2'b11, pswI, 2'b00}; // Set TVN PLA decoder + else if( tvnLatch == TVN_INTERRUPT) + tvnMux = {6'b0, Ird[7:0], 2'b00}; // Interrupt vector was read and transferred to IRD + else + tvnMux = {10'b0, tvnLatch, 2'b00}; + end + else + tvnMux = { 8'h0, Irdecod.macroTvn, 2'b00}; + end + +endmodule + +// Nanorom (plus) decoder for die nanocode +module nDecoder3( input s_clks Clks, input s_irdecod Irdecod, output s_nanod Nanod, + input enT2, enT4, + input [UROM_WIDTH-1:0] microLatch, + input [NANO_WIDTH-1:0] nanoLatch); + +localparam NANO_IR2IRD = 67; +localparam NANO_TOIRC = 66; +localparam NANO_ALU_COL = 63; // ALU operator column order is 63-64-65 ! +localparam NANO_ALU_FI = 61; // ALU finish-init 62-61 +localparam NANO_TODBIN = 60; +localparam NANO_ALUE = 57; // 57-59 shared with DCR control +localparam NANO_DCR = 57; // 57-59 shared with ALUE control +localparam NANO_DOBCTRL_1 = 56; // Input to control and permwrite +localparam NANO_LOWBYTE = 55; // Used by MOVEP +localparam NANO_HIGHBYTE = 54; +localparam NANO_DOBCTRL_0 = 53; // Input to control and permwrite +localparam NANO_ALU_DCTRL = 51; // 52-51 databus input mux control +localparam NANO_ALU_ACTRL = 50; // addrbus input mux control +localparam NANO_DBD2ALUB = 49; +localparam NANO_ABD2ALUB = 48; +localparam NANO_DBIN2DBD = 47; +localparam NANO_DBIN2ABD = 46; +localparam NANO_ALU2ABD = 45; +localparam NANO_ALU2DBD = 44; +localparam NANO_RZ = 43; +localparam NANO_BUSBYTE = 42; // If *both* this set and instruction is byte sized, then bus cycle is byte sized. +localparam NANO_PCLABL = 41; +localparam NANO_RXL_DBL = 40; // Switches RXL/RYL on DBL/ABL buses +localparam NANO_PCLDBL = 39; +localparam NANO_ABDHRECHARGE = 38; +localparam NANO_REG2ABL = 37; // register to ABL +localparam NANO_ABL2REG = 36; // ABL to register +localparam NANO_ABLABD = 35; +localparam NANO_DBLDBD = 34; +localparam NANO_DBL2REG = 33; // DBL to register +localparam NANO_REG2DBL = 32; // register to DBL +localparam NANO_ATLCTRL = 29; // 31-29 +localparam NANO_FTUCONTROL = 25; +localparam NANO_SSP = 24; +localparam NANO_RXH_DBH = 22; // Switches RXH/RYH on DBH/ABH buses +localparam NANO_AUOUT = 20; // 21-20 +localparam NANO_AUCLKEN = 19; +localparam NANO_AUCTRL = 16; // 18-16 +localparam NANO_DBLDBH = 15; +localparam NANO_ABLABH = 14; +localparam NANO_EXT_ABH = 13; +localparam NANO_EXT_DBH = 12; +localparam NANO_ATHCTRL = 9; // 11-9 +localparam NANO_REG2ABH = 8; // register to ABH +localparam NANO_ABH2REG = 7; // ABH to register +localparam NANO_REG2DBH = 6; // register to DBH +localparam NANO_DBH2REG = 5; // DBH to register +localparam NANO_AOBCTRL = 3; // 4-3 +localparam NANO_PCH = 0; // 1-0 PchDbh PchAbh +localparam NANO_NO_SP_ALGN = 0; // Same bits as above when both set + +localparam NANO_FTU_UPDTPEND = 1; // Also loads FTU constant according to IRD ! +localparam NANO_FTU_INIT_ST = 15; // Set S, clear T (but not TPEND) +localparam NANO_FTU_CLRTPEND = 14; +localparam NANO_FTU_TVN = 13; +localparam NANO_FTU_ABL2PREN = 12; // ABL => FTU & ABL => PREN. Both transfers enabled, but only one will be used depending on uroutine. +localparam NANO_FTU_SSW = 11; +localparam NANO_FTU_RSTPREN = 10; +localparam NANO_FTU_IRD = 9; +localparam NANO_FTU_2ABL = 8; +localparam NANO_FTU_RDSR = 7; +localparam NANO_FTU_INL = 6; +localparam NANO_FTU_PSWI = 5; // Read Int Mask into FTU +localparam NANO_FTU_DBL = 4; +localparam NANO_FTU_2SR = 2; +localparam NANO_FTU_CONST = 1; + + reg [3:0] ftuCtrl; + + logic [2:0] athCtrl, atlCtrl; + assign athCtrl = nanoLatch[ NANO_ATHCTRL+2: NANO_ATHCTRL]; + assign atlCtrl = nanoLatch[ NANO_ATLCTRL+2: NANO_ATLCTRL]; + wire [1:0] aobCtrl = nanoLatch[ NANO_AOBCTRL+1:NANO_AOBCTRL]; + wire [1:0] dobCtrl = {nanoLatch[ NANO_DOBCTRL_1], nanoLatch[NANO_DOBCTRL_0]}; + + always_ff @( posedge Clks.clk) begin + if( enT4) begin + // Reverse order! + ftuCtrl <= { nanoLatch[ NANO_FTUCONTROL+0], nanoLatch[ NANO_FTUCONTROL+1], nanoLatch[ NANO_FTUCONTROL+2], nanoLatch[ NANO_FTUCONTROL+3]} ; + + Nanod.auClkEn <= !nanoLatch[ NANO_AUCLKEN]; + Nanod.auCntrl <= nanoLatch[ NANO_AUCTRL+2 : NANO_AUCTRL+0]; + Nanod.noSpAlign <= (nanoLatch[ NANO_NO_SP_ALGN + 1:NANO_NO_SP_ALGN] == 2'b11); + Nanod.extDbh <= nanoLatch[ NANO_EXT_DBH]; + Nanod.extAbh <= nanoLatch[ NANO_EXT_ABH]; + Nanod.todbin <= nanoLatch[ NANO_TODBIN]; + Nanod.toIrc <= nanoLatch[ NANO_TOIRC]; + + // ablAbd is disabled on byte transfers (adbhCharge plus irdIsByte). Not sure the combination makes much sense. + // It happens in a few cases but I don't see anything enabled on abL (or abH) section anyway. + + Nanod.ablAbd <= nanoLatch[ NANO_ABLABD]; + Nanod.ablAbh <= nanoLatch[ NANO_ABLABH]; + Nanod.dblDbd <= nanoLatch[ NANO_DBLDBD]; + Nanod.dblDbh <= nanoLatch[ NANO_DBLDBH]; + + Nanod.dbl2Atl <= (atlCtrl == 3'b010); + Nanod.atl2Dbl <= (atlCtrl == 3'b011); + Nanod.abl2Atl <= (atlCtrl == 3'b100); + Nanod.atl2Abl <= (atlCtrl == 3'b101); + + Nanod.aob2Ab <= (athCtrl == 3'b101); // Used on BSER1 only + + Nanod.abh2Ath <= (athCtrl == 3'b001) | (athCtrl == 3'b101); + Nanod.dbh2Ath <= (athCtrl == 3'b100); + Nanod.ath2Dbh <= (athCtrl == 3'b110); + Nanod.ath2Abh <= (athCtrl == 3'b011); + + Nanod.alu2Dbd <= nanoLatch[ NANO_ALU2DBD]; + Nanod.alu2Abd <= nanoLatch[ NANO_ALU2ABD]; + + Nanod.abd2Dcr <= (nanoLatch[ NANO_DCR+1:NANO_DCR] == 2'b11); + Nanod.dcr2Dbd <= (nanoLatch[ NANO_DCR+2:NANO_DCR+1] == 2'b11); + Nanod.dbd2Alue <= (nanoLatch[ NANO_ALUE+2:NANO_ALUE+1] == 2'b10); + Nanod.alue2Dbd <= (nanoLatch[ NANO_ALUE+1:NANO_ALUE] == 2'b01); + + Nanod.dbd2Alub <= nanoLatch[ NANO_DBD2ALUB]; + Nanod.abd2Alub <= nanoLatch[ NANO_ABD2ALUB]; + + // Originally not latched. We better should because we transfer one cycle later, T3 instead of T1. + Nanod.dobCtrl <= dobCtrl; + // Nanod.adb2Dob <= (dobCtrl == 2'b10); Nanod.dbd2Dob <= (dobCtrl == 2'b01); Nanod.alu2Dob <= (dobCtrl == 2'b11); + + end + end + + // Update SSW at the start of Bus/Addr error ucode + assign Nanod.updSsw = Nanod.aob2Ab; + + assign Nanod.updTpend = (ftuCtrl == NANO_FTU_UPDTPEND); + assign Nanod.clrTpend = (ftuCtrl == NANO_FTU_CLRTPEND); + assign Nanod.tvn2Ftu = (ftuCtrl == NANO_FTU_TVN); + assign Nanod.const2Ftu = (ftuCtrl == NANO_FTU_CONST); + assign Nanod.ftu2Dbl = (ftuCtrl == NANO_FTU_DBL) | ( ftuCtrl == NANO_FTU_INL); + assign Nanod.ftu2Abl = (ftuCtrl == NANO_FTU_2ABL); + assign Nanod.inl2psw = (ftuCtrl == NANO_FTU_INL); + assign Nanod.pswIToFtu = (ftuCtrl == NANO_FTU_PSWI); + assign Nanod.ftu2Sr = (ftuCtrl == NANO_FTU_2SR); + assign Nanod.sr2Ftu = (ftuCtrl == NANO_FTU_RDSR); + assign Nanod.ird2Ftu = (ftuCtrl == NANO_FTU_IRD); // Used on bus/addr error + assign Nanod.ssw2Ftu = (ftuCtrl == NANO_FTU_SSW); + assign Nanod.initST = (ftuCtrl == NANO_FTU_INL) | (ftuCtrl == NANO_FTU_CLRTPEND) | (ftuCtrl == NANO_FTU_INIT_ST); + assign Nanod.abl2Pren = (ftuCtrl == NANO_FTU_ABL2PREN); + assign Nanod.updPren = (ftuCtrl == NANO_FTU_RSTPREN); + + assign Nanod.Ir2Ird = nanoLatch[ NANO_IR2IRD]; + + // ALU control better latched later after combining with IRD decoding + + assign Nanod.aluDctrl = nanoLatch[ NANO_ALU_DCTRL+1 : NANO_ALU_DCTRL]; + assign Nanod.aluActrl = nanoLatch[ NANO_ALU_ACTRL]; + assign Nanod.aluColumn = { nanoLatch[ NANO_ALU_COL], nanoLatch[ NANO_ALU_COL+1], nanoLatch[ NANO_ALU_COL+2]}; + wire [1:0] aluFinInit = nanoLatch[ NANO_ALU_FI+1:NANO_ALU_FI]; + assign Nanod.aluFinish = (aluFinInit == 2'b10); + assign Nanod.aluInit = (aluFinInit == 2'b01); + + // FTU 2 CCR encoded as both ALU Init and ALU Finish set. + // In theory this encoding allows writes to CCR without writing to SR + // But FTU 2 CCR and to SR are both set together at nanorom. + assign Nanod.ftu2Ccr = ( aluFinInit == 2'b11); + + assign Nanod.abdIsByte = nanoLatch[ NANO_ABDHRECHARGE]; + + // Not being latched on T4 creates non unique case warning! + assign Nanod.au2Db = (nanoLatch[ NANO_AUOUT + 1: NANO_AUOUT] == 2'b01); + assign Nanod.au2Ab = (nanoLatch[ NANO_AUOUT + 1: NANO_AUOUT] == 2'b10); + assign Nanod.au2Pc = (nanoLatch[ NANO_AUOUT + 1: NANO_AUOUT] == 2'b11); + + assign Nanod.db2Aob = (aobCtrl == 2'b10); + assign Nanod.ab2Aob = (aobCtrl == 2'b01); + assign Nanod.au2Aob = (aobCtrl == 2'b11); + + assign Nanod.dbin2Abd = nanoLatch[ NANO_DBIN2ABD]; + assign Nanod.dbin2Dbd = nanoLatch[ NANO_DBIN2DBD]; + + assign Nanod.permStart = (| aobCtrl); + assign Nanod.isWrite = ( | dobCtrl); + assign Nanod.waitBusFinish = nanoLatch[ NANO_TOIRC] | nanoLatch[ NANO_TODBIN] | Nanod.isWrite; + assign Nanod.busByte = nanoLatch[ NANO_BUSBYTE]; + + assign Nanod.noLowByte = nanoLatch[ NANO_LOWBYTE]; + assign Nanod.noHighByte = nanoLatch[ NANO_HIGHBYTE]; + + // Not registered. Register at T4 after combining + // Might be better to remove all those and combine here instead of at execution unit !! + assign Nanod.abl2reg = nanoLatch[ NANO_ABL2REG]; + assign Nanod.abh2reg = nanoLatch[ NANO_ABH2REG]; + assign Nanod.dbl2reg = nanoLatch[ NANO_DBL2REG]; + assign Nanod.dbh2reg = nanoLatch[ NANO_DBH2REG]; + assign Nanod.reg2dbl = nanoLatch[ NANO_REG2DBL]; + assign Nanod.reg2dbh = nanoLatch[ NANO_REG2DBH]; + assign Nanod.reg2abl = nanoLatch[ NANO_REG2ABL]; + assign Nanod.reg2abh = nanoLatch[ NANO_REG2ABH]; + + assign Nanod.ssp = nanoLatch[ NANO_SSP]; + + assign Nanod.rz = nanoLatch[ NANO_RZ]; + + // Actually DTL can't happen on PC relative mode. See IR decoder. + + wire dtldbd = 1'b0; + wire dthdbh = 1'b0; + wire dtlabd = 1'b0; + wire dthabh = 1'b0; + + wire dblSpecial = Nanod.pcldbl | dtldbd; + wire dbhSpecial = Nanod.pchdbh | dthdbh; + wire ablSpecial = Nanod.pclabl | dtlabd; + wire abhSpecial = Nanod.pchabh | dthabh; + + // + // Combine with IRD decoding + // Careful that IRD is updated only on T1! All output depending on IRD must be latched on T4! + // + + // PC used instead of RY on PC relative instuctions + + assign Nanod.rxlDbl = nanoLatch[ NANO_RXL_DBL]; + wire isPcRel = Irdecod.isPcRel & !Nanod.rz; + wire pcRelDbl = isPcRel & !nanoLatch[ NANO_RXL_DBL]; + wire pcRelDbh = isPcRel & !nanoLatch[ NANO_RXH_DBH]; + wire pcRelAbl = isPcRel & nanoLatch[ NANO_RXL_DBL]; + wire pcRelAbh = isPcRel & nanoLatch[ NANO_RXH_DBH]; + + assign Nanod.pcldbl = nanoLatch[ NANO_PCLDBL] | pcRelDbl; + assign Nanod.pchdbh = (nanoLatch[ NANO_PCH+1:NANO_PCH] == 2'b01) | pcRelDbh; + + assign Nanod.pclabl = nanoLatch[ NANO_PCLABL] | pcRelAbl; + assign Nanod.pchabh = (nanoLatch[ NANO_PCH+1:NANO_PCH] == 2'b10) | pcRelAbh; + + // Might be better not to register these signals to allow latching RX/RY mux earlier! + // But then must latch Irdecod.isPcRel on T3! + + always_ff @( posedge Clks.clk) begin + if( enT4) begin + Nanod.rxl2db <= Nanod.reg2dbl & !dblSpecial & nanoLatch[ NANO_RXL_DBL]; + Nanod.rxl2ab <= Nanod.reg2abl & !ablSpecial & !nanoLatch[ NANO_RXL_DBL]; + + Nanod.dbl2rxl <= Nanod.dbl2reg & !dblSpecial & nanoLatch[ NANO_RXL_DBL]; + Nanod.abl2rxl <= Nanod.abl2reg & !ablSpecial & !nanoLatch[ NANO_RXL_DBL]; + + Nanod.rxh2dbh <= Nanod.reg2dbh & !dbhSpecial & nanoLatch[ NANO_RXH_DBH]; + Nanod.rxh2abh <= Nanod.reg2abh & !abhSpecial & !nanoLatch[ NANO_RXH_DBH]; + + Nanod.dbh2rxh <= Nanod.dbh2reg & !dbhSpecial & nanoLatch[ NANO_RXH_DBH]; + Nanod.abh2rxh <= Nanod.abh2reg & !abhSpecial & !nanoLatch[ NANO_RXH_DBH]; + + Nanod.dbh2ryh <= Nanod.dbh2reg & !dbhSpecial & !nanoLatch[ NANO_RXH_DBH]; + Nanod.abh2ryh <= Nanod.abh2reg & !abhSpecial & nanoLatch[ NANO_RXH_DBH]; + + Nanod.dbl2ryl <= Nanod.dbl2reg & !dblSpecial & !nanoLatch[ NANO_RXL_DBL]; + Nanod.abl2ryl <= Nanod.abl2reg & !ablSpecial & nanoLatch[ NANO_RXL_DBL]; + + Nanod.ryl2db <= Nanod.reg2dbl & !dblSpecial & !nanoLatch[ NANO_RXL_DBL]; + Nanod.ryl2ab <= Nanod.reg2abl & !ablSpecial & nanoLatch[ NANO_RXL_DBL]; + + Nanod.ryh2dbh <= Nanod.reg2dbh & !dbhSpecial & !nanoLatch[ NANO_RXH_DBH]; + Nanod.ryh2abh <= Nanod.reg2abh & !abhSpecial & nanoLatch[ NANO_RXH_DBH]; + end + + // Originally isTas only delayed on T2 (and seems only a late mask rev fix) + // Better latch the combination on T4 + if( enT4) + Nanod.isRmc <= Irdecod.isTas & nanoLatch[ NANO_BUSBYTE]; + end + + +endmodule + +// +// IRD execution decoder. Complements nano code decoder +// +// IRD updated on T1, while ncode still executing. To avoid using the next IRD, +// decoded signals must be registered on T3, or T4 before using them. +// +module irdDecode( input [15:0] ird, + output s_irdecod Irdecod); + + wire [3:0] line = ird[15:12]; + logic [15:0] lineOnehot; + + // This can be registered and pipelined from the IR decoder ! + onehotEncoder4 irdLines( line, lineOnehot); + + wire isRegShift = (lineOnehot['he]) & (ird[7:6] != 2'b11); + wire isDynShift = isRegShift & ird[5]; + + assign Irdecod.isPcRel = (& ird[ 5:3]) & ~isDynShift & !ird[2] & ird[1]; + assign Irdecod.isTas = lineOnehot[4] & (ird[11:6] == 6'b101011); + + assign Irdecod.rx = ird[11:9]; + assign Irdecod.ry = ird[ 2:0]; + + wire isPreDecr = (ird[ 5:3] == 3'b100); + wire eaAreg = (ird[5:3] == 3'b001); + + // rx is A or D + // movem + always_comb begin + unique case( 1'b1) + lineOnehot[1], + lineOnehot[2], + lineOnehot[3]: + // MOVE: RX always Areg except if dest mode is Dn 000 + Irdecod.rxIsAreg = (| ird[8:6]); + + lineOnehot[4]: Irdecod.rxIsAreg = (& ird[8:6]); // not CHK (LEA) + + lineOnehot['h8]: Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7]; // SBCD + lineOnehot['hc]: Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7]; // ABCD/EXG An,An + + lineOnehot['h9], + lineOnehot['hb], + lineOnehot['hd]: Irdecod.rxIsAreg = + (ird[7] & ird[6]) | // SUBA/CMPA/ADDA + (eaAreg & ird[8] & (ird[7:6] != 2'b11)); // SUBX/CMPM/ADDX + default: + Irdecod.rxIsAreg = Irdecod.implicitSp; + endcase + end + + // RX is movem + always_comb begin + Irdecod.rxIsMovem = lineOnehot[4] & ~ird[8] & ~Irdecod.implicitSp; + end + assign Irdecod.movemPreDecr = Irdecod.rxIsMovem & isPreDecr; + + // RX is DT. + // but SSP explicit or pc explicit has higher priority! + // addq/subq (scc & dbcc also, but don't use rx) + // Immediate including static bit + assign Irdecod.rxIsDt = lineOnehot[5] | (lineOnehot[0] & ~ird[8]); + + // RX is USP + assign Irdecod.rxIsUsp = lineOnehot[4] & (ird[ 11:4] == 8'he6); + + // RY is DT + // rz or PC explicit has higher priority + + wire eaImmOrAbs = (ird[5:3] == 3'b111) & ~ird[1]; + assign Irdecod.ryIsDt = eaImmOrAbs & ~isRegShift; + + // RY is Address register + always_comb begin + logic eaIsAreg; + + // On most cases RY is Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL) + eaIsAreg = (ird[5:3] != 3'b000) & (ird[5:3] != 3'b111); + + unique case( 1'b1) + // MOVE: RY always Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL) + // Most lines, including misc line 4, also. + default: Irdecod.ryIsAreg = eaIsAreg; + + lineOnehot[5]: // DBcc is an exception + Irdecod.ryIsAreg = eaIsAreg & (ird[7:3] != 5'b11001); + + lineOnehot[6], + lineOnehot[7]: Irdecod.ryIsAreg = 1'b0; + + lineOnehot['he]: + Irdecod.ryIsAreg = ~isRegShift; + endcase + end + + // Byte sized instruction + + // Original implementation sets this for some instructions that aren't really byte size + // but doesn't matter because they don't have a byte transfer enabled at nanocode, such as MOVEQ + + wire xIsScc = (ird[7:6] == 2'b11) & (ird[5:3] != 3'b001); + wire xStaticMem = (ird[11:8] == 4'b1000) & (ird[5:4] == 2'b00); // Static bit to mem + always_comb begin + unique case( 1'b1) + lineOnehot[0]: + Irdecod.isByte = + ( ird[8] & (ird[5:4] != 2'b00) ) | // Dynamic bit to mem + ( (ird[11:8] == 4'b1000) & (ird[5:4] != 2'b00) ) | // Static bit to mem + ( (ird[8:7] == 2'b10) & (ird[5:3] == 3'b001) ) | // Movep from mem only! For byte mux + ( (ird[8:6] == 3'b000) & !xStaticMem ); // Immediate byte + + lineOnehot[1]: Irdecod.isByte = 1'b1; // MOVE.B + + + lineOnehot[4]: Irdecod.isByte = (ird[7:6] == 2'b00) | Irdecod.isTas; + lineOnehot[5]: Irdecod.isByte = (ird[7:6] == 2'b00) | xIsScc; + + lineOnehot[8], + lineOnehot[9], + lineOnehot['hb], + lineOnehot['hc], + lineOnehot['hd], + lineOnehot['he]: Irdecod.isByte = (ird[7:6] == 2'b00); + + default: Irdecod.isByte = 1'b0; + endcase + end + + // Need it for special byte size. Bus is byte, but whole register word is modified. + assign Irdecod.isMovep = lineOnehot[0] & ird[8] & eaAreg; + + + // rxIsSP implicit use of RX for actual SP transfer + // + // This logic is simple and will include some instructions that don't actually reference SP. + // But doesn't matter as long as they don't perform any RX transfer. + + always_comb begin + unique case( 1'b1) + lineOnehot[6]: Irdecod.implicitSp = (ird[11:8] == 4'b0001); // BSR + lineOnehot[4]: + // Misc like RTS, JSR, etc + Irdecod.implicitSp = (ird[11:8] == 4'b1110) | (ird[11:6] == 6'b1000_01); + default: Irdecod.implicitSp = 1'b0; + endcase + end + + // Modify CCR (and not SR) + // Probably overkill !! Only needs to distinguish SR vs CCR + // RTR, MOVE to CCR, xxxI to CCR + assign Irdecod.toCcr = ( lineOnehot[4] & ((ird[11:0] == 12'he77) | (ird[11:6] == 6'b010011)) ) | + ( lineOnehot[0] & (ird[8:6] == 3'b000)); + + // FTU constants + // This should not be latched on T3/T4. Latch on T2 or not at all. FTU needs it on next T3. + // Note: Reset instruction gets constant from ALU not from FTU! + logic [15:0] ftuConst; + wire [3:0] zero28 = (ird[11:9] == 0) ? 4'h8 : { 1'b0, ird[11:9]}; // xltate 0,1-7 into 8,1-7 + + always_comb begin + unique case( 1'b1) + lineOnehot[6], // Bcc short + lineOnehot[7]: ftuConst = { { 8{ ird[ 7]}}, ird[ 7:0] }; // MOVEQ + + lineOnehot['h5], // addq/subq/static shift double check this + lineOnehot['he]: ftuConst = { 12'b0, zero28}; + + // MULU/MULS DIVU/DIVS + lineOnehot['h8], + lineOnehot['hc]: ftuConst = 16'h0f; + + lineOnehot[4]: ftuConst = 16'h80; // TAS + + default: ftuConst = '0; + endcase + end + assign Irdecod.ftuConst = ftuConst; + + // + // TRAP Vector # for group 2 exceptions + // + + always_comb begin + if( lineOnehot[4]) begin + case ( ird[6:5]) + 2'b00,2'b01: Irdecod.macroTvn = 6; // CHK + 2'b11: Irdecod.macroTvn = 7; // TRAPV + 2'b10: Irdecod.macroTvn = {2'b10, ird[3:0]}; // TRAP + endcase + end + else + Irdecod.macroTvn = 5; // Division by zero + end + + + wire eaAdir = (ird[ 5:3] == 3'b001); + wire size11 = ird[7] & ird[6]; + + // Opcodes variants that don't affect flags + // ADDA/SUBA ADDQ/SUBQ MOVEA + + assign Irdecod.inhibitCcr = + ( (lineOnehot[9] | lineOnehot['hd]) & size11) | // ADDA/SUBA + ( lineOnehot[5] & eaAdir) | // ADDQ/SUBQ to An (originally checks for line[4] as well !?) + ( (lineOnehot[2] | lineOnehot[3]) & ird[8:6] == 3'b001); // MOVEA + +endmodule + +/* + Execution unit + + Executes register transfers set by the microcode. Originally through a set of bidirectional buses. + Most sources are available at T3, but DBIN only at T4! CCR also might be updated at T4, but it is not connected to these buses. + We mux at T1 and T2, then transfer to the destination at T3. The exception is AOB that need to be updated earlier. + +*/ + +module excUnit( input s_clks Clks, + input enT1, enT2, enT3, enT4, + input s_nanod Nanod, input s_irdecod Irdecod, + input [15:0] Ird, // ALU row (and others) decoder needs it + input pswS, + input [15:0] ftu, + input [15:0] iEdb, + + output logic [7:0] ccr, + output [15:0] alue, + + output prenEmpty, au05z, + output logic dcr4, ze, + output logic aob0, + output [15:0] AblOut, + output logic [15:0] Irc, + output logic [15:0] oEdb, + output logic [23:1] eab); + +localparam REG_USP = 15; +localparam REG_SSP = 16; +localparam REG_DT = 17; + + // Register file + reg [15:0] regs68L[ 18]; + reg [15:0] regs68H[ 18]; + +// synthesis translate off + /* + It is bad practice to initialize simulation registers that the hardware doesn't. + There is risk that simulation would be different than the real hardware. But in this case is the other way around. + Some ROM uses something like sub.l An,An at powerup which clears the register + Simulator power ups the registers with 'X, as they are really undetermined at the real hardware. + But the simulator doesn't realize (it can't) that the same value is substracting from itself, + and that the result should be zero even when it's 'X - 'X. + */ + + initial begin + for( int i = 0; i < 18; i++) begin + regs68L[i] <= '0; + regs68H[i] <= '0; + end + end + + // For simulation display only + wire [31:0] SSP = { regs68H[REG_SSP], regs68L[REG_SSP]}; + +// synthesis translate on + + + wire [15:0] aluOut; + wire [15:0] dbin; + logic [15:0] dcrOutput; + + reg [15:0] PcL, PcH; + + reg [31:0] auReg, aob; + + reg [15:0] Ath, Atl; + + // Bus execution + reg [15:0] Dbl, Dbh; + reg [15:0] Abh, Abl; + reg [15:0] Abd, Dbd; + + assign AblOut = Abl; + assign au05z = (~| auReg[5:0]); + + logic [15:0] dblMux, dbhMux; + logic [15:0] abhMux, ablMux; + logic [15:0] abdMux, dbdMux; + + logic abdIsByte; + + logic Pcl2Dbl, Pch2Dbh; + logic Pcl2Abl, Pch2Abh; + + + // RX RY muxes + // RX and RY actual registers + logic [4:0] actualRx, actualRy; + logic [3:0] movemRx; + logic byteNotSpAlign; // Byte instruction and no sp word align + + // IRD decoded signals must be latched. See comments on decoder + // But nanostore decoding can't be latched before T4. + // + // If we need this earlier we can register IRD decode on T3 and use nano async + + logic [4:0] rxMux, ryMux; + logic [3:0] rxReg, ryReg; + logic rxIsSp, ryIsSp; + logic rxIsAreg, ryIsAreg; + + always_comb begin + + // Unique IF !! + if( Nanod.ssp) begin + rxMux = REG_SSP; + rxIsSp = 1'b1; + rxReg = 1'bX; + end + else if( Irdecod.rxIsUsp) begin + rxMux = REG_USP; + rxIsSp = 1'b1; + rxReg = 1'bX; + end + else if( Irdecod.rxIsDt & !Irdecod.implicitSp) begin + rxMux = REG_DT; + rxIsSp = 1'b0; + rxReg = 1'bX; + end + else begin + if( Irdecod.implicitSp) + rxReg = 15; + else if( Irdecod.rxIsMovem) + rxReg = movemRx; + else + rxReg = { Irdecod.rxIsAreg, Irdecod.rx}; + + if( (& rxReg)) begin + rxMux = pswS ? REG_SSP : 15; + rxIsSp = 1'b1; + end + else begin + rxMux = { 1'b0, rxReg}; + rxIsSp = 1'b0; + end + end + + // RZ has higher priority! + if( Irdecod.ryIsDt & !Nanod.rz) begin + ryMux = REG_DT; + ryIsSp = 1'b0; + ryReg = 'X; + end + else begin + ryReg = Nanod.rz ? Irc[15:12] : {Irdecod.ryIsAreg, Irdecod.ry}; + ryIsSp = (& ryReg); + if( ryIsSp & pswS) // No implicit SP on RY + ryMux = REG_SSP; + else + ryMux = { 1'b0, ryReg}; + end + + end + + always_ff @( posedge Clks.clk) begin + if( enT4) begin + byteNotSpAlign <= Irdecod.isByte & ~(Nanod.rxlDbl ? rxIsSp : ryIsSp); + + actualRx <= rxMux; + actualRy <= ryMux; + + rxIsAreg <= rxIsSp | rxMux[3]; + ryIsAreg <= ryIsSp | ryMux[3]; + end + + if( enT4) + abdIsByte <= Nanod.abdIsByte & Irdecod.isByte; + end + + // Set RX/RY low word to which bus segment is connected. + + wire ryl2Abl = Nanod.ryl2ab & (ryIsAreg | Nanod.ablAbd); + wire ryl2Abd = Nanod.ryl2ab & (~ryIsAreg | Nanod.ablAbd); + wire ryl2Dbl = Nanod.ryl2db & (ryIsAreg | Nanod.dblDbd); + wire ryl2Dbd = Nanod.ryl2db & (~ryIsAreg | Nanod.dblDbd); + + wire rxl2Abl = Nanod.rxl2ab & (rxIsAreg | Nanod.ablAbd); + wire rxl2Abd = Nanod.rxl2ab & (~rxIsAreg | Nanod.ablAbd); + wire rxl2Dbl = Nanod.rxl2db & (rxIsAreg | Nanod.dblDbd); + wire rxl2Dbd = Nanod.rxl2db & (~rxIsAreg | Nanod.dblDbd); + + // Buses. Main mux + + logic abhIdle, ablIdle, abdIdle; + logic dbhIdle, dblIdle, dbdIdle; + + always_comb begin + {abhIdle, ablIdle, abdIdle} = '0; + {dbhIdle, dblIdle, dbdIdle} = '0; + + unique case( 1'b1) + ryl2Dbd: dbdMux = regs68L[ actualRy]; + rxl2Dbd: dbdMux = regs68L[ actualRx]; + Nanod.alue2Dbd: dbdMux = alue; + Nanod.dbin2Dbd: dbdMux = dbin; + Nanod.alu2Dbd: dbdMux = aluOut; + Nanod.dcr2Dbd: dbdMux = dcrOutput; + default: begin dbdMux = 'X; dbdIdle = 1'b1; end + endcase + + unique case( 1'b1) + rxl2Dbl: dblMux = regs68L[ actualRx]; + ryl2Dbl: dblMux = regs68L[ actualRy]; + Nanod.ftu2Dbl: dblMux = ftu; + Nanod.au2Db: dblMux = auReg[15:0]; + Nanod.atl2Dbl: dblMux = Atl; + Pcl2Dbl: dblMux = PcL; + default: begin dblMux = 'X; dblIdle = 1'b1; end + endcase + + unique case( 1'b1) + Nanod.rxh2dbh: dbhMux = regs68H[ actualRx]; + Nanod.ryh2dbh: dbhMux = regs68H[ actualRy]; + Nanod.au2Db: dbhMux = auReg[31:16]; + Nanod.ath2Dbh: dbhMux = Ath; + Pch2Dbh: dbhMux = PcH; + default: begin dbhMux = 'X; dbhIdle = 1'b1; end + endcase + + unique case( 1'b1) + ryl2Abd: abdMux = regs68L[ actualRy]; + rxl2Abd: abdMux = regs68L[ actualRx]; + Nanod.dbin2Abd: abdMux = dbin; + Nanod.alu2Abd: abdMux = aluOut; + default: begin abdMux = 'X; abdIdle = 1'b1; end + endcase + + unique case( 1'b1) + Pcl2Abl: ablMux = PcL; + rxl2Abl: ablMux = regs68L[ actualRx]; + ryl2Abl: ablMux = regs68L[ actualRy]; + Nanod.ftu2Abl: ablMux = ftu; + Nanod.au2Ab: ablMux = auReg[15:0]; + Nanod.aob2Ab: ablMux = aob[15:0]; + Nanod.atl2Abl: ablMux = Atl; + default: begin ablMux = 'X; ablIdle = 1'b1; end + endcase + + unique case( 1'b1) + Pch2Abh: abhMux = PcH; + Nanod.rxh2abh: abhMux = regs68H[ actualRx]; + Nanod.ryh2abh: abhMux = regs68H[ actualRy]; + Nanod.au2Ab: abhMux = auReg[31:16]; + Nanod.aob2Ab: abhMux = aob[31:16]; + Nanod.ath2Abh: abhMux = Ath; + default: begin abhMux = 'X; abhIdle = 1'b1; end + endcase + + end + + // Source starts driving the bus on T1. Bus holds data until end of T3. Destination latches at T3. + + // These registers store the first level mux, without bus interconnections. + // Even when this uses almost to 100 registers, it saves a lot of comb muxing and it is much faster. + reg [15:0] preAbh, preAbl, preAbd; + reg [15:0] preDbh, preDbl, preDbd; + + always_ff @( posedge Clks.clk) begin + + // Register first level mux at T1 + if( enT1) begin + {preAbh, preAbl, preAbd} <= { abhMux, ablMux, abdMux}; + {preDbh, preDbl, preDbd} <= { dbhMux, dblMux, dbdMux}; + end + + // Process bus interconnection at T2. Many combinations only used on DIV + // We use a simple method. If a specific bus segment is not driven we know that it should get data from a neighbour segment. + // In some cases this is not true and the segment is really idle without any destination. But then it doesn't matter. + + if( enT2) begin + if( Nanod.extAbh) + Abh <= { 16{ ablIdle ? preAbd[ 15] : preAbl[ 15] }}; + else if( abhIdle) + Abh <= ablIdle ? preAbd : preAbl; + else + Abh <= preAbh; + + if( ~ablIdle) + Abl <= preAbl; + else + Abl <= Nanod.ablAbh ? preAbh : preAbd; + + Abd <= ~abdIdle ? preAbd : ablIdle ? preAbh : preAbl; + + if( Nanod.extDbh) + Dbh <= { 16{ dblIdle ? preDbd[ 15] : preDbl[ 15] }}; + else if( dbhIdle) + Dbh <= dblIdle ? preDbd : preDbl; + else + Dbh <= preDbh; + + if( ~dblIdle) + Dbl <= preDbl; + else + Dbl <= Nanod.dblDbh ? preDbh : preDbd; + + Dbd <= ~dbdIdle ? preDbd: dblIdle ? preDbh : preDbl; + + /* + Dbl <= dblMux; Dbh <= dbhMux; + Abd <= abdMux; Dbd <= dbdMux; + Abh <= abhMux; Abl <= ablMux; */ + end + end + + // AOB + // + // Originally change on T1. We do on T2, only then the output is enabled anyway. + // + // AOB[0] is used for address error. But even when raises on T1, seems not actually used until T2 or possibly T3. + // It is used on T1 when deasserted at the BSER exception ucode. Probably deassertion timing is not critical. + // But in that case (at BSER), AOB is loaded from AU, so we can safely transfer on T1. + + // We need to take directly from first level muxes that are updated and T1 + + wire au2Aob = Nanod.au2Aob | (Nanod.au2Db & Nanod.db2Aob); + + always_ff @( posedge Clks.clk) begin + // UNIQUE IF ! + + if( enT1 & au2Aob) // From AU we do can on T1 + aob <= auReg; + else if( enT2) begin + if( Nanod.db2Aob) + aob <= { preDbh, ~dblIdle ? preDbl : preDbd}; + else if( Nanod.ab2Aob) + aob <= { preAbh, ~ablIdle ? preAbl : preAbd}; + end + end + + assign eab = aob[23:1]; + assign aob0 = aob[0]; + + // AU + logic [31:0] auInpMux; + + // `ifdef ALW_COMB_BUG + // Old Modelsim bug. Doesn't update ouput always. Need excplicit sensitivity list !? + // always @( Nanod.auCntrl) begin + + always_comb begin + unique case( Nanod.auCntrl) + 3'b000: auInpMux = 0; + 3'b001: auInpMux = byteNotSpAlign | Nanod.noSpAlign ? 1 : 2; // +1/+2 + 3'b010: auInpMux = -4; + 3'b011: auInpMux = { Abh, Abl}; + 3'b100: auInpMux = 2; + 3'b101: auInpMux = 4; + 3'b110: auInpMux = -2; + 3'b111: auInpMux = byteNotSpAlign | Nanod.noSpAlign ? -1 : -2; // -1/-2 + default: auInpMux = 'X; + endcase + end + + // Simulation problem + // Sometimes (like in MULM1) DBH is not set. AU is used in these cases just as a 6 bits counter testing if bits 5-0 are zero. + // But when adding something like 32'hXXXX0000, the simulator (incorrectly) will set *all the 32 bits* of the result as X. + +// synthesis translate_off + `define SIMULBUGX32 1 + wire [16:0] aulow = Dbl + auInpMux[15:0]; + wire [31:0] auResult = {Dbh + auInpMux[31:16] + aulow[16], aulow[15:0]}; +// synthesis translate_on + + always_ff @( posedge Clks.clk) begin + if( Clks.pwrUp) + auReg <= '0; + else if( enT3 & Nanod.auClkEn) + `ifdef SIMULBUGX32 + auReg <= auResult; + `else + auReg <= { Dbh, Dbl } + auInpMux; + `endif + end + + + // Main A/D registers + + always_ff @( posedge Clks.clk) begin + if( enT3) begin + if( Nanod.dbl2rxl | Nanod.abl2rxl) begin + if( ~rxIsAreg) begin + if( Nanod.dbl2rxl) regs68L[ actualRx] <= Dbd; + else if( abdIsByte) regs68L[ actualRx][7:0] <= Abd[7:0]; + else regs68L[ actualRx] <= Abd; + end + else + regs68L[ actualRx] <= Nanod.dbl2rxl ? Dbl : Abl; + end + + if( Nanod.dbl2ryl | Nanod.abl2ryl) begin + if( ~ryIsAreg) begin + if( Nanod.dbl2ryl) regs68L[ actualRy] <= Dbd; + else if( abdIsByte) regs68L[ actualRy][7:0] <= Abd[7:0]; + else regs68L[ actualRy] <= Abd; + end + else + regs68L[ actualRy] <= Nanod.dbl2ryl ? Dbl : Abl; + end + + // High registers are easier. Both A & D on the same buses, and not byte ops. + if( Nanod.dbh2rxh | Nanod.abh2rxh) + regs68H[ actualRx] <= Nanod.dbh2rxh ? Dbh : Abh; + if( Nanod.dbh2ryh | Nanod.abh2ryh) + regs68H[ actualRy] <= Nanod.dbh2ryh ? Dbh : Abh; + + end + end + + // PC & AT + reg dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl; + + always_ff @( posedge Clks.clk) begin + if( Clks.extReset) begin + { dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl } <= '0; + + Pcl2Dbl <= 1'b0; + Pch2Dbh <= 1'b0; + Pcl2Abl <= 1'b0; + Pch2Abh <= 1'b0; + end + else if( enT4) begin // Must latch on T4 ! + dbl2Pcl <= Nanod.dbl2reg & Nanod.pcldbl; + dbh2Pch <= Nanod.dbh2reg & Nanod.pchdbh; + abh2Pch <= Nanod.abh2reg & Nanod.pchabh; + abl2Pcl <= Nanod.abl2reg & Nanod.pclabl; + + Pcl2Dbl <= Nanod.reg2dbl & Nanod.pcldbl; + Pch2Dbh <= Nanod.reg2dbh & Nanod.pchdbh; + Pcl2Abl <= Nanod.reg2abl & Nanod.pclabl; + Pch2Abh <= Nanod.reg2abh & Nanod.pchabh; + end + + // Unique IF !!! + if( enT1 & Nanod.au2Pc) + PcL <= auReg[15:0]; + else if( enT3) begin + if( dbl2Pcl) + PcL <= Dbl; + else if( abl2Pcl) + PcL <= Abl; + end + + // Unique IF !!! + if( enT1 & Nanod.au2Pc) + PcH <= auReg[31:16]; + else if( enT3) begin + if( dbh2Pch) + PcH <= Dbh; + else if( abh2Pch) + PcH <= Abh; + end + + // Unique IF !!! + if( enT3) begin + if( Nanod.dbl2Atl) + Atl <= Dbl; + else if( Nanod.abl2Atl) + Atl <= Abl; + end + + // Unique IF !!! + if( enT3) begin + if( Nanod.abh2Ath) + Ath <= Abh; + else if( Nanod.dbh2Ath) + Ath <= Dbh; + end + + end + + // Movem reg mask priority encoder + + wire rmIdle; + logic [3:0] prHbit; + logic [15:0] prenLatch; + + // Invert reg order for predecrement mode + assign prenEmpty = (~| prenLatch); + pren rmPren( .mask( prenLatch), .hbit (prHbit)); + + always_ff @( posedge Clks.clk) begin + // Cheating: PREN always loaded from DBIN + // Must be on T1 to branch earlier if reg mask is empty! + if( enT1 & Nanod.abl2Pren) + prenLatch <= dbin; + else if( enT3 & Nanod.updPren) begin + prenLatch [prHbit] <= 1'b0; + movemRx <= Irdecod.movemPreDecr ? ~prHbit : prHbit; + end + end + + // DCR + wire [15:0] dcrCode; + + wire [3:0] dcrInput = abdIsByte ? { 1'b0, Abd[ 2:0]} : Abd[ 3:0]; + onehotEncoder4 dcrDecoder( .bin( dcrInput), .bitMap( dcrCode)); + + always_ff @( posedge Clks.clk) begin + if( Clks.pwrUp) + dcr4 <= '0; + else if( enT3 & Nanod.abd2Dcr) begin + dcrOutput <= dcrCode; + dcr4 <= Abd[4]; + end + end + + // ALUB + reg [15:0] alub; + + always_ff @( posedge Clks.clk) begin + if( enT3) begin + // UNIQUE IF !! + if( Nanod.dbd2Alub) + alub <= Dbd; + else if( Nanod.abd2Alub) + alub <= Abd; // abdIsByte affects this !!?? + end + end + + wire alueClkEn = enT3 & Nanod.dbd2Alue; + + // DOB/DBIN/IRC + + logic [15:0] dobInput; + wire dobIdle = (~| Nanod.dobCtrl); + + always_comb begin + unique case (Nanod.dobCtrl) + NANO_DOB_ADB: dobInput = Abd; + NANO_DOB_DBD: dobInput = Dbd; + NANO_DOB_ALU: dobInput = aluOut; + default: dobInput = 'X; + endcase + end + + dataIo dataIo( .Clks, .enT1, .enT2, .enT3, .enT4, .Nanod, .Irdecod, + .iEdb, .dobIdle, .dobInput, .aob0, + .Irc, .dbin, .oEdb); + + fx68kAlu alu( + .clk( Clks.clk), .pwrUp( Clks.pwrUp), .enT1, .enT3, .enT4, + .ird( Ird), + .aluColumn( Nanod.aluColumn), .aluAddrCtrl( Nanod.aluActrl), + .init( Nanod.aluInit), .finish( Nanod.aluFinish), .aluIsByte( Irdecod.isByte), + .ftu2Ccr( Nanod.ftu2Ccr), + .alub, .ftu, .alueClkEn, .alue, + .aluDataCtrl( Nanod.aluDctrl), .iDataBus( Dbd), .iAddrBus(Abd), + .ze, .aluOut, .ccr); + +endmodule + +// +// Data bus I/O +// At a separate module because it is a bit complicated and the timing is special. +// Here we do the low/high byte mux and the special case of MOVEP. +// +// Original implementation is rather complex because both the internal and external buses are bidirectional. +// Input is latched async at the EDB register. +// We capture directly from the external data bus to the internal registers (IRC & DBIN) on PHI2, starting the external S7 phase, at a T4 internal period. + +module dataIo( input s_clks Clks, + input enT1, enT2, enT3, enT4, + input s_nanod Nanod, input s_irdecod Irdecod, + input [15:0] iEdb, + input aob0, + + input dobIdle, + input [15:0] dobInput, + + output logic [15:0] Irc, + output logic [15:0] dbin, + output logic [15:0] oEdb + ); + + reg [15:0] dob; + + // DBIN/IRC + + // Timing is different than any other register. We can latch only on the next T4 (bus phase S7). + // We need to register all control signals correctly because the next ublock will already be started. + // Can't latch control on T4 because if there are wait states there might be multiple T4 before we latch. + + reg xToDbin, xToIrc; + reg dbinNoLow, dbinNoHigh; + reg byteMux, isByte_T4; + + always_ff @( posedge Clks.clk) begin + + // Byte mux control. Can't latch at T1. AOB might be not ready yet. + // Must latch IRD decode at T1 (or T4). Then combine and latch only at T3. + + // Can't latch at T3, a new IRD might be loaded already at T1. + // Ok to latch at T4 if combination latched then at T3 + if( enT4) + isByte_T4 <= Irdecod.isByte; // Includes MOVEP from mem, we could OR it here + + if( enT3) begin + dbinNoHigh <= Nanod.noHighByte; + dbinNoLow <= Nanod.noLowByte; + byteMux <= Nanod.busByte & isByte_T4 & ~aob0; + end + + if( enT1) begin + // If on wait states, we continue latching until next T1 + xToDbin <= 1'b0; + xToIrc <= 1'b0; + end + else if( enT3) begin + xToDbin <= Nanod.todbin; + xToIrc <= Nanod.toIrc; + end + + // Capture on T4 of the next ucycle + // If there are wait states, we keep capturing every PHI2 until the next T1 + + if( xToIrc & Clks.enPhi2) + Irc <= iEdb; + if( xToDbin & Clks.enPhi2) begin + // Original connects both halves of EDB. + if( ~dbinNoLow) + dbin[ 7:0] <= byteMux ? iEdb[ 15:8] : iEdb[7:0]; + if( ~dbinNoHigh) + dbin[ 15:8] <= ~byteMux & dbinNoLow ? iEdb[ 7:0] : iEdb[ 15:8]; + end + end + + // DOB + logic byteCycle; + + always_ff @( posedge Clks.clk) begin + // Originaly on T1. Transfer to internal EDB also on T1 (stays enabled upto the next T1). But only on T4 (S3) output enables. + // It is safe to do on T3, then, but control signals if derived from IRD must be registered. + // Originally control signals are not registered. + + // Wait states don't affect DOB operation that is done at the start of the bus cycle. + + if( enT4) + byteCycle <= Nanod.busByte & Irdecod.isByte; // busIsByte but not MOVEP + + // Originally byte low/high interconnect is done at EDB, not at DOB. + if( enT3 & ~dobIdle) begin + dob[7:0] <= Nanod.noLowByte ? dobInput[15:8] : dobInput[ 7:0]; + dob[15:8] <= (byteCycle | Nanod.noHighByte) ? dobInput[ 7:0] : dobInput[15:8]; + end + end + assign oEdb = dob; + +endmodule + + +// Provides ucode routine entries (A1/A3) for each opcode +// Also checks for illegal opcode and priv violation + +// This is one of the slowest part of the processor. +// But no need to optimize or pipeline because the result for a1-a3 is not needed until at least 4 cycles. +// IR updated at the least one microinstruction earlier. +// Just need to configure the timing analizer correctly. +// isPriv, isIllegal might be needed as soon as two cycles later + + +module uaddrDecode( + input [15:0] opcode, + output [UADDR_WIDTH-1:0] a1, a2, a3, + output logic isPriv, isIllegal, isLineA, isLineF, + output [15:0] lineBmap); + + wire [3:0] line = opcode[15:12]; + logic [3:0] eaCol, movEa; + + onehotEncoder4 irLineDecod( line, lineBmap); + + assign isLineA = lineBmap[ 'hA]; + assign isLineF = lineBmap[ 'hF]; + + pla_lined pla_lined( .movEa( movEa), .col( eaCol), + .opcode( opcode), .lineBmap( lineBmap), + .palIll( isIllegal), .plaA1( a1), .plaA2( a2), .plaA3( a3) ); + + // ea decoding + assign eaCol = eaDecode( opcode[ 5:0]); + assign movEa = eaDecode( {opcode[ 8:6], opcode[ 11:9]} ); + + // EA decode + function [3:0] eaDecode; + input [5:0] eaBits; + begin + unique case( eaBits[ 5:3]) + 3'b111: + case( eaBits[ 2:0]) + 3'b000: eaDecode = 7; // Absolute short + 3'b001: eaDecode = 8; // Absolute long + 3'b010: eaDecode = 9; // PC displacement + 3'b011: eaDecode = 10; // PC offset + 3'b100: eaDecode = 11; // Immediate + default: eaDecode = 12; // Invalid + endcase + + default: eaDecode = eaBits[5:3]; // Register based EAs + endcase + end + endfunction + + + /* + Privileged instructions: + + ANDI/EORI/ORI SR + MOVE to SR + MOVE to/from USP + RESET + RTE + STOP + */ + + always_comb begin + unique case( lineBmap) + + // ori/andi/eori SR + 'h01: isPriv = ((opcode & 16'hf5ff) == 16'h007c); + + 'h10: + begin + // No priority !!! + if( (opcode & 16'hffc0) == 16'h46c0) // move to sr + isPriv = 1'b1; + + else if( (opcode & 16'hfff0) == 16'h4e60) // move usp + isPriv = 1'b1; + + else if( opcode == 16'h4e70 || // reset + opcode == 16'h4e73 || // rte + opcode == 16'h4e72) // stop + isPriv = 1'b1; + else + isPriv = 1'b0; + end + + default: isPriv = 1'b0; + endcase + end + + +endmodule + +// bin to one-hot, 4 bits to 16-bit bitmap +module onehotEncoder4( input [3:0] bin, output reg [15:0] bitMap); + always_comb begin + case( bin) + 'b0000: bitMap = 16'h0001; + 'b0001: bitMap = 16'h0002; + 'b0010: bitMap = 16'h0004; + 'b0011: bitMap = 16'h0008; + 'b0100: bitMap = 16'h0010; + 'b0101: bitMap = 16'h0020; + 'b0110: bitMap = 16'h0040; + 'b0111: bitMap = 16'h0080; + 'b1000: bitMap = 16'h0100; + 'b1001: bitMap = 16'h0200; + 'b1010: bitMap = 16'h0400; + 'b1011: bitMap = 16'h0800; + 'b1100: bitMap = 16'h1000; + 'b1101: bitMap = 16'h2000; + 'b1110: bitMap = 16'h4000; + 'b1111: bitMap = 16'h8000; + endcase + end +endmodule + +// priority encoder +// used by MOVEM regmask +// this might benefit from device specific features +// MOVEM doesn't need speed, will read the result 2 CPU cycles after each update. +module pren( mask, hbit); + parameter size = 16; + parameter outbits = 4; + + input [size-1:0] mask; + output reg [outbits-1:0] hbit; + // output reg idle; + + always @( mask) begin + integer i; + hbit = 0; + // idle = 1; + for( i = size-1; i >= 0; i = i - 1) begin + if( mask[ i]) begin + hbit = i; + // idle = 0; + end + end + end + +endmodule + +// Microcode sequencer + +module sequencer( input s_clks Clks, input enT3, + input [UROM_WIDTH-1:0] microLatch, + input A0Err, BerrA, busAddrErr, Spuria, Avia, + input Tpend, intPend, isIllegal, isPriv, excRst, isLineA, isLineF, + input [15:0] psw, + input prenEmpty, au05z, dcr4, ze, i11, + input [1:0] alue01, + input [15:0] Ird, + input [UADDR_WIDTH-1:0] a1, a2, a3, + output logic [3:0] tvn, + output logic [UADDR_WIDTH-1:0] nma); + + logic [UADDR_WIDTH-1:0] uNma; + logic [UADDR_WIDTH-1:0] grp1Nma; + logic [1:0] c0c1; + reg a0Rst; + wire A0Sel; + wire inGrp0Exc; + + // assign nma = Clks.extReset ? RSTP0_NMA : (A0Err ? BSER1_NMA : uNma); + // assign nma = A0Err ? (a0Rst ? RSTP0_NMA : BSER1_NMA) : uNma; + + // word type I: 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 + // NMA : .. .. 09 08 01 00 05 04 03 02 07 06 .. .. .. .. .. + + wire [UADDR_WIDTH-1:0] dbNma = { microLatch[ 14:13], microLatch[ 6:5], microLatch[ 10:7], microLatch[ 12:11]}; + + // Group 0 exception. + // Separated block from regular NMA. Otherwise simulation might depend on order of assigments. + always_comb begin + if( A0Err) begin + if( a0Rst) // Reset + nma = RSTP0_NMA; + else if( inGrp0Exc) // Double fault + nma = HALT1_NMA; + else // Bus or address error + nma = BSER1_NMA; + end + else + nma = uNma; + end + + always_comb begin + // Format II (conditional) or I (direct branch) + if( microLatch[1]) + uNma = { microLatch[ 14:13], c0c1, microLatch[ 10:7], microLatch[ 12:11]}; + else + case( microLatch[ 3:2]) + 0: uNma = dbNma; // DB + 1: uNma = A0Sel ? grp1Nma : a1; + 2: uNma = a2; + 3: uNma = a3; + endcase + end + + // Format II, conditional, NMA decoding + wire [1:0] enl = { Ird[6], prenEmpty}; // Updated on T3 + + wire [1:0] ms0 = { Ird[8], alue01[0]}; + wire [3:0] m01 = { au05z, Ird[8], alue01}; + wire [1:0] nz1 = { psw[ NF], psw[ ZF]}; + wire [1:0] nv = { psw[ NF], psw[ VF]}; + + logic ccTest; + wire [4:0] cbc = microLatch[ 6:2]; // CBC bits + + always_comb begin + unique case( cbc) + 'h0: c0c1 = {i11, i11}; // W/L offset EA, from IRC + + 'h1: c0c1 = (au05z) ? 2'b01 : 2'b11; // Updated on T3 + 'h11: c0c1 = (au05z) ? 2'b00 : 2'b11; + + 'h02: c0c1 = { 1'b0, ~psw[ CF]}; // C used in DIV + 'h12: c0c1 = { 1'b1, ~psw[ CF]}; + + 'h03: c0c1 = {psw[ ZF], psw[ ZF]}; // Z used in DIVU + + 'h04: // nz1, used in DIVS + case( nz1) + 'b00: c0c1 = 2'b10; + 'b10: c0c1 = 2'b01; + 'b01,'b11: c0c1 = 2'b11; + endcase + + 'h05: c0c1 = {psw[ NF], 1'b1}; // N used in CHK and DIV + 'h15: c0c1 = {1'b1, psw[ NF]}; + + // nz2, used in DIVS (same combination as nz1) + 'h06: c0c1 = { ~nz1[1] & ~nz1[0], 1'b1}; + + 'h07: // ms0 used in MUL + case( ms0) + 'b10, 'b00: c0c1 = 2'b11; + 'b01: c0c1 = 2'b01; + 'b11: c0c1 = 2'b10; + endcase + + 'h08: // m01 used in MUL + case( m01) + 'b0000,'b0001,'b0100,'b0111: c0c1 = 2'b11; + 'b0010,'b0011,'b0101: c0c1 = 2'b01; + 'b0110: c0c1 = 2'b10; + default: c0c1 = 2'b00; + endcase + + // Conditional + 'h09: c0c1 = (ccTest) ? 2'b11 : 2'b01; + 'h19: c0c1 = (ccTest) ? 2'b11 : 2'b10; + + // DCR bit 4 (high or low word) + 'h0c: c0c1 = dcr4 ? 2'b01: 2'b11; + 'h1c: c0c1 = dcr4 ? 2'b10: 2'b11; + + // DBcc done + 'h0a: c0c1 = ze ? 2'b11 : 2'b00; + + // nv, used in CHK + 'h0b: c0c1 = (nv == 2'b00) ? 2'b00 : 2'b11; + + // V, used in trapv + 'h0d: c0c1 = { ~psw[ VF], ~psw[VF]}; + + // enl, combination of pren idle and word/long on IRD + 'h0e,'h1e: + case( enl) + 2'b00: c0c1 = 'b10; + 2'b10: c0c1 = 'b11; + // 'hx1 result 00/01 depending on condition 0e/1e + 2'b01,2'b11: + c0c1 = { 1'b0, microLatch[ 6]}; + endcase + + default: c0c1 = 'X; + endcase + end + + // CCR conditional + always_comb begin + unique case( Ird[ 11:8]) + 'h0: ccTest = 1'b1; // T + 'h1: ccTest = 1'b0; // F + 'h2: ccTest = ~psw[ CF] & ~psw[ ZF]; // HI + 'h3: ccTest = psw[ CF] | psw[ZF]; // LS + 'h4: ccTest = ~psw[ CF]; // CC (HS) + 'h5: ccTest = psw[ CF]; // CS (LO) + 'h6: ccTest = ~psw[ ZF]; // NE + 'h7: ccTest = psw[ ZF]; // EQ + 'h8: ccTest = ~psw[ VF]; // VC + 'h9: ccTest = psw[ VF]; // VS + 'ha: ccTest = ~psw[ NF]; // PL + 'hb: ccTest = psw[ NF]; // MI + 'hc: ccTest = (psw[ NF] & psw[ VF]) | (~psw[ NF] & ~psw[ VF]); // GE + 'hd: ccTest = (psw[ NF] & ~psw[ VF]) | (~psw[ NF] & psw[ VF]); // LT + 'he: ccTest = (psw[ NF] & psw[ VF] & ~psw[ ZF]) | + (~psw[ NF] & ~psw[ VF] & ~psw[ ZF]); // GT + 'hf: ccTest = psw[ ZF] | (psw[ NF] & ~psw[VF]) | (~psw[ NF] & psw[VF]); // LE + endcase + end + + // Exception logic + logic rTrace, rInterrupt; + logic rIllegal, rPriv, rLineA, rLineF; + logic rExcRst, rExcAdrErr, rExcBusErr; + logic rSpurious, rAutovec; + wire grp1LatchEn, grp0LatchEn; + + // Originally control signals latched on T4. Then exception latches updated on T3 + assign grp1LatchEn = microLatch[0] & (microLatch[1] | !microLatch[4]); + assign grp0LatchEn = microLatch[4] & !microLatch[1]; + + assign inGrp0Exc = rExcRst | rExcBusErr | rExcAdrErr; + + always_ff @( posedge Clks.clk) begin + if( grp0LatchEn & enT3) begin + rExcRst <= excRst; + rExcBusErr <= BerrA; + rExcAdrErr <= busAddrErr; + rSpurious <= Spuria; + rAutovec <= Avia; + end + + // Update group 1 exception latches + // Inputs from IR decoder updated on T1 as soon as IR loaded + // Trace pending updated on T3 at the start of the instruction + // Interrupt pending on T2 + if( grp1LatchEn & enT3) begin + rTrace <= Tpend; + rInterrupt <= intPend; + rIllegal <= isIllegal & ~isLineA & ~isLineF; + rLineA <= isLineA; + rLineF <= isLineF; + rPriv <= isPriv & !psw[ SF]; + end + end + + // exception priority + always_comb begin + grp1Nma = TRAC1_NMA; + if( rExcRst) + tvn = '0; // Might need to change that to signal in exception + else if( rExcBusErr | rExcAdrErr) + tvn = { 1'b1, rExcAdrErr}; + + // Seudo group 0 exceptions. Just for updating TVN + else if( rSpurious | rAutovec) + tvn = rSpurious ? TVN_SPURIOUS : TVN_AUTOVEC; + + else if( rTrace) + tvn = 9; + else if( rInterrupt) begin + tvn = TVN_INTERRUPT; + grp1Nma = ITLX1_NMA; + end + else begin + unique case( 1'b1) // Can't happen more than one of these + rIllegal: tvn = 4; + rPriv: tvn = 8; + rLineA: tvn = 10; + rLineF: tvn = 11; + default: tvn = 1; // Signal no group 0/1 exception + endcase + end + end + + assign A0Sel = rIllegal | rLineF | rLineA | rPriv | rTrace | rInterrupt; + + always_ff @( posedge Clks.clk) begin + if( Clks.extReset) + a0Rst <= 1'b1; + else if( enT3) + a0Rst <= 1'b0; + end + +endmodule + + +// +// DMA/BUS Arbitration +// + +module busArbiter( input s_clks Clks, + input BRi, BgackI, Halti, bgBlock, + output busAvail, + output logic BGn); + + enum int unsigned { DRESET = 0, DIDLE, D1, D_BR, D_BA, D_BRA, D3, D2} dmaPhase, next; + + always_comb begin + case(dmaPhase) + DRESET: next = DIDLE; + DIDLE: begin + if( bgBlock) + next = DIDLE; + else if( ~BgackI) + next = D_BA; + else if( ~BRi) + next = D1; + else + next = DIDLE; + end + + D_BA: begin // Loop while only BGACK asserted, BG negated here + if( ~BRi & !bgBlock) + next = D3; + else if( ~BgackI & !bgBlock) + next = D_BA; + else + next = DIDLE; + end + + D1: next = D_BR; // Loop while only BR asserted + D_BR: next = ~BRi & BgackI ? D_BR : D_BA; // No direct path to IDLE ! + + D3: next = D_BRA; + D_BRA: begin // Loop while both BR and BGACK asserted + case( {BgackI, BRi} ) + 2'b11: next = DIDLE; // Both deasserted + 2'b10: next = D_BR; // BR asserted only + 2'b01: next = D2; // BGACK asserted only + 2'b00: next = D_BRA; // Stay here while both asserted + endcase + end + + // Might loop here if both deasserted, should normally don't arrive here anyway? + // D2: next = (BgackI & BRi) | bgBlock ? D2: D_BA; + + D2: next = D_BA; + + default: next = DIDLE; // Should not reach here normally + endcase + end + + logic granting; + always_comb begin + unique case( next) + D1, D3, D_BR, D_BRA: granting = 1'b1; + default: granting = 1'b0; + endcase + end + + reg rGranted; + assign busAvail = Halti & BRi & BgackI & ~rGranted; + + always_ff @( posedge Clks.clk) begin + if( Clks.extReset) begin + dmaPhase <= DRESET; + rGranted <= 1'b0; + end + else if( Clks.enPhi2) begin + dmaPhase <= next; + // Internal signal changed on PHI2 + rGranted <= granting; + end + + // External Output changed on PHI1 + if( Clks.extReset) + BGn <= 1'b1; + else if( Clks.enPhi1) + BGn <= ~rGranted; + + end + +endmodule + +module busControl( input s_clks Clks, input enT1, input enT4, + input permStart, permStop, iStop, + input aob0, + input isWrite, isByte, isRmc, + input busAvail, + output bgBlock, + output busAddrErr, + output waitBusCycle, + output busStarting, // Asserted during S0 + output logic addrOe, // Asserted from S1 to the end, whole bus cycle except S0 + output bciWrite, // Used for SSW on bus/addr error + + input rDtack, BeDebounced, Vpai, + output ASn, output LDSn, output UDSn, eRWn); + + reg rAS, rLDS, rUDS, rRWn; + assign ASn = rAS; + assign LDSn = rLDS; + assign UDSn = rUDS; + assign eRWn = rRWn; + + //reg dataOe; + + reg bcPend; + reg isWriteReg, bciByte, isRmcReg, wendReg; + assign bciWrite = isWriteReg; + reg addrOeDelay; + reg isByteT4; + + wire canStart, busEnd; + wire bcComplete, bcReset; + + wire isRcmReset = bcComplete & bcReset & isRmcReg; + + assign busAddrErr = aob0 & ~bciByte; + + // Bus retry not really supported. + // It's BERR and HALT and not address error, and not read-modify cycle. + wire busRetry = ~busAddrErr & 1'b0; + + enum int unsigned { SRESET = 0, SIDLE, S0, S2, S4, S6, SRMC_RES} busPhase, next; + + always_ff @( posedge Clks.clk) begin + if( Clks.extReset) + busPhase <= SRESET; + else if( Clks.enPhi1) + busPhase <= next; + end + + always_comb begin + case( busPhase) + SRESET: next = SIDLE; + SRMC_RES: next = SIDLE; // Single cycle special state when read phase of RMC reset + S0: next = S2; + S2: next = S4; + S4: next = busEnd ? S6 : S4; + S6: next = isRcmReset ? SRMC_RES : (canStart ? S0 : SIDLE); + SIDLE: next = canStart ? S0 : SIDLE; + default: next = SIDLE; + endcase + end + + // Idle phase of RMC bus cycle. Might be better to just add a new state + wire rmcIdle = (busPhase == SIDLE) & ~ASn & isRmcReg; + + assign canStart = (busAvail | rmcIdle) & (bcPend | permStart) & !busRetry & !bcReset; + + wire busEnding = (next == SIDLE) | (next == S0); + + assign busStarting = (busPhase == S0); + + // term signal (DTACK, BERR, VPA, adress error) + assign busEnd = ~rDtack | iStop; + + // bcComplete asserted on raising edge of S6 (together with SNC). + assign bcComplete = (busPhase == S6); + + // Clear bus info latch on completion (regular or aborted) and no bus retry (and not PHI1). + // bciClear asserted half clock later on PHI2, and bci latches cleared async concurrently + wire bciClear = bcComplete & ~busRetry; + + // Reset on reset or (berr & berrDelay & (not halt or rmc) & not 6800 & in bus cycle) (and not PHI1) + assign bcReset = Clks.extReset | (addrOeDelay & BeDebounced & Vpai); + + // Enable uclock only on S6 (S8 on Bus Error) or not bciPermStop + assign waitBusCycle = wendReg & !bcComplete; + + // Block Bus Grant when starting new bus cycle. But No need if AS already asserted (read phase of RMC) + // Except that when that RMC phase aborted on bus error, it's asserted one cycle later! + assign bgBlock = ((busPhase == S0) & ASn) | (busPhase == SRMC_RES); + + always_ff @( posedge Clks.clk) begin + if( Clks.extReset) begin + addrOe <= 1'b0; + end + else if( Clks.enPhi2 & ( busPhase == S0)) // From S1, whole bus cycle except S0 + addrOe <= 1'b1; + else if( Clks.enPhi1 & (busPhase == SRMC_RES)) + addrOe <= 1'b0; + else if( Clks.enPhi1 & ~isRmcReg & busEnding) + addrOe <= 1'b0; + + if( Clks.enPhi1) + addrOeDelay <= addrOe; + + if( Clks.extReset) begin + rAS <= 1'b1; + rUDS <= 1'b1; + rLDS <= 1'b1; + rRWn <= 1'b1; + //dataOe <= '0; + end + else begin +/* + if( Clks.enPhi2 & isWriteReg & (busPhase == S2)) + dataOe <= 1'b1; + else if( Clks.enPhi1 & (busEnding | (busPhase == SIDLE)) ) + dataOe <= 1'b0; +*/ + if( Clks.enPhi1 & busEnding) + rRWn <= 1'b1; + else if( Clks.enPhi1 & isWriteReg) begin + // Unlike LDS/UDS Asserted even in address error + if( (busPhase == S0) & isWriteReg) + rRWn <= 1'b0; + end + + // AS. Actually follows addrOe half cycle later! + if( Clks.enPhi1 & (busPhase == S0)) + rAS <= 1'b0; + else if( Clks.enPhi2 & (busPhase == SRMC_RES)) // Bus error on read phase of RMC. Deasserted one cycle later + rAS <= 1'b1; + else if( Clks.enPhi2 & bcComplete & ~SRMC_RES) + if( ~isRmcReg) // Keep AS asserted on the IDLE phase of RMC + rAS <= 1'b1; + + if( Clks.enPhi1 & (busPhase == S0)) begin + if( ~isWriteReg & !busAddrErr) begin + rUDS <= ~(~bciByte | ~aob0); + rLDS <= ~(~bciByte | aob0); + end + end + else if( Clks.enPhi1 & isWriteReg & (busPhase == S2) & !busAddrErr) begin + rUDS <= ~(~bciByte | ~aob0); + rLDS <= ~(~bciByte | aob0); + end + else if( Clks.enPhi2 & bcComplete) begin + rUDS <= 1'b1; + rLDS <= 1'b1; + end + + end + + end + + // Bus cycle info latch. Needed because uinstr might change if the bus is busy and we must wait. + // Note that urom advances even on wait states. It waits *after* updating urom and nanorom latches. + // Even without wait states, ublocks of type ir (init reading) will not wait for bus completion. + // Originally latched on (permStart AND T1). + + // Bus cycle info latch: isRead, isByte, read-modify-cycle, and permStart (bus cycle pending). Some previously latched on T4? + // permStop also latched, but unconditionally on T1 + + // Might make more sense to register this outside this module + always_ff @( posedge Clks.clk) begin + if( enT4) begin + isByteT4 <= isByte; + end + end + + // Bus Cycle Info Latch + always_ff @( posedge Clks.clk) begin + if( Clks.pwrUp) begin + bcPend <= 1'b0; + wendReg <= 1'b0; + isWriteReg <= 1'b0; + bciByte <= 1'b0; + isRmcReg <= 1'b0; + end + + else if( Clks.enPhi2 & (bciClear | bcReset)) begin + bcPend <= 1'b0; + wendReg <= 1'b0; + end + else begin + if( enT1 & permStart) begin + isWriteReg <= isWrite; + bciByte <= isByteT4; + isRmcReg <= isRmc & ~isWrite; // We need special case the end of the read phase only. + bcPend <= 1'b1; + end + if( enT1) + wendReg <= permStop; + end + end + +endmodule + +// +// microrom and nanorom instantiation +// +// There is bit of wasting of resources here. An extra registering pipeline happens that is not needed. +// This is just for the purpose of helping inferring block RAM using pure generic code. Inferring RAM is important for performance. +// Might be more efficient to use vendor specific features such as clock enable. +// + +module uRom( input clk, input [UADDR_WIDTH-1:0] microAddr, output logic [UROM_WIDTH-1:0] microOutput); + reg [UROM_WIDTH-1:0] uRam[ UROM_DEPTH]; + initial begin + $readmemb("microrom.mem", uRam); + end + + always_ff @( posedge clk) + microOutput <= uRam[ microAddr]; +endmodule + + +module nanoRom( input clk, input [NADDR_WIDTH-1:0] nanoAddr, output logic [NANO_WIDTH-1:0] nanoOutput); + reg [NANO_WIDTH-1:0] nRam[ NANO_DEPTH]; + initial begin + $readmemb("nanorom.mem", nRam); + end + + always_ff @( posedge clk) + nanoOutput <= nRam[ nanoAddr]; +endmodule + +// Translate uaddr to nanoaddr +module microToNanoAddr( + input [UADDR_WIDTH-1:0] uAddr, + output [NADDR_WIDTH-1:0] orgAddr); + + wire [UADDR_WIDTH-1:2] baseAddr = uAddr[UADDR_WIDTH-1:2]; + logic [NADDR_WIDTH-1:2] orgBase; + assign orgAddr = { orgBase, uAddr[1:0]}; + + always @( baseAddr) + begin + // nano ROM (136 addresses) + case( baseAddr) + +'h00: orgBase = 7'h0 ; +'h01: orgBase = 7'h1 ; +'h02: orgBase = 7'h2 ; +'h03: orgBase = 7'h2 ; +'h08: orgBase = 7'h3 ; +'h09: orgBase = 7'h4 ; +'h0A: orgBase = 7'h5 ; +'h0B: orgBase = 7'h5 ; +'h10: orgBase = 7'h6 ; +'h11: orgBase = 7'h7 ; +'h12: orgBase = 7'h8 ; +'h13: orgBase = 7'h8 ; +'h18: orgBase = 7'h9 ; +'h19: orgBase = 7'hA ; +'h1A: orgBase = 7'hB ; +'h1B: orgBase = 7'hB ; +'h20: orgBase = 7'hC ; +'h21: orgBase = 7'hD ; +'h22: orgBase = 7'hE ; +'h23: orgBase = 7'hD ; +'h28: orgBase = 7'hF ; +'h29: orgBase = 7'h10 ; +'h2A: orgBase = 7'h11 ; +'h2B: orgBase = 7'h10 ; +'h30: orgBase = 7'h12 ; +'h31: orgBase = 7'h13 ; +'h32: orgBase = 7'h14 ; +'h33: orgBase = 7'h14 ; +'h38: orgBase = 7'h15 ; +'h39: orgBase = 7'h16 ; +'h3A: orgBase = 7'h17 ; +'h3B: orgBase = 7'h17 ; +'h40: orgBase = 7'h18 ; +'h41: orgBase = 7'h18 ; +'h42: orgBase = 7'h18 ; +'h43: orgBase = 7'h18 ; +'h44: orgBase = 7'h19 ; +'h45: orgBase = 7'h19 ; +'h46: orgBase = 7'h19 ; +'h47: orgBase = 7'h19 ; +'h48: orgBase = 7'h1A ; +'h49: orgBase = 7'h1A ; +'h4A: orgBase = 7'h1A ; +'h4B: orgBase = 7'h1A ; +'h4C: orgBase = 7'h1B ; +'h4D: orgBase = 7'h1B ; +'h4E: orgBase = 7'h1B ; +'h4F: orgBase = 7'h1B ; +'h54: orgBase = 7'h1C ; +'h55: orgBase = 7'h1D ; +'h56: orgBase = 7'h1E ; +'h57: orgBase = 7'h1F ; +'h5C: orgBase = 7'h20 ; +'h5D: orgBase = 7'h21 ; +'h5E: orgBase = 7'h22 ; +'h5F: orgBase = 7'h23 ; +'h70: orgBase = 7'h24 ; +'h71: orgBase = 7'h24 ; +'h72: orgBase = 7'h24 ; +'h73: orgBase = 7'h24 ; +'h74: orgBase = 7'h24 ; +'h75: orgBase = 7'h24 ; +'h76: orgBase = 7'h24 ; +'h77: orgBase = 7'h24 ; +'h78: orgBase = 7'h25 ; +'h79: orgBase = 7'h25 ; +'h7A: orgBase = 7'h25 ; +'h7B: orgBase = 7'h25 ; +'h7C: orgBase = 7'h25 ; +'h7D: orgBase = 7'h25 ; +'h7E: orgBase = 7'h25 ; +'h7F: orgBase = 7'h25 ; +'h84: orgBase = 7'h26 ; +'h85: orgBase = 7'h27 ; +'h86: orgBase = 7'h28 ; +'h87: orgBase = 7'h29 ; +'h8C: orgBase = 7'h2A ; +'h8D: orgBase = 7'h2B ; +'h8E: orgBase = 7'h2C ; +'h8F: orgBase = 7'h2D ; +'h94: orgBase = 7'h2E ; +'h95: orgBase = 7'h2F ; +'h96: orgBase = 7'h30 ; +'h97: orgBase = 7'h31 ; +'h9C: orgBase = 7'h32 ; +'h9D: orgBase = 7'h33 ; +'h9E: orgBase = 7'h34 ; +'h9F: orgBase = 7'h35 ; +'hA4: orgBase = 7'h36 ; +'hA5: orgBase = 7'h36 ; +'hA6: orgBase = 7'h37 ; +'hA7: orgBase = 7'h37 ; +'hAC: orgBase = 7'h38 ; +'hAD: orgBase = 7'h38 ; +'hAE: orgBase = 7'h39 ; +'hAF: orgBase = 7'h39 ; +'hB4: orgBase = 7'h3A ; +'hB5: orgBase = 7'h3A ; +'hB6: orgBase = 7'h3B ; +'hB7: orgBase = 7'h3B ; +'hBC: orgBase = 7'h3C ; +'hBD: orgBase = 7'h3C ; +'hBE: orgBase = 7'h3D ; +'hBF: orgBase = 7'h3D ; +'hC0: orgBase = 7'h3E ; +'hC1: orgBase = 7'h3F ; +'hC2: orgBase = 7'h40 ; +'hC3: orgBase = 7'h41 ; +'hC8: orgBase = 7'h42 ; +'hC9: orgBase = 7'h43 ; +'hCA: orgBase = 7'h44 ; +'hCB: orgBase = 7'h45 ; +'hD0: orgBase = 7'h46 ; +'hD1: orgBase = 7'h47 ; +'hD2: orgBase = 7'h48 ; +'hD3: orgBase = 7'h49 ; +'hD8: orgBase = 7'h4A ; +'hD9: orgBase = 7'h4B ; +'hDA: orgBase = 7'h4C ; +'hDB: orgBase = 7'h4D ; +'hE0: orgBase = 7'h4E ; +'hE1: orgBase = 7'h4E ; +'hE2: orgBase = 7'h4F ; +'hE3: orgBase = 7'h4F ; +'hE8: orgBase = 7'h50 ; +'hE9: orgBase = 7'h50 ; +'hEA: orgBase = 7'h51 ; +'hEB: orgBase = 7'h51 ; +'hF0: orgBase = 7'h52 ; +'hF1: orgBase = 7'h52 ; +'hF2: orgBase = 7'h52 ; +'hF3: orgBase = 7'h52 ; +'hF8: orgBase = 7'h53 ; +'hF9: orgBase = 7'h53 ; +'hFA: orgBase = 7'h53 ; +'hFB: orgBase = 7'h53 ; + + default: + orgBase = 'X; + endcase + end + +endmodule + +// +// For compilation test only +// + +`ifdef FX68K_TEST +module fx68kTop( input clk32, + input extReset, + // input pwrUp, + + input DTACKn, input VPAn, + input BERRn, + input BRn, BGACKn, + input IPL0n, input IPL1n, input IPL2n, + input [15:0] iEdb, + + output [15:0] oEdb, + output eRWn, output ASn, output LDSn, output UDSn, + output logic E, output VMAn, + output FC0, output FC1, output FC2, + output BGn, + output oRESETn, output oHALTEDn, + output [23:1] eab + ); + + // Clock must be at least twice the desired frequency. A 32 MHz clock means a maximum 16 MHz effective frequency. + // In this example we divide the clock by 4. Resulting on an effective processor running at 8 MHz. + + reg [1:0] clkDivisor = '0; + always @( posedge clk32) begin + clkDivisor <= clkDivisor + 1'b1; + end + + /* + These two signals must be a single cycle pulse. They don't need to be registered. + Same signal can't be asserted twice in a row. Other than that there are no restrictions. + There can be any number of cycles, or none, even variable non constant cycles, between each pulse. + */ + + wire enPhi1 = (clkDivisor == 2'b11); + wire enPhi2 = (clkDivisor == 2'b01); + + + fx68k fx68k( .clk( clk32), + .extReset, .pwrUp( extReset), .enPhi1, .enPhi2, + + .DTACKn, .VPAn, .BERRn, .BRn, .BGACKn, + .IPL0n, .IPL1n, .IPL2n, + .iEdb, + + .oEdb, + .eRWn, .ASn, .LDSn, .UDSn, + .E, .VMAn, + .FC0, .FC1, .FC2, + .BGn, + .oRESETn, .oHALTEDn, .eab); + +endmodule +`endif diff --git a/rtl/fx68k/fx68k.txt b/rtl/fx68k/fx68k.txt new file mode 100644 index 0000000..b9c3c5a --- /dev/null +++ b/rtl/fx68k/fx68k.txt @@ -0,0 +1,87 @@ +FX68K + +68000 cycle accurate core +Copyright (c) 2018 by Jorge Cwik +fx68k@fxatari.com + + +FX68K is a 68K cycle exact compatible core. In theory at least, it should be impossible to distinguish functionally from a real 68K processor. + +On Cyclone families it uses just over 5,100 LEs and about 5KB internal ram, reaching a max clock frequency close to 40MHz. Some optimizations are still possible to implement and increase the performance. + +The core is fully synchronous. Considerable effort was done to avoid any asynchronous logic. + +Written in SystemVerilog. + +The timing of the external bus signals is exactly as the original processor. The only feature that is not implemented yet is bus retry using the external HALT input signal. + +It was designed to replace an actual chip on a real board. This wasn't yet tested however and not all necessary output enable control signals are fully implemented. + + +Copyright + +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + + +Developer Notes + + +The core receives a clock that must be at least twice the frequency of the desired nominal speed. The core also receives two signals for masking both phases of the clock (PHI1 and PHI2). These signals are implemented as simple clock enable for all the flip flops used by the core. This way, the original clock frequency can be any multiple and it doesn't even need to be regular or constant. + +These two signals are enPhi1 and enPhi2. They must be a single cycle pulse, and they don't need to be registered. Because they are actually used as clock enable, the output signals change one cycle later. + +enPhi1 should be asserted one cycle before the high phase of the nominal clock, and enPhi2 one cycle before the low phase. + +E.g., during a bus cycle, AS is asserted one cycle after enPhi1 is asserted, and AS is deasserted one cycle after enPhi2 is asserted. This follows the original bus timing that specify AS being asserted on the raising edge of the clock, and deasserted on the falling edge one. + +All signals follow the original polarity and then most are low active. + +extReset is external reset and is synchronous and high active. Hence is doesn't have to be registered. + +pwrUp qualifies external reset as being a cold power up reset. If it is asserted, then extReset must be asserted as well. Most system don't need to distinguish between a cold and a warm reset at the CPU level. Then both signals can be always asserted together. The core does expect pwrUp to be asserted initially because there is no true asynchronous reset. The signal is high active. + + +Timing analysis + +Microcode access is one of the slowest paths on the core. But the microcode output is not needed immediately. Use the following constraints to get a more accurate timing analysis. Note that the full path might need to be modified: + +# Altera/Intel + +set_multicycle_path -start -setup -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|microAddr[*]] 2 +set_multicycle_path -start -hold -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|microAddr[*]] 1 +set_multicycle_path -start -setup -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|nanoAddr[*]] 2 +set_multicycle_path -start -hold -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|nanoAddr[*]] 1 + +# For Xilinx Vivado + +set_multicycle_path -setup -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/nanoAddr_reg*/D] 2 +set_multicycle_path -setup -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/microAddr_reg*/D] 2 +set_multicycle_path -hold -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/nanoAddr_reg*/D] 1 +set_multicycle_path -hold -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/microAddr_reg*/D] 1 + + +The update of the CCR flags is also time critical. Some compilers might benefit with the following constraints, but this wasn't fully verified yet: + + +# Altera/Intel +# set_multicycle_path -start -setup -from [fx68k:fx68k|nanoLatch[*]] +# -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 2 +# set_multicycle_path -start -setup -from [fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|oper[*]] +# -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 2 +# set_multicycle_path -start -hold -from [fx68k:fx68k|nanoLatch[*]] +# -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 1 +# set_multicycle_path -start -hold -from [fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|oper[*]] +# -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 1 diff --git a/rtl/fx68k/fx68kAlu.sv b/rtl/fx68k/fx68kAlu.sv new file mode 100644 index 0000000..ada293b --- /dev/null +++ b/rtl/fx68k/fx68kAlu.sv @@ -0,0 +1,843 @@ +// +// FX 68K +// +// M68K cycle accurate, fully synchronous +// Copyright (c) 2018 by Jorge Cwik +// +// ALU +// + +// altera message_off 10230 +// altera message_off 10763 +// altera message_off 10958 + +`timescale 1 ns / 1 ns + +localparam MASK_NBITS = 5; + +localparam + OP_AND = 1, + OP_SUB = 2, OP_SUBX = 3, OP_ADD = 4, + OP_EXT = 5, OP_SBCD = 6, OP_SUB0 = 7, + OP_OR = 8, OP_EOR = 9, + OP_SUBC = 10, OP_ADDC = 11, OP_ADDX = 12, + OP_ASL = 13, + OP_ASR = 14, + OP_LSL = 15, + OP_LSR = 16, + OP_ROL = 17, + OP_ROR = 18, + OP_ROXL = 19, + OP_ROXR = 20, + OP_SLAA = 21, + OP_ABCD = 22; + +module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4, + input [15:0] ird, + input [2:0] aluColumn, + input [1:0] aluDataCtrl, + input aluAddrCtrl, alueClkEn, ftu2Ccr, init, finish, aluIsByte, + input [15:0] ftu, + input [15:0] alub, + input [15:0] iDataBus, input [15:0] iAddrBus, + output ze, + output reg [15:0] alue, + output reg [7:0] ccr, + output [15:0] aluOut); + + +`define ALU_ROW_01 16'h0002 +`define ALU_ROW_02 16'h0004 +`define ALU_ROW_03 16'h0008 +`define ALU_ROW_04 16'h0010 +`define ALU_ROW_05 16'h0020 +`define ALU_ROW_06 16'h0040 +`define ALU_ROW_07 16'h0080 +`define ALU_ROW_08 16'h0100 +`define ALU_ROW_09 16'h0200 +`define ALU_ROW_10 16'h0400 +`define ALU_ROW_11 16'h0800 +`define ALU_ROW_12 16'h1000 +`define ALU_ROW_13 16'h2000 +`define ALU_ROW_14 16'h4000 +`define ALU_ROW_15 16'h8000 + + + // Bit positions for flags in CCR + localparam CF = 0, VF = 1, ZF = 2, NF = 3, XF = 4; + + reg [15:0] aluLatch; + reg [4:0] pswCcr; + reg [4:0] ccrCore; + + logic [15:0] result; + logic [4:0] ccrTemp; + reg coreH; // half carry latch + + logic [15:0] subResult; + logic subHcarry; + logic subCout, subOv; + + assign aluOut = aluLatch; + assign ze = ~ccrCore[ ZF]; // Check polarity !!! + + // + // Control + // Signals derived from IRD *must* be registered on either T3 or T4 + // Signals derived from nano rom can be registered on T4. + + reg [15:0] row; + reg isArX; // Don't set Z + reg noCcrEn; + reg isByte; + + reg [4:0] ccrMask; + reg [4:0] oper; + + logic [15:0] aOperand, dOperand; + wire isCorf = ( aluDataCtrl == 2'b10); + + wire [15:0] cRow; + wire cIsArX; + wire cNoCcrEn; + rowDecoder rowDecoder( .ird( ird), .row( cRow), .noCcrEn( cNoCcrEn), .isArX( cIsArX)); + + // Get Operation & CCR Mask from row/col + // Registering them on T4 increase performance. But slowest part seems to be corf ! + wire [4:0] cMask; + wire [4:0] aluOp; + + aluGetOp aluGetOp( .row, .col( aluColumn), .isCorf, .aluOp); + ccrTable ccrTable( .col( aluColumn), .row( row), .finish, .ccrMask( cMask)); + + // Inefficient, uCode could help ! + wire shftIsMul = row[7]; + wire shftIsDiv = row[1]; + + wire [31:0] shftResult; + reg [7:0] bcdLatch; + reg bcdCarry, bcdOverf; + + reg isLong; + reg rIrd8; + logic isShift; + logic shftCin, shftRight, addCin; + + // Register some decoded signals + always_ff @( posedge clk) begin + if( enT3) begin + row <= cRow; + isArX <= cIsArX; + noCcrEn <= cNoCcrEn; + rIrd8 <= ird[8]; + isByte <= aluIsByte; + end + + if( enT4) begin + // Decode if long shift + // MUL and DIV are long (but special !) + isLong <= (ird[7] & ~ird[6]) | shftIsMul | shftIsDiv; + + ccrMask <= cMask; + oper <= aluOp; + end + end + + + always_comb begin + // Dest (addr) operand source + // If aluCsr (depends on column/row) addrbus is shifted !! + aOperand = (aluAddrCtrl ? alub : iAddrBus); + + // Second (data,source) operand mux + case( aluDataCtrl) + 2'b00: dOperand = iDataBus; + 2'b01: dOperand = 'h0000; + 2'b11: dOperand = 'hffff; + // 2'b10: dOperand = bcdResult; + 2'b10: dOperand = 'X; + endcase + end + + // Execution + + // shift operand MSB. Input in ASR/ROL. Carry in right. + // Can't be registered because uses bus operands that aren't available early ! + wire shftMsb = isLong ? alue[15] : (isByte ? aOperand[7] : aOperand[15]); + + aluShifter shifter( .data( { alue, aOperand}), + .swapWords( shftIsMul | shftIsDiv), + .cin( shftCin), .dir( shftRight), .isByte( isByte), .isLong( isLong), + .result( shftResult)); + + wire [7:0] bcdResult; + wire bcdC, bcdV; + aluCorf aluCorf( .binResult( aluLatch[7:0]), .hCarry( coreH), + .bAdd( (oper != OP_SBCD) ), .cin( pswCcr[ XF]), + .bcdResult( bcdResult), .dC( bcdC), .ov( bcdV)); + + // BCD adjust is among the slowest processing on ALU ! + // Precompute and register BCD result on T1 + // We don't need to wait for execution buses because corf is always added to ALU previous result + always_ff @( posedge clk) + if( enT1) begin + bcdLatch <= bcdResult; + bcdCarry <= bcdC; + bcdOverf <= bcdV; + end + + // Adder carry in selector + always_comb + begin + case( oper) + OP_ADD, OP_SUB: addCin = 1'b0; + OP_SUB0: addCin = 1'b1; // NOT = 0 - op - 1 + OP_ADDC,OP_SUBC: addCin = ccrCore[ CF]; + OP_ADDX,OP_SUBX: addCin = pswCcr[ XF]; + default: addCin = 1'bX; + endcase + end + + // Shifter carry in and direction selector + always_comb begin + case( oper) + OP_LSL, OP_ASL, OP_ROL, OP_ROXL, OP_SLAA: shftRight = 1'b0; + OP_LSR, OP_ASR, OP_ROR, OP_ROXR: shftRight = 1'b1; + default: shftRight = 1'bX; + endcase + + case( oper) + OP_LSR, + OP_ASL, + OP_LSL: shftCin = 1'b0; + OP_ROL, + OP_ASR: shftCin = shftMsb; + OP_ROR: shftCin = aOperand[0]; + OP_ROXL, + OP_ROXR: + if( shftIsMul) + shftCin = rIrd8 ? pswCcr[NF] ^ pswCcr[VF] : pswCcr[ CF]; + else + shftCin = pswCcr[ XF]; + + OP_SLAA: shftCin = aluColumn[1]; // col4 -> 0, col 6-> 1 + default: shftCin = 'X; + endcase + end + + // ALU operation selector + always_comb begin + + // sub is DATA - ADDR + mySubber( aOperand, dOperand, addCin, + (oper == OP_ADD) | (oper == OP_ADDC) | (oper == OP_ADDX), + isByte, subResult, subCout, subOv); + + isShift = 1'b0; + case( oper) + OP_AND: result = aOperand & dOperand; + OP_OR: result = aOperand | dOperand; + OP_EOR: result = aOperand ^ dOperand; + + OP_EXT: result = { {8{aOperand[7]}}, aOperand[7:0]}; + + OP_SLAA, + OP_ASL, OP_ASR, + OP_LSL, OP_LSR, + OP_ROL, OP_ROR, + OP_ROXL, OP_ROXR: + begin + result = shftResult[15:0]; + isShift = 1'b1; + end + + OP_ADD, + OP_ADDC, + OP_ADDX, + OP_SUB, + OP_SUBC, + OP_SUB0, + OP_SUBX: result = subResult; + + OP_ABCD, + OP_SBCD: result = { 8'hXX, bcdLatch}; + + default: result = 'X; + endcase + end + + task mySubber; + input [15:0] inpa, inpb; + input cin, bAdd, isByte; + output reg [15:0] result; + output cout, ov; + + // Not very efficient! + logic [16:0] rtemp; + logic rm,sm,dm,tsm; + + begin + if( isByte) + begin + rtemp = bAdd ? { 1'b0, inpb[7:0]} + { 1'b0, inpa[7:0]} + cin: + { 1'b0, inpb[7:0] } - { 1'b0, inpa[7:0]} - cin; + result = { {8{ rtemp[7]}}, rtemp[7:0]}; + cout = rtemp[8]; + end + else begin + rtemp = bAdd ? { 1'b0, inpb } + { 1'b0, inpa} + cin: + { 1'b0, inpb } - { 1'b0, inpa} - cin; + result = rtemp[ 15:0]; + cout = rtemp[16]; + end + + rm = isByte ? rtemp[7] : rtemp[15]; + dm = isByte ? inpb[ 7] : inpb[ 15]; + tsm = isByte ? inpa[ 7] : inpa[ 15]; + sm = bAdd ? tsm : ~tsm; + + ov = (sm & dm & ~rm) | (~sm & ~dm & rm); + + // Store half carry for bcd correction + subHcarry = inpa[4] ^ inpb[4] ^ rtemp[4]; + + end + endtask + + + // CCR flags process + always_comb begin + + ccrTemp[XF] = pswCcr[XF]; ccrTemp[CF] = 0; ccrTemp[VF] = 0; + + // Not on all operators + ccrTemp[ ZF] = isByte ? ~(| result[7:0]) : ~(| result); + ccrTemp[ NF] = isByte ? result[7] : result[15]; + + unique case( oper) + + OP_EXT: + // Division overflow. + if( aluColumn == 5) begin + ccrTemp[VF] = 1'b1; + ccrTemp[NF] = 1'b1; ccrTemp[ ZF] = 1'b0; + end + + OP_SUB0, // used by NOT + OP_OR, + OP_EOR: + begin + ccrTemp[CF] = 0; ccrTemp[VF] = 0; + end + + OP_AND: + begin + // ROXL/ROXR indeed copy X to C in column 1 (OP_AND), executed before entering the loop. + // Needed when rotate count is zero, the ucode with the ROX operator never reached. + // C must be set to the value of X, X remains unaffected. + if( (aluColumn == 1) & (row[11] | row[8])) + ccrTemp[CF] = pswCcr[XF]; + else + ccrTemp[CF] = 0; + ccrTemp[VF] = 0; + end + + // Assumes col 3 of DIV use C and not X ! + // V will be set in other cols (2/3) of DIV + OP_SLAA: ccrTemp[ CF] = aOperand[15]; + + OP_LSL,OP_ROXL: + begin + ccrTemp[ CF] = shftMsb; + ccrTemp[ XF] = shftMsb; + ccrTemp[ VF] = 1'b0; + end + + OP_LSR,OP_ROXR: + begin + // 0 Needed for mul, or carry gets in high word + ccrTemp[ CF] = shftIsMul ? 1'b0 : aOperand[0]; + ccrTemp[ XF] = aOperand[0]; + // Not relevant for MUL, we clear it at mulm6 (1f) anyway. + // Not that MUL can never overlow! + ccrTemp[ VF] = 0; + // Z is checking here ALU (low result is actually in ALUE). + // But it is correct, see comment above. + end + + OP_ASL: + begin + ccrTemp[ XF] = shftMsb; ccrTemp[ CF] = shftMsb; + // V set if msb changed on any shift. + // Otherwise clear previously on OP_AND (col 1i). + ccrTemp[ VF] = pswCcr[VF] | (shftMsb ^ + (isLong ? alue[15-1] : (isByte ? aOperand[7-1] : aOperand[15-1])) ); + end + OP_ASR: + begin + ccrTemp[ XF] = aOperand[0]; ccrTemp[ CF] = aOperand[0]; + ccrTemp[ VF] = 0; + end + + // X not changed on ROL/ROR ! + OP_ROL: ccrTemp[ CF] = shftMsb; + OP_ROR: ccrTemp[ CF] = aOperand[0]; + + OP_ADD, + OP_ADDC, + OP_ADDX, + OP_SUB, + OP_SUBC, + OP_SUBX: + begin + ccrTemp[ CF] = subCout; + ccrTemp[ XF] = subCout; + ccrTemp[ VF] = subOv; + end + + OP_ABCD, + OP_SBCD: + begin + ccrTemp[ XF] = bcdCarry; + ccrTemp[ CF] = bcdCarry; + ccrTemp[ VF] = bcdOverf; + end + + endcase + + end + + // Core and psw latched at the same cycle + + // CCR filter + // CCR out mux for Z & C flags + // Z flag for 32-bit result + // Not described, but should be used also for instructions + // that clear but not set Z (ADDX/SUBX/ABCD, etc)! + logic [4:0] ccrMasked; + always_comb begin + ccrMasked = (ccrTemp & ccrMask) | (pswCcr & ~ccrMask); + // if( finish | isCorf | isArX) // No need to check specicially for isCorf as they always have the "finish" flag anyway + if( finish | isArX) + ccrMasked[ ZF] = ccrTemp[ ZF] & pswCcr[ ZF]; + end + + always_ff @( posedge clk) begin + if( enT3) begin + // Update latches from ALU operators + if( (| aluColumn)) begin + aluLatch <= result; + + coreH <= subHcarry; + + // Update CCR core + if( (| aluColumn)) + ccrCore <= ccrTemp; // Most bits not really used + end + + if( alueClkEn) + alue <= iDataBus; + else if( isShift & (| aluColumn)) + alue <= shftResult[31:16]; + end + + // CCR + // Originally on T3-T4 edge pulse !! + // Might be possible to update on T4 (but not after T0) from partial result registered on T3, it will increase performance! + if( pwrUp) + pswCcr <= '0; + else if( enT3 & ftu2Ccr) + pswCcr <= ftu[4:0]; + else if( enT3 & ~noCcrEn & (finish | init)) + pswCcr <= ccrMasked; + end + assign ccr = { 3'b0, pswCcr}; + + +endmodule + +// add bcd correction factor +// It would be more efficient to merge add/sub with main ALU !!! +module aluCorf( input [7:0] binResult, input bAdd, input cin, input hCarry, + output [7:0] bcdResult, output dC, output logic ov); + + reg [8:0] htemp; + reg [4:0] hNib; + + wire lowC = hCarry | (bAdd ? gt9( binResult[ 3:0]) : 1'b0); + wire highC = cin | (bAdd ? (gt9( htemp[7:4]) | htemp[8]) : 1'b0); + + always_comb begin + if( bAdd) begin + htemp = { 1'b0, binResult} + (lowC ? 4'h6 : 4'h0); + hNib = htemp[8:4] + (highC ? 4'h6 : 4'h0); + ov = hNib[3] & ~binResult[7]; + end + else begin + htemp = { 1'b0, binResult} - (lowC ? 4'h6 : 4'h0); + hNib = htemp[8:4] - (highC ? 4'h6 : 4'h0); + ov = ~hNib[3] & binResult[7]; + end + end + + assign bcdResult = { hNib[ 3:0], htemp[3:0]}; + assign dC = hNib[4] | cin; + + // Nibble > 9 + function gt9 (input [3:0] nib); + begin + gt9 = nib[3] & (nib[2] | nib[1]); + end + endfunction + +endmodule + + +module aluShifter( input [31:0] data, + input isByte, input isLong, swapWords, + input dir, input cin, + output logic [31:0] result); + // output reg cout + + logic [31:0] tdata; + + // size mux, put cin in position if dir == right + always_comb begin + tdata = data; + if( isByte & dir) + tdata[8] = cin; + else if( !isLong & dir) + tdata[16] = cin; + end + + always_comb begin + // Reverse alu/alue position for MUL & DIV + // Result reversed again + if( swapWords & dir) + result = { tdata[0], tdata[31:17], cin, tdata[15:1]}; + else if( swapWords) + result = { tdata[30:16], cin, tdata[14:0], tdata[31]}; + + else if( dir) + result = { cin, tdata[31:1]}; + else + result = { tdata[30:0], cin}; + end + +endmodule + + +// Get current OP from row & col +module aluGetOp( input [15:0] row, input [2:0] col, input isCorf, + output logic [4:0] aluOp); + + always_comb begin + aluOp = 'X; + unique case( col) + 1: aluOp = OP_AND; + 5: aluOp = OP_EXT; + + default: + unique case( 1'b1) + row[1]: + unique case( col) + 2: aluOp = OP_SUB; + 3: aluOp = OP_SUBC; + 4,6: aluOp = OP_SLAA; + endcase + + row[2]: + unique case( col) + 2: aluOp = OP_ADD; + 3: aluOp = OP_ADDC; + 4: aluOp = OP_ASR; + endcase + + row[3]: + unique case( col) + 2: aluOp = OP_ADDX; + 3: aluOp = isCorf ? OP_ABCD : OP_ADD; + 4: aluOp = OP_ASL; + endcase + + row[4]: + aluOp = ( col == 4) ? OP_LSL : OP_AND; + + row[5], + row[6]: + unique case( col) + 2: aluOp = OP_SUB; + 3: aluOp = OP_SUBC; + 4: aluOp = OP_LSR; + endcase + + row[7]: // MUL + unique case( col) + 2: aluOp = OP_SUB; + 3: aluOp = OP_ADD; + 4: aluOp = OP_ROXR; + endcase + + row[8]: + // OP_AND For EXT.L + // But would be more efficient to change ucode and use column 1 instead of col3 at ublock extr1! + unique case( col) + 2: aluOp = OP_EXT; + 3: aluOp = OP_AND; + 4: aluOp = OP_ROXR; + endcase + + row[9]: + unique case( col) + 2: aluOp = OP_SUBX; + 3: aluOp = OP_SBCD; + 4: aluOp = OP_ROL; + endcase + + row[10]: + unique case( col) + 2: aluOp = OP_SUBX; + 3: aluOp = OP_SUBC; + 4: aluOp = OP_ROR; + endcase + + row[11]: + unique case( col) + 2: aluOp = OP_SUB0; + 3: aluOp = OP_SUB0; + 4: aluOp = OP_ROXL; + endcase + + row[12]: aluOp = OP_ADDX; + row[13]: aluOp = OP_EOR; + row[14]: aluOp = (col == 4) ? OP_EOR : OP_OR; + row[15]: aluOp = (col == 3) ? OP_ADD : OP_OR; // OP_ADD used by DBcc + + endcase + endcase + end +endmodule + +// Decodes IRD into ALU row (1-15) +// Slow, but no need to optimize for speed since IRD is latched at least two CPU cycles before it is used +// We also register the result after combining with column from nanocode +// +// Many opcodes are not decoded because they either don't do any ALU op, +// or use only columns 1 and 5 that are the same for all rows. + +module rowDecoder( input [15:0] ird, + output logic [15:0] row, output noCcrEn, output logic isArX); + + + // Addr or data register direct + wire eaRdir = (ird[ 5:4] == 2'b00); + // Addr register direct + wire eaAdir = (ird[ 5:3] == 3'b001); + wire size11 = ird[7] & ird[6]; + + always_comb begin + case( ird[15:12]) + 'h4, + 'h9, + 'hd: + isArX = row[10] | row[12]; + default: + isArX = 1'b0; + endcase + end + + always_comb begin + unique case( ird[15:12]) + + 'h4: begin + if( ird[8]) + row = `ALU_ROW_06; // chk (or lea) + else case( ird[11:9]) + 'b000: row = `ALU_ROW_10; // negx + 'b001: row = `ALU_ROW_04; // clr + 'b010: row = `ALU_ROW_05; // neg + 'b011: row = `ALU_ROW_11; // not + 'b100: row = (ird[7]) ? `ALU_ROW_08 : `ALU_ROW_09; // nbcd/swap/ext(or pea) + 'b101: row = `ALU_ROW_15; // tst & tas + default: row = 0; + endcase + end + + 'h0: begin + if( ird[8]) // dynamic bit + row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13; + else case( ird[ 11:9]) + 'b000: row = `ALU_ROW_14; // ori + 'b001: row = `ALU_ROW_04; // andi + 'b010: row = `ALU_ROW_05; // subi + 'b011: row = `ALU_ROW_02; // addi + 'b100: row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13; // static bit + 'b101: row = `ALU_ROW_13; // eori + 'b110: row = `ALU_ROW_06; // cmpi + default: row = 0; + endcase + end + + // MOVE + // move.b originally also rows 5 & 15. Only because IRD bit 14 is not decoded. + // It's the same for move the operations performed by MOVE.B + + 'h1,'h2,'h3: row = `ALU_ROW_02; + + 'h5: + if( size11) + row = `ALU_ROW_15; // As originally and easier to decode + else + row = ird[8] ? `ALU_ROW_05 : `ALU_ROW_02; // addq/subq + 'h6: row = 0; //bcc/bra/bsr + 'h7: row = `ALU_ROW_02; // moveq + 'h8: + if( size11) // div + row = `ALU_ROW_01; + else if( ird[8] & eaRdir) // sbcd + row = `ALU_ROW_09; + else + row = `ALU_ROW_14; // or + 'h9: + if( ird[8] & ~size11 & eaRdir) + row = `ALU_ROW_10; // subx + else + row = `ALU_ROW_05; // sub/suba + 'hb: + if( ird[8] & ~size11 & ~eaAdir) + row = `ALU_ROW_13; // eor + else + row = `ALU_ROW_06; // cmp/cmpa/cmpm + 'hc: + if( size11) + row = `ALU_ROW_07; // mul + else if( ird[8] & eaRdir) // abcd + row = `ALU_ROW_03; + else + row = `ALU_ROW_04; // and + 'hd: + if( ird[8] & ~size11 & eaRdir) + row = `ALU_ROW_12; // addx + else + row = `ALU_ROW_02; // add/adda + 'he: + begin + reg [1:0] stype; + + if( size11) // memory shift/rotate + stype = ird[ 10:9]; + else // register shift/rotate + stype = ird[ 4:3]; + + case( {stype, ird[8]}) + 0: row = `ALU_ROW_02; // ASR + 1: row = `ALU_ROW_03; // ASL + 2: row = `ALU_ROW_05; // LSR + 3: row = `ALU_ROW_04; // LSL + 4: row = `ALU_ROW_08; // ROXR + 5: row = `ALU_ROW_11; // ROXL + 6: row = `ALU_ROW_10; // ROR + 7: row = `ALU_ROW_09; // ROL + endcase + end + + default: row = 0; + endcase + end + + // Decode opcodes that don't affect flags + // ADDA/SUBA ADDQ/SUBQ MOVEA + + assign noCcrEn = + // ADDA/SUBA + ( ird[15] & ~ird[13] & ird[12] & size11) | + // ADDQ/SUBQ to An + ( (ird[15:12] == 4'h5) & eaAdir) | + // MOVEA + ( (~ird[15] & ~ird[14] & ird[13]) & ird[8:6] == 3'b001); + +endmodule + +// Row/col CCR update table +module ccrTable( + input [2:0] col, input [15:0] row, input finish, + output logic [MASK_NBITS-1:0] ccrMask); + + localparam + KNZ00 = 5'b01111, // ok coz operators clear them + KKZKK = 5'b00100, + KNZKK = 5'b01100, + KNZ10 = 5'b01111, // Used by OP_EXT on divison overflow + KNZ0C = 5'b01111, // Used by DIV. V should be 0, but it is ok: + // DIVU: ends with quotient - 0, so V & C always clear. + // DIVS: ends with 1i (AND), again, V & C always clear. + + KNZVC = 5'b01111, + XNKVC = 5'b11011, // Used by BCD instructions. Don't modify Z at all at the binary operation. Only at the BCD correction cycle + + CUPDALL = 5'b11111, + CUNUSED = 5'bxxxxx; + + + logic [MASK_NBITS-1:0] ccrMask1; + + always_comb begin + unique case( col) + 1: ccrMask = ccrMask1; + + 2,3: + unique case( 1'b1) + row[1]: ccrMask = KNZ0C; // DIV, used as 3n in col3 + + row[3], // ABCD + row[9]: // SBCD/NBCD + ccrMask = (col == 2) ? XNKVC : CUPDALL; + + row[2], + row[5], + row[10], // SUBX/NEGX + row[12]: ccrMask = CUPDALL; // ADDX + + row[6], // CMP + row[7], // MUL + row[11]: ccrMask = KNZVC; // NOT + row[4], + row[8], // Not used in col 3 + row[13], + row[14]: ccrMask = KNZ00; + row[15]: ccrMask = 5'b0; // TAS/Scc, not used in col 3 + // default: ccrMask = CUNUSED; + endcase + + 4: + unique case( row) + // 1: DIV, only n (4n & 6n) + // 14: BCLR 4n + // 6,12,13,15 // not used + `ALU_ROW_02, + `ALU_ROW_03, // ASL (originally ANZVA) + `ALU_ROW_04, + `ALU_ROW_05: ccrMask = CUPDALL; // Shifts (originally ANZ0A) + + `ALU_ROW_07: ccrMask = KNZ00; // MUL (originally KNZ0A) + `ALU_ROW_09, + `ALU_ROW_10: ccrMask = KNZ00; // RO[lr] (originally KNZ0A) + `ALU_ROW_08, // ROXR (originally ANZ0A) + `ALU_ROW_11: ccrMask = CUPDALL; // ROXL (originally ANZ0A) + default: ccrMask = CUNUSED; + endcase + + 5: ccrMask = row[1] ? KNZ10 : 5'b0; + default: ccrMask = CUNUSED; + endcase + end + + // Column 1 (AND) + always_comb begin + if( finish) + ccrMask1 = row[7] ? KNZ00 : KNZKK; + else + ccrMask1 = row[13] | row[14] ? KKZKK : KNZ00; + end + +endmodule diff --git a/rtl/fx68k/microrom.mem b/rtl/fx68k/microrom.mem new file mode 100644 index 0000000..22558e8 --- /dev/null +++ b/rtl/fx68k/microrom.mem @@ -0,0 +1,1024 @@ +10010000101100000 +10000100000000000 +00101001011010000 +00111110011000000 +01000000000001100 +01000000000001100 +01000010010000000 +10001100011100000 +01000100010000000 +10000000010000000 +10000000010000000 +01000100010000000 +00001010010000000 +10000000100000000 +10000000100000000 +01101001100000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000100 +00001010110000000 +00111000001100000 +00100101001001010 +00000000000001100 +10110000110100001 +00000000000001100 +00001110100000000 +00110100101000000 +00100011010100000 +00000010010000000 +10000110000000010 +00111110110000000 +00000100011100000 +00101111010100000 +10010011100000010 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +10011101000000000 +00000100110010110 +00101001010000000 +10110000110100001 +00000000000000100 +00111110000100000 +10010111010100000 +01000110000100000 +01010111100000000 +10001010010011010 +01000110010100001 +00000110010111010 +01001100010100000 +10001010010010111 +01000000000100001 +00110100111000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000010001100000 +01001010000100001 +10110100111000000 +00011011010100000 +10000000000000100 +10110100111000000 +00000000000000100 +00001000001000000 +00000100011100110 +10001110010100001 +00000000011110010 +01001000011000000 +00001000010100110 +10001010000110111 +00000000111110010 +01001000111000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +10101001000000001 +10001000001000001 +01000000000000100 +01001100001111010 +00000110001000000 +00010110001100000 +00011010000000000 +10110000110100001 +01111000001100000 +00011000000000000 +00000100100100001 +00000000000000100 +00000000101100000 +00000000000000100 +00010001010100000 +10010111000100001 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000010001100000 +00000000000000100 +01111000011100000 +00011011010100000 +00101101000000000 +01000110010111010 +00101101000000000 +10001010101100000 +01010110001100000 +00011000110000000 +01010110001100000 +10001110011100001 +00000100101100000 +01000110010111010 +00000100101100000 +10001010111100000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +10101001000000001 +00001000101010110 +00011111010100000 +01101101110000000 +00000000000000100 +10111110000100000 +00000100011100000 +10001100101000001 +00000110001000000 +00001110000010010 +00100101000010110 +00101101000100000 +00000000011100000 +00001000111100000 +00100101000011010 +00110100111000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000010000100010 +00001010110000000 +00000000000000100 +00101101010000000 +01010001010000000 +01000110111000000 +00000000000000100 +00000000010110010 +00110100101000000 +00100011010100000 +10000000000001000 +01101011010000000 +00111110110000000 +00000100011100000 +10010101000000000 +01111110010100000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +10001100101000001 +10000010100000010 +01000010101000000 +00011111100100000 +10100111100000001 +10010010110000010 +01110100111000000 +00010111010000000 +10101011100000001 +10010010100000010 +01110000100100000 +00000000100100000 +10100101100100001 +10000010110000010 +01001010101000000 +00010111000000000 +00010001000010110 +01110010100111010 +10110100010000000 +00110100111000000 +01000010010000110 +01110010110111011 +01111100000000000 +00101101000100000 +00101001001010001 +01011011111100000 +01101111011000000 +00100011100000000 +00111110000110000 +00000000000000000 +10101111011000000 +00000000000000000 +00001010100000000 +10101011100100001 +01010011000100001 +10010101010000000 +00000000110000000 +10111010000100001 +01011001010000000 +10010101000000000 +00101101101100000 +10100011100100001 +01011110100000000 +01110100011100000 +00101011111000000 +10110000110100001 +01010101010100001 +00000000000000000 +00111000100000000 +01011011000000000 +00001000100100000 +10001100101000001 +00100001100000000 +01011011010000000 +00001000110100000 +10011001110100001 +00000110010111010 +01011011100000000 +00000000110100000 +10011101010000001 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +10110000110100001 +00011101000100000 +00011101000100000 +00010001000101110 +01011010110000000 +01011001010100000 +10011101010100000 +00000000000000100 +10110000110100001 +00110110000000000 +10110000011100001 +10110000011100001 +10011101000000001 +01110100111000000 +00101101100100000 +10011000100000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +10000000000000100 +00000000000000100 +00000100111000000 +00000100111000000 +00000100111000000 +00001100010101010 +00001000000010110 +00101001010000000 +10011000100000000 +00011011100100000 +01000100010000000 +01000000000001100 +10011000010000001 +10011011110100000 +10011111110100001 +00011000010000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00111110001000000 +10101011100100001 +10001010100000000 +10101011100100001 +00100011010000000 +10110000001100001 +10000000110000000 +10110000101100001 +00000000000000000 +10110000101100001 +10110110110100000 +10100001110100001 +00111100010000000 +10011101100000001 +10111110100100000 +10010011010100001 +00111100010100000 +10101011100000001 +10101001101000000 +10101011100000001 +00000000000000000 +10011111000100001 +10101001111000000 +10011011000100001 +00000000000000000 +10010011010100001 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00001010100000000 +10111110000100000 +10000100100000000 +00111010001100000 +00000000110000000 +10011001000000000 +10000100110000000 +00111010011100000 +00101101101100000 +10001110111000000 +10101111101000000 +00010100100000000 +00101011111000000 +10110100001100000 +10101111111000000 +00010100010000000 +00111000100000000 +10110100101100000 +10101001010100000 +00101011001000000 +00100001100000000 +10001110010000000 +10101111001000000 +00101011011000000 +00000110010111010 +10111000110000000 +10011101110100000 +00111010101100000 +00000000000000000 +10101011011100000 +01100011110100001 +00111010111100000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00100101000000000 +00000100000010110 +00000000000000100 +00001110000001110 +00100001000000000 +10110000110100001 +00100101011001010 +00111000001100000 +00100101100000001 +10011000010000000 +01101101100000000 +00000000000001100 +01100101110000000 +00000000000001100 +00001100001111010 +01001100001111010 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +10101111000000001 +00000100111000000 +10101111000000001 +00000000000000100 +00100111010000000 +00001110101100000 +11010001100000000 +00110010100111010 +00000000000000100 +00000100111000000 +00000000000000100 +10110000110100001 +01100111110000001 +10000000000000100 +01111100100100000 +01100001100100001 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000001100000 +10001010010100001 +00110110100000110 +00000000000000100 +00100001000000000 +10111110000100000 +10100111000100000 +00111000010000000 +10000000000000100 +00101001100100000 +00101101100100000 +00000000000000100 +00100101110100000 +00000000000000100 +00100101110100000 +00100101110100000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +10100111000100000 +01101011000100000 +01111110000100001 +10100111000100000 +10100111001000000 +10111110000100000 +00101111010000000 +00110010100111010 +00000000000000100 +10100011100100001 +00000000000000100 +00000010011100001 +10100111110100000 +00000000000000100 +00101111110100000 +00101111101100000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00100101001000000 +00101001000010110 +00110010000100000 +00100011000100000 +00100101011000000 +00101001011100000 +00101011110110000 +00101111001000000 +00010100000000000 +10110100111000001 +01110010100100000 +10110000110100001 +00010100110000000 +10110100110100001 +01111000110100000 +10111110110100001 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00100011010100000 +00100111000100000 +00000110100000010 +10111110000100000 +00000100011100000 +00110000110000000 +00000110110000010 +10010001110000000 +10110100111000001 +10000000000001000 +01110000100100000 +10110100101000000 +10010101110100001 +10111110000100000 +01101101111100000 +10101011101000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00101001000010110 +10001010011100001 +00100001000000110 +00101101000000110 +00101001011100000 +10001010011100001 +00110110111000110 +00101101010000110 +10001100101000001 +10110100101000000 +10101101101100000 +01111110000100001 +10100101100100001 +10101011101000000 +10101011111000000 +01100001100100001 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00110010100111010 +10001010010100001 +10110100100000000 +10110100111000001 +01110010110111010 +10001010010100001 +10101011010100000 +10110100110100001 +10111100100100001 +01101111110000000 +01000110010000001 +10101111111100000 +10101011110000001 +01100011110000000 +01110100100100001 +10110000000000000 +10011001110000000 +00110110000000000 +00101111001000000 +10111110000100000 +00110100111000000 +10001100100100000 +00000000000000100 +00110010000000000 +00000100010100110 +00111110000100000 +00111110000100000 +10100111011000000 +01110100110000001 +01110100100100000 +10010101000000000 +10110110100000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00110110000000000 +00010110001100000 +00000110010111010 +00000110010111010 +00110100111000000 +10111010010000000 +00001110110000000 +00000000000000100 +10110000110100001 +01111010100000000 +01010110001100001 +10111010110000000 +10110000110100000 +00100001010001010 +01010110001100001 +01110000100100000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000100111000000 +10111000000100001 +00000000000000100 +00110000010100000 +01111110000100000 +10111000010100001 +00000000000000100 +00111000001100000 +01111110000100000 +10000000000000100 +01111100100100000 +01000000000000100 +00000000000000100 +01110100111000000 +01111100110100000 +01110010100100000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +01001110111100000 +00000000000000100 +00000000000000100 +10110000110100001 +00000000000000000 +00000000000000000 +00000000000000000 +01011001100000000 +01111010100100001 +00000000001001010 +10000000000000100 +01110010110100000 +01110110110100000 +01111010110100001 +01111110000100000 +00000000000000100 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +10001100110100111 +10111100001000001 +10111100001000001 +00101101000000110 +10001100101100111 +10111100011000001 +10111100011000001 +00101101010000110 +10110100101000000 +01111110000100000 +10110100101000000 +10111100100100001 +10111110110000000 +01000000000000100 +10111110110000000 +10111000100100001 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +10111110000000000 +10110010010000001 +00111110010000001 +00111000001100000 +10101001110000000 +10110000000100001 +00101111100100000 +00111000101110000 +00110010100111010 +01111010101000000 +01000110010000001 +01000110010000000 +01110010110111010 +01111010111000000 +01110100100100001 +01110100100100001 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00101001110100000 +10001100100100000 +01110010000100000 +10110000110100001 +00000010000011110 +01111000000000000 +01000000101000000 +10110000010000001 +00101101110100000 +10111010000000000 +01001010001000000 +10110110000100001 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +10100111101000000 +00000000000000000 +10010010000000010 +10100111000000001 +10100111111000000 +00000000000000000 +10010010010000010 +10001110011100001 +00100011001100000 +00100001001001010 +10010011000000010 +10001010110100001 +01100011011100000 +00100001011001010 +10010011010000010 +10001010100100001 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 +00000000000000000 diff --git a/rtl/fx68k/nanorom.mem b/rtl/fx68k/nanorom.mem new file mode 100644 index 0000000..df7d74d --- /dev/null +++ b/rtl/fx68k/nanorom.mem @@ -0,0 +1,336 @@ +00000000000000000000000000000000000000000000000010000000000000000000 +00000000000000000000000000000000000000000000000010000000000000000000 +00000000000000000000000000000000000000000000000010000000000000000000 +00000000000000000000000000001000000110011100000000000000101001000001 +00100001000000011000010001001000000110100000000001000000011001001001 +00000001100000000010100000001000000110000000001001000000001001001001 +00100000000000011000010001000000000101000000000010000000100001010000 +11000001000000000000000000001000000100010000000001000000000001010001 +00100001000000011000010000000000000000000000000101000000000000010000 +01000001011000000000100000000110010001000000001100000000110100011000 +01000001011000000000100000000110010001000000001100000001100100011000 +00100001000000011000010000000000000100000000000001000000000001010000 +10100100001000011000001000010000101001110000000001000100110010100001 +01000000000000000000000010000000010100000000001000110001000000000000 +00100001000000011000000000110010100100011111010001100000000001000000 +00100010000000011000000000000000100010000100000000010100000100000011 +00000001011000000000000001000110000000000000000010000000000100000000 +00000000000000000000000000001000000100000000000001000000000001010001 +00000001100000000010100000001000000110000000001001010000001001001001 +00101000000000001000010000000000000000000000000010000000000000000000 +01100010000000011000010010000000010100000000001000110001000000000000 +00000000000000000000000010010010100000000000000100110010000000000000 +00100000000000011000010001001000000110000000001001010000001001001001 +00000000000000000000001000000000100100000000000000110010000001011000 +00010010000000000100100000001000000100000000000010000000000001010001 +00100010000000011100000000000000000001100000000010001000100000000000 +00010010000000000100000000000000010001100000000010000000000000000000 +00000000000000000000000000011001100110100000010001000000011011010001 +10100010110000000000000000000000100000010000010010000100000100000000 +10000000000000000000000000001000000100010000000001000000000001000001 +00100000000000011001000000011010000110000000001001000000001001001001 +00010011000000000000101000010000001001000000010101000000100000110000 +00000001000000000001010000000000000000000000000101100000000000010000 +00100010000000011000001000001000100110000000000001000000000001010001 +00000001000000000010100001010000001001000000010110000000100000110000 +01000001000000000000000000000000000001101010001100000000110000000000 +00110100000000000100000100000000000000000000000010000000000000000000 +00000000000100100000100000000000010000000000000000000001000000011000 +01110101000000000100100000100010000001100000000000000000110100001010 +00100010000000011010000100000000100010000100000000010100000100000011 +11000001000000000000000000001000000100010000000001000000000001010001 +01010011000000000100100000100010000001100000000000000000110100001010 +11000001000000000000000000001001100110110000000001000000011011000001 +01001001110000000000001000001000001000000000000101000000000000100001 +00000000000000000000100000100010010000000000000000110001000100000010 +00010000110000000001010000000000000000011100000010000000000000011000 +01010001110000000001000000011010100100000000000001000000000001000001 +00000000000000000000000001000000000100000000001100010000000001010000 +00001000000000011001001000001000000110100000000001000100000011010001 +01010001110000000001010000001000001000000000000101000000000000110001 +10100010110100100100000001000000000001110000000010000000110000010000 +00000000000100000000000000000010100001001010000101100000100000010000 +00010000110000000001000000000000100000000000010010000100000100000000 +10000000000000000000000000001000000100010000000001000000000001000001 +00000001000000000000000001000000001001000000000101000000100000100000 +00010010000000000000100000001010101000000000000101000000000000110001 +10100000000100111000000000100001100010111010000101100000011010010010 +00100000000000011000000000110010100110000000010000100000001101000010 +00010010000000001100000000000000000000000000000010000000000000000000 +11000001000000000000001000011101100100010000000001000000000001000001 +00010100000000000100000100000000000000000000000010000000000000000000 +10100010110000000100001000000000100000010000010010000100000010000000 +00100000000100111000000000000000100000010010000101000100000100010010 +00100010000000011000000000000000100010000100000000010100000100000011 +00100010100000011001010000010000100100000000001110000100001000000000 +00000000000100000000000000000010100000001010000101000000000000010000 +00100010100000011001000000010010100100000000001110000100001000000000 +00000001000000000000010000000000100000000000010101000100000010010000 +00000000000100100000000000100010000000000100000000110001000100011010 +00100000000000011000000000010000100110000000011000100000001001000000 +00000000000100100000100000100010010000000000000000110001000100011010 +00000000011000000000000000000110000000000000001110000000110100111000 +00011000000000011001001000001000000100000000000001000000000001010001 +00100010000000011100000000000000000001100000000010001000100000000000 +00110000100000001000000100000000100000000000000010000100000100000000 +00000000000100000000000000000010100001000000000101100000100000010000 +10100010110000000100001000010001100000010000000010000000000000000000 +01000001000000000000000000000000000000000000000101000000000000010000 +10000000000000000000000000001000000100010000000001000000000001000001 +00000000000000000000000000001000001000000000000101000000000000110001 +00001000110000000000001000000000000000000000000010000000000000000000 +00010010000000001100000000000000000000000000000010000000000000000000 +00010000000000001010000100000000110001000000000010000100011000000000 +01010001000000011000001000000000000001100000000000000000110000000000 +00001100000000011000001000100001000010100000000101110000000000000011 +01000000000000000000000010000000010100000000001000110000000001000000 +11000001000000000000000000001000001000010000000101000000000000100001 +00000000000000000000000000001000000100011100000001100000000001000001 +00000000000000000000000000000000000000000000000101100000000000000000 +00000000000100000000000000000000100000000000000101000100000100010000 +11101011000000000000000000000000000000010000000010000000000000000000 +01100001000000011001000000011010100100000000000001000000000001000001 +01100010000000011000010010000000010100000000001000110000000001000000 +00000000000000000000000010010010100000000000010100110000000100000000 +01000001000000000000010000011001101000000000000101000100001000110001 +00100000000100111100000000000000000010000010000100100010001000010000 +00010010000000000000000000000010110100000000001110000000000000011000 +00000000000000000000001000010000100100000000011100110010000001011000 +00000000000100000000000000010000111000000000010101000100011000110000 +00000000011000000010100000000110000100000000001101110000000101000000 +00000000000000000000000000000000000000000000000010000000000000000000 +00000001000000000000000000000000010101001010001101000000100001010000 +00000001000000000000010000000000100000000000000101000100001000010000 +01110101000000010000001000000000000001100000000000000000110000000000 +01000001000000000000000010000000010100001010001000110001000000000000 +00100010000000011000000000011010101010000000010101000000001100110001 +00100001000000011000010001010000000100000000010000010000000001010000 +01000001000000000000010000000000100000000110000101000000000000010000 +01000001000000000000000010000000010100001010001000110001000000000000 +00100000000000011000010001010001000000000000011010000000000010001000 +00000001000000000000000001010000000100000000010001110000000001000000 +00010010000000001000000000011010101000000000000101000000000000110001 +00000000000000000000000000001000001000000000000101000000000000110001 +00010010000000000001100000000010000000000000000101100000000000000000 +00010010000000000001000000000010000100000000000101100000000000000000 +00100010000000011100000000001000001000000000000101000000000000100001 +00000001000000000001010000000000001010100000000110000000011000101000 +00000001100000000000100000000000000000000000000101000000000000010000 +00010010000000000000101000001001000100000000001001000000000011010001 +11110101001000000100000000000000000000010000000010000000000000000000 +00000000000000000000010000001001101000000000000101000010000010110001 +00000000000000000000010000000000100000000110000101100000000000000000 +00100010100000001001100000000010000010000100001000000000001000001000 +00100010100000001001000000000010000110000100001000000000001000001000 +00010010000000001000010000000000000000000000001110000000000000011000 +00110100000100101100000000000000000001100000000001100000110000010000 +01110101000000001000000100000000111000000000010010000100000100000000 +01000000000000000000010000010000100110000000011100100000000001011000 +11010011000000000000101000001001000100010000001001000000000011010001 +11110101001000000000000000000000100000010000000010000100000100000000 +01110101000000000100000000000000010000000000010010001000000001000000 +01110101000000000000000000000000110000000000010010001100000101000000 +01110101000000000000000000000000110000000000010010001100011001000000 +01110000000000011100000000000000000001100000001101000000110000000000 +00010000000000001000000000000010100000000000000010000000000000000000 +00010010000000000100000100000000010001000000000010000000000000000000 +01000000000000000000010000010000100110000000011100100010001001011000 +00100000000000011000010000000000000100000000000000100000000001000000 +00000001000000000000000000000000001000000000000101000000000000110000 +00100001000000011100000001011001000110000000011000000000001011001001 +01100001000000011000000000010010100110000000011100100000001101011000 +01100001000000011000010000010010000010000000010101000000001100010000 +00000000000000000000000100000000010010100000001100110001011000011000 +01100001000000011000000000010000100110000000011000100000001001000000 +00000000000000000000000000001000000100011100000001100000000001000001 +00010010000000000000000000010010110110000000001110000010001000011000 +01000001000000000000100000010010010000000000010000110001000100011000 +00010010000000000000010000010000110110000000001110000010001000011000 +01000001000000000000000010000000010100001010001000110000000001000000 +01000001000000000000010000001000101000000110000101000000000000110001 +00000001000000000000010000000000100000000000000101000100001000010000 +00101000000000001000010000000000000000000000000010000000000000000000 +00100010000000011000000000000000100000000000000010000100011000000000 +00100010001000011010000000000000100000000000000010000100000100000000 +11010011001000000100000000010000011000010000000010000000000000000000 +00010010000000000100000000000000010000000000010010001000000001000000 +00001000000000011000001000000000000000000000000101110000000000000011 +00100010110000000000010000001000001000000000000101000000000000110001 +00100010000000011000000000000000100010100000000010000000000000000000 +00100000000000011000000000110001100100011111011001100000000011000010 +00100000000000011000000000001000100110000000001001010000001001000001 +01000001000000000000000000010000000100000000011100100000000001011000 +00000000100000000010100000000000000001000000000101000000100000010000 +00000001000000000000000000011001000100000000011001000000000011000001 +00000000011000000010100001000110000101000000000000010000100101010000 +00100001000000011100000001011001000100000000011001000000000011000001 +01000000000000000000000000000000000101001010001101100000100001000000 +00000000000100000000000000000000100001001010000101100100100100010000 +00000000011000000000000000000010110110000000001100000000001101011000 +01000001000000000000000000000001111001100000001010000000110010100000 +00110010000000011000000000010010100010000000001110000010001000011000 +11000001000000000000000000011001100110110000010001000000011011000001 +00100000000000011010000000100001110000001100001010000000000010000010 +00000000000000000000000000010000000100010101010001100000000001000000 +01000000000000000000000000000000000010100000000010000000011000001000 +00000001000000000000000000000000000001101010001101000000110000010000 +10000000000000000000001000001101100100010000000001000000000001000001 +01110101000000000000000000000000110000000000000010001100000101000000 +11000001000000000000000000001000000100010000000001000000000001000001 +00100010000000011000000000001001101000000010000101000010000010110001 +00100010000100011000000000010010100000000000000101000000000000010000 +11100101000000011100000000001001000100010000001001000000000011010001 +00100100000100111000000000000000100000000000010101100100000100010000 +00100010000100011000000000011010100100000000000000000000000001011001 +00100000000000001000001000000000100000000000000010000100000010000000 +00100010000000011100001000001000100100000000000001000100001001010001 +00010010000000000100000100000000010001000000000010000000000000000000 +10000000000000000000001000011101000100010000000001000000000001000001 +00011000000000011000001000000000100010000000000010000000000000000000 +01000000000000000000000000000000000100000000000001000000000001010000 +01000000000000000000010000010000100110000000011100100000011001001000 +00000000001000000010001000010001010000000000000010001000000000100000 +11100101000000011100000000001000001000010000000101000000000000110001 +01000001000000000000001000010001100000000000000010000000000000000000 +00110100000000000000000000000000110000000000000010001100000101000000 +10000000000000000000001000001000100100010000010001000100000011000001 +01110101000000000100001000000001110000000000010010001000000001000000 +10000000000000000000001000001000100100010000000001000100000011000001 +00110100000000000000000000000000110000000000010010001100000101000000 +00110100000000000000000000000000110000000000010010001100011001000000 +01000000000000000000000000010000000110100000011100100000011001001000 +00000000000100000000000000010000111000000000010101000100000100110010 +00000000000100000000000000100010100001100000000001000000110000011000 +01000000000000000000000000010010000110000000010000100000001101001000 +00000000000000000000000000001000000110000000001001000000001001001001 +01000000000000000000010000000001100000000000000101000010000010010000 +01000000000000000000000000001000000110000000001001010000001001000001 +00000001000000000000000000000000000001101010001101000000110000000000 +11100101000000011000000000010000111001110000010010000100110100100000 +00000000000000000000000000011010101010000000000101000010001000110001 +11000001000000000000001000001101100100010000000001000000000001000001 +00000000000000000000000100000000010000000000000001100001000000000000 +00000000000000000000000000001001100100000000001001000000000011010001 +11000001000000000000010000010001100000010000010010000000011010000000 +00000000000000000000000000000000000000010110000010000000000000000000 +00000000000000000000000000000000000000001100000000000001000000000000 +00100010000000011000000000000000100010100000000010000000000000000000 +00001000000000011000001000000000000000000000000101110000000000000011 +10000000000000000000000000000000000000010000000010000000000000000000 +00000000000000000000010000000000100010000000000010000010001000000000 +00101000000000001000001000000000000000000000000010000000000000000000 +01010011000000000000100000000010100001100000001100000000110000011000 +00000001000010000000000001000000000000000000000101000000000000010000 +00100010000000011000010000001101101000000000000101000000000000110001 +00000000000000000000100000010010010000000000010000110001000100000000 +01000000000000000000000000010000000100000000011100100000000001000000 +00000000000000000000000100010010010000000000010000110001000100000000 +01000000000000000000100000000000010000000000000001000000110000010000 +01010011000000001000010000000000000001100000001100000000110000011000 +01000001000000000000010000001001101000000000000101000000000000110001 +00100100000100011001000000000000100000000000010101000100000100010000 +01100010000000011000100000010010110010000000001100000000110000011000 +00011000000000011000001000000000000000000000000101110000000000000011 +00000000000000000000000000001000000100000000000001000000000001010001 +00010010000000000100000100000000010001000000000010000000000000000000 +00001010000000011000001000000000000000000000000101110000000000000011 +00010010000000000000000000000001110100000010001110000010000010011000 +01100010000000011000100000010010110010000000001100000001000000011000 +01000000000000000000100000000010010000000000001100110001000100011000 +00100010000100011000000001011010100100000000000001000000000001011001 +00000001000000000000010000000001100001001010000101000000100000010000 +00000000000000000000010000000000100101000110001110000000100001011000 +00000000000000000000100000010010010000000000010000110001000100011000 +01010011000000000000100000000001100001100010001100000010110010011000 +01100011000000011000000000010010100100000000011101110000000001011000 +00000000000100000001000000010000100100000000011101000100000101010000 +00100010000100011000000001010010100100000000011100010000000001010000 +00000001000000000000010000000000100000000001000101000100000010010000 +00000001000000000000010000000001100000001111000101000000000000010000 +00000000000000000000000000010010100000000110010101100000000100000000 +00000111000000000000010000010000111000001000010110000100001000100000 +01000000000000000000100000000001110000000000001001000000110010010000 +01001011000000011000001000000000000001100000000000000000110000000000 +00000000000000000000010000000000100010000000000101000000000000010000 +10100100000000011100000000001000000100010000000001000000000001000001 +00010000000000000000000000010000100100000010000010000000000000000000 +00000000000000000000000000001000000100000010000000110010000001000001 +01000000000000000000000000001001100100000000001001010000000011000001 +00000000000000000000000000001001100100000000001001010000000011000001 +00100000000000011000000000010010100010000000010101000000001100010000 +00000000000100000000000000000000101000000000000101000100011000110000 +00000000000100100000100000010010010000000000010000110001000100011000 +01000000000000000000010000010001100000000000010101000010000010010000 +00100001000000011100010100000000110010000000001110001000100000011000 +00000000000000000000001000000000100000000110000101000000000000000000 +00000110000000000000000000000000000000001000000010000000000000000000 +01000000000000000000010000000000100100001010001100110010000001000000 +01000000000000000000000000000000000100001010001100000000000001000000 +01100001000000011000000000000000100001100010000000000000110000000000 +01000001000000000000010000000000100000000110000101010000000000010000 +00101000000000001000010000001000101010000000000101100000000000100001 +10000110000000000000000000001000001000001000000101100000000000100001 +00000000000000000000000000001000000100000000000001000000000001010001 +00100010000100111000100000000000110010100000000001000000110000010000 +00100100000100111100000000001000000100000000000001000000000001011001 +00100011000000011000010100000000010000000000001110001000100000011000 +00000000000000000000000000011001100110100000010001000000011011010001 +00000000000000000000000000000000000000000000000010000000000000000000 +00000000000100100000010001001000100100000000000001000000011001001001 +00100100001000111100001000000000100010000000000101000000000000010000 +01000001000000000000000000010001100000000010000010000000000000000000 +00100010000000011010000000000000110100000000011110001100100100011000 +11100101000000011100000100000000001000010000010101000000011010000000 +00010000000000000000100000000000100001100010001100000000110000000000 +00100010000100111000010001001000000100000000000000000000000001011001 +00010000000000000010000000000000100100000010001110000000000000011000 +11100011000000011100001000010101100000010000000101000000000000000000 +00100000000000011000000000110010100100011111010001100000000001000000 +10000000000100000000000000001000100110110000000001000000000001011001 +11000001000000000000000000001001000100010000001001000000000011010001 +00100100000100111100000000000000000000000000000101100000000000010000 +10000000000100100000000001001001000100010000001001000000000011001001 +11000001000000000000000000000000000000010000000010000000000000000000 +00110100001100100000000000000000100000000000000101100100000100010000 +00000001000001000000000001000000000000000000000101000000000000010000 +00000001000010000000010001000000100000000000000101000100000010010000 +00100000000100111000000000010000101000010111010101000100000100110010 +11100101000000011100000000000000000000010000000010000000000000000000 +11100101000000011000000000000000100000010000010010000100000100000000 +00000000000000000000000000001000001000000000000101000000000000110001 +00000000000000000000000000000000000000000000000010000000000000000000 +00000000000000000000000000000000000000000000000010000000000000000000 +00000000000000000000000000000000000000000000000010000000000000000000 +00000001000000000000000000001000001001100000000001000000110000110001 +00000001000001000000000001001000000100000000000001010000000001011001 +00100000000000001000001000000000100000000000000010000100000010000000 +11000001000000000000010000001001001000010000000101000000000000110001 +00000000000110000000000001000000100000000000000101000100000100010000 +00000000000101000000000001000000100000000000000101000100000100010000 +00000000000010100000000001010000000100000000000101000000000000010000 +00000000000101000000000001001010000100000000000001010000000001011001 +11100101001000011100000000000000010000010000010010001000000000100000 +00100000000000001000000000001000001000000000000110000000000000110001 +00100000000000011000000000000000100000000100011100000101000100011000 +00100000000000011000000000010000110100000000011100000101000100011000 +01100011100000011000000100010010000000000000000101110000000000000011 +01100010000000011000010100000000010000000000001100000001000000011000 +10000000000100100000000001001000000100010000000001000000000001011001 +01100010000000011000010100000010010000000000001100110001000100011000 +01100011000000011000010000010000000100000000011101110000000001011000 +00000000000000000000010000000000100000000110000101000000000000010000 +00000000000000000000000000000000000000011100001110000000000000011000 +10100000000000001000010000001000101000000110000101000000000000100001 +00100000000000011000000000110001100100001111011001100000000011000010 +00000001000000000000010000000001100001001010000101000010100010010000 +00100010001000111000010000010000000100000000011101000000000001010000 +00100100000100111100000000000000000000000000000101000000000000010000 +00100010000100011000010001010000000100000000011100010000000001010000 +01000001000000000000000100010000011000000000000010000000000000000000 +00000000000000000000010000000000100010000000000101000010001000010000 +00100000000100111000000000000000100000000010000100100000000000010000 +00100010000000011000010000001000001000000000000101000000000000110001 +00000001000000000000010000000000100000000000000101000100000010010000 +00000000000000000000000000000000000000000000000010000000000000000000 +00000000000000000000001000000000100100000000000000110010000001011000 +00000000011000000000000000000010110110000000001100000000001101011000 diff --git a/rtl/fx68k/uaddrPla.sv b/rtl/fx68k/uaddrPla.sv new file mode 100644 index 0000000..3be2f74 --- /dev/null +++ b/rtl/fx68k/uaddrPla.sv @@ -0,0 +1,2195 @@ +// +// FX68K +// +// Opcode to uaddr entry routines (A2-A2-A3) PLA +// + +// altera message_off 10230 + + +`timescale 1 ns / 1 ns + +`define NMA_BITS 10 + +`define SFTM1 'h3C7 +`define SRRW1 'h382 +`define SRIW1 'h381 +`define SRRL1 'h386 +`define SRIL1 'h385 +`define BSRI1 'h089 +`define BSRW1 'h0A9 +`define BBCI1 'h308 +`define BBCW1 'h068 +`define RLQL1 'h23B +`define ADRW1 'h006 +`define PINW1 'h21C +`define PDCW1 'h103 +`define ADSW1 'h1C2 +`define AIXW0 'h1E3 +`define ABWW1 'h00A +`define ABLW1 'h1E2 +`define TRAP1 'h1D0 +`define LINK1 'h30B +`define UNLK1 'h119 +`define LUSP1 'h2F5 +`define SUSP1 'h230 +`define TRPV1 'h06D +`define RSET1 'h3A6 +`define B 'h363 +`define STOP1 'h3A2 +`define RTR1 'h12A +`define RTS1 'h126 + + +module pla_lined( + input [3:0] movEa, + input [3:0] col, + + input [15:0] opcode, + input [15:0] lineBmap, + + output palIll, + output logic [`NMA_BITS-1:0] plaA1, + output logic [`NMA_BITS-1:0] plaA2, + output logic [`NMA_BITS-1:0] plaA3 + ); + + wire [3:0] line = opcode[ 15:12]; + wire [2:0] row86 = opcode[8:6]; + + logic [15:0] arIll; + logic [`NMA_BITS-1:0] arA1[ 15:0]; + logic [`NMA_BITS-1:0] arA23[ 15:0]; + logic [`NMA_BITS-1:0] scA3; + + logic illMisc; + logic [`NMA_BITS-1:0] a1Misc; + + /* + reg [`NMA_BITS-1:0] lineMask[ 15:0]; + always_comb begin + integer i; + for( i = 0; i < 16; i = i + 1) + lineMask[i] = { 16{lineBmap[ i]}}; + end + */ + + assign palIll = (| (arIll & lineBmap)); + + // Only line 0 has 3 subs + assign plaA1 = arA1[ line]; + assign plaA2 = arA23[ line]; + assign plaA3 = lineBmap[0] ? scA3 : arA23[ line]; + + + // Simple lines + always_comb begin + // Line 6: Branch + arIll[ 'h6] = 1'b0; + arA23[ 'h6] = 'X; + if( opcode[ 11:8] == 4'h1) + arA1[ 'h6] = (| opcode[7:0]) ? `BSRI1 : `BSRW1; + else + arA1[ 'h6] = (| opcode[7:0]) ? `BBCI1 : `BBCW1; + + // Line 7: moveq + arIll[ 'h7] = opcode[ 8]; + arA23[ 'h7] = 'X; + arA1[ 'h7] = `RLQL1; + + // Line A & F + arIll[ 'ha] = 1'b1; arIll[ 'hf] = 1'b1; + arA1[ 'ha] = 'X; arA1[ 'hf] = 'X; + arA23[ 'ha] = 'X; arA23[ 'hf] = 'X; + + end + + // Special lines + + // Line e: shifts + always_comb begin + if( ~opcode[11] & opcode[7] & opcode[6]) + begin + arA23[ 'he] = `SFTM1; + unique case( col) + 2: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `ADRW1; end + 3: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `PINW1; end + 4: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `PDCW1; end + 5: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `ADSW1; end + 6: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `AIXW0; end + 7: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `ABWW1; end + 8: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `ABLW1; end + default: begin arIll[ 'he] = 1'b1; arA1[ 'he] = 'X; end + endcase + end + else + begin + arA23[ 'he] = 'X; + unique case( opcode[ 7:6]) + 2'b00, + 2'b01: begin + arIll[ 'he] = 1'b0; + arA1[ 'he] = opcode[ 5] ? `SRRW1 : `SRIW1; + end + 2'b10: begin + arIll[ 'he] = 1'b0; + arA1[ 'he] = opcode[ 5] ? `SRRL1 : `SRIL1; + end + 2'b11: begin arIll[ 'he] = 1'b1; arA1[ 'he] = 'X; end + endcase + end + end + + // Misc. line 4 row + always_comb begin + illMisc = 1'b0; + case( opcode[ 5:3]) + 3'b000, + 3'b001: a1Misc = `TRAP1; + 3'b010: a1Misc = `LINK1; + 3'b011: a1Misc = `UNLK1; + 3'b100: a1Misc = `LUSP1; + 3'b101: a1Misc = `SUSP1; + + 3'b110: + case( opcode[ 2:0]) + 3'b110: a1Misc = `TRPV1; + 3'b000: a1Misc = `RSET1; + 3'b001: a1Misc = `B; + 3'b010: a1Misc = `STOP1; + 3'b011: a1Misc = `RTR1; + 3'b111: a1Misc = `RTR1; + 3'b101: a1Misc = `RTS1; + default: begin illMisc = 1'b1; a1Misc = 'X; end + endcase + + default: begin illMisc = 1'b1; a1Misc = 'X; end + endcase + end + +// +// Past here +// + + +// +// Line: 0 +// +always_comb begin + +if( (opcode[11:6] & 'h1F) == 'h8) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1CC; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h37) == 'h0) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1CC; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h1F) == 'h9) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1CC; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h37) == 'h1) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1CC; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h1F) == 'hA) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h10C; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00B; scA3 = 'h29D; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00F; scA3 = 'h29D; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h179; scA3 = 'h29D; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1C6; scA3 = 'h29D; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E7; scA3 = 'h29D; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00E; scA3 = 'h29D; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E6; scA3 = 'h29D; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h37) == 'h2) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h10C; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00B; scA3 = 'h29D; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00F; scA3 = 'h29D; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h179; scA3 = 'h29D; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1C6; scA3 = 'h29D; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E7; scA3 = 'h29D; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00E; scA3 = 'h29D; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E6; scA3 = 'h29D; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h37) == 'h10) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h37) == 'h11) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h37) == 'h12) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h10C; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00B; scA3 = 'h29D; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00F; scA3 = 'h29D; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h179; scA3 = 'h29D; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1C6; scA3 = 'h29D; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E7; scA3 = 'h29D; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00E; scA3 = 'h29D; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E6; scA3 = 'h29D; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h7) == 'h4) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E7; arA23[ 'h0] = 'X; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1D2; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h006; arA23[ 'h0] = 'X; scA3 = 'h215; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h21C; arA23[ 'h0] = 'X; scA3 = 'h215; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h103; arA23[ 'h0] = 'X; scA3 = 'h215; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1C2; arA23[ 'h0] = 'X; scA3 = 'h215; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E3; arA23[ 'h0] = 'X; scA3 = 'h215; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h00A; arA23[ 'h0] = 'X; scA3 = 'h215; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E2; arA23[ 'h0] = 'X; scA3 = 'h215; end + 9: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1C2; arA23[ 'h0] = 'X; scA3 = 'h215; end + 10: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E3; arA23[ 'h0] = 'X; scA3 = 'h215; end + 11: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h0EA; arA23[ 'h0] = 'h0AB; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h7) == 'h5) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3EF; arA23[ 'h0] = 'X; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1D6; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h006; arA23[ 'h0] = 'X; scA3 = 'h081; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h21C; arA23[ 'h0] = 'X; scA3 = 'h081; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h103; arA23[ 'h0] = 'X; scA3 = 'h081; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1C2; arA23[ 'h0] = 'X; scA3 = 'h081; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E3; arA23[ 'h0] = 'X; scA3 = 'h081; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h00A; arA23[ 'h0] = 'X; scA3 = 'h081; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E2; arA23[ 'h0] = 'X; scA3 = 'h081; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h7) == 'h7) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3EF; arA23[ 'h0] = 'X; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1CE; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h006; arA23[ 'h0] = 'X; scA3 = 'h081; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h21C; arA23[ 'h0] = 'X; scA3 = 'h081; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h103; arA23[ 'h0] = 'X; scA3 = 'h081; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1C2; arA23[ 'h0] = 'X; scA3 = 'h081; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E3; arA23[ 'h0] = 'X; scA3 = 'h081; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h00A; arA23[ 'h0] = 'X; scA3 = 'h081; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E2; arA23[ 'h0] = 'X; scA3 = 'h081; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h7) == 'h6) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3EB; arA23[ 'h0] = 'X; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1CA; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h006; arA23[ 'h0] = 'X; scA3 = 'h069; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h21C; arA23[ 'h0] = 'X; scA3 = 'h069; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h103; arA23[ 'h0] = 'X; scA3 = 'h069; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1C2; arA23[ 'h0] = 'X; scA3 = 'h069; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E3; arA23[ 'h0] = 'X; scA3 = 'h069; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h00A; arA23[ 'h0] = 'X; scA3 = 'h069; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E2; arA23[ 'h0] = 'X; scA3 = 'h069; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( opcode[11:6] == 'h20) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h3E7; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h215; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h215; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h215; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h215; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h215; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h215; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h215; end + 9: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h215; end + 10: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h215; end + 11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( opcode[11:6] == 'h21) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h3EF; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h081; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h081; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h081; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h081; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h081; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h081; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h081; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( opcode[11:6] == 'h23) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h3EF; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h081; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h081; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h081; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h081; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h081; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h081; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h081; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( opcode[11:6] == 'h22) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h3EB; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h069; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h069; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h069; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h069; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h069; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h069; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h069; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( opcode[11:6] == 'h30) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h108; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h087; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h087; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h087; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h087; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h087; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h087; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h087; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( opcode[11:6] == 'h31) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h108; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h087; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h087; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h087; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h087; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h087; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h087; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h087; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else if( opcode[11:6] == 'h32) begin + unique case ( col) + 0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h104; scA3 = 'X; end + 1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00B; scA3 = 'h08F; end + 3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00F; scA3 = 'h08F; end + 4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h179; scA3 = 'h08F; end + 5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1C6; scA3 = 'h08F; end + 6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E7; scA3 = 'h08F; end + 7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00E; scA3 = 'h08F; end + 8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E6; scA3 = 'h08F; end + 9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + 11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + endcase +end + +else begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X ; arA23[ 'h0] = 'X; scA3 = 'X; end + +end + + +// +// Line: 4 +// +always_comb begin + +if( (opcode[11:6] & 'h27) == 'h0) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h133; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h2B8; end + 3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h2B8; end + 4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h2B8; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h2B8; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h2B8; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h2B8; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h2B8; end + 9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h27) == 'h1) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h133; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h2B8; end + 3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h2B8; end + 4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h2B8; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h2B8; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h2B8; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h2B8; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h2B8; end + 9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h27) == 'h2) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h137; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00B; arA23[ 'h4] = 'h2BC; end + 3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00F; arA23[ 'h4] = 'h2BC; end + 4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h179; arA23[ 'h4] = 'h2BC; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C6; arA23[ 'h4] = 'h2BC; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E7; arA23[ 'h4] = 'h2BC; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00E; arA23[ 'h4] = 'h2BC; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E6; arA23[ 'h4] = 'h2BC; end + 9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( opcode[11:6] == 'h3) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3A5; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h3A1; end + 3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h3A1; end + 4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h3A1; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h3A1; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h3A1; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h3A1; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h3A1; end + 9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( opcode[11:6] == 'h13) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h301; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h159; end + 3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h159; end + 4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h159; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h159; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h159; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h159; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h159; end + 9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h159; end + 10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h159; end + 11: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h0EA; arA23[ 'h4] = 'h301; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( opcode[11:6] == 'h1B) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h301; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h159; end + 3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h159; end + 4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h159; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h159; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h159; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h159; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h159; end + 9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h159; end + 10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h159; end + 11: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h0EA; arA23[ 'h4] = 'h301; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( opcode[11:6] == 'h20) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h13B; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h15C; end + 3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h15C; end + 4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h15C; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h15C; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h15C; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h15C; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h15C; end + 9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( opcode[11:6] == 'h21) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h341; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h17C; arA23[ 'h4] = 'X; end + 3: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 4: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h17D; arA23[ 'h4] = 'X; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FF; arA23[ 'h4] = 'X; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h178; arA23[ 'h4] = 'X; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FA; arA23[ 'h4] = 'X; end + 9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h17D; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FF; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( opcode[11:6] == 'h22) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h133; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3A0; arA23[ 'h4] = 'X; end + 3: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3A4; arA23[ 'h4] = 'X; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F1; arA23[ 'h4] = 'X; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h325; arA23[ 'h4] = 'X; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1ED; arA23[ 'h4] = 'X; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E5; arA23[ 'h4] = 'X; end + 9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( opcode[11:6] == 'h23) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h232; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3A0; arA23[ 'h4] = 'X; end + 3: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3A4; arA23[ 'h4] = 'X; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F1; arA23[ 'h4] = 'X; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h325; arA23[ 'h4] = 'X; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1ED; arA23[ 'h4] = 'X; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E5; arA23[ 'h4] = 'X; end + 9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( opcode[11:6] == 'h28) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h12D; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h3C3; end + 3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h3C3; end + 4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h3C3; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h3C3; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h3C3; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h3C3; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h3C3; end + 9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( opcode[11:6] == 'h29) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h12D; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h3C3; end + 3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h3C3; end + 4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h3C3; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h3C3; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h3C3; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h3C3; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h3C3; end + 9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( opcode[11:6] == 'h2A) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h125; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00B; arA23[ 'h4] = 'h3CB; end + 3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00F; arA23[ 'h4] = 'h3CB; end + 4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h179; arA23[ 'h4] = 'h3CB; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C6; arA23[ 'h4] = 'h3CB; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E7; arA23[ 'h4] = 'h3CB; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00E; arA23[ 'h4] = 'h3CB; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E6; arA23[ 'h4] = 'h3CB; end + 9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( opcode[11:6] == 'h2B) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h345; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h343; end + 3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h343; end + 4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h343; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h343; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h343; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h343; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h343; end + 9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h3E) == 'h32) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h127; arA23[ 'h4] = 'X; end + 3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h123; arA23[ 'h4] = 'X; end + 4: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FD; arA23[ 'h4] = 'X; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F5; arA23[ 'h4] = 'X; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F9; arA23[ 'h4] = 'X; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E9; arA23[ 'h4] = 'X; end + 9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FD; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F5; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h7) == 'h6) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h152; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h151; end + 3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h151; end + 4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h151; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h151; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h151; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h151; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h151; end + 9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h151; end + 10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h151; end + 11: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h0EA; arA23[ 'h4] = 'h152; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( (opcode[11:6] & 'h7) == 'h7) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2F1; arA23[ 'h4] = 'X; end + 3: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 4: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2F2; arA23[ 'h4] = 'X; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FB; arA23[ 'h4] = 'X; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h275; arA23[ 'h4] = 'X; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3E4; arA23[ 'h4] = 'X; end + 9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2F2; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FB; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( opcode[11:6] == 'h3A) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h273; arA23[ 'h4] = 'X; end + 3: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 4: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2B0; arA23[ 'h4] = 'X; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F3; arA23[ 'h4] = 'X; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h293; arA23[ 'h4] = 'X; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F2; arA23[ 'h4] = 'X; end + 9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2B0; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F3; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( opcode[11:6] == 'h3B) begin + unique case ( col) + 0: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h255; arA23[ 'h4] = 'X; end + 3: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 4: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + 5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2B4; arA23[ 'h4] = 'X; end + 6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F7; arA23[ 'h4] = 'X; end + 7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h297; arA23[ 'h4] = 'X; end + 8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F6; arA23[ 'h4] = 'X; end + 9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2B4; arA23[ 'h4] = 'X; end + 10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F7; arA23[ 'h4] = 'X; end + 11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + endcase +end + +else if( opcode[11:6] == 'h39) begin + arIll[ 'h4] = illMisc; arA1[ 'h4] = a1Misc ; arA23[ 'h4] = 'X; +end + +else begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X ; arA23[ 'h4] = 'X; end + +end + +always_comb begin + +// +// Line: 1 +// +unique case( movEa) + +0: // Row: 0 + unique case ( col) + 0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h121; arA23[ 'h1] = 'X; end + 1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + 2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h29B; end + 3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h29B; end + 4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h29B; end + 5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h29B; end + 6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h29B; end + 7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h29B; end + 8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h29B; end + 9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h29B; end + 10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h29B; end + 11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h121; end + default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + endcase + +2: // Row: 2 + unique case ( col) + 0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h2FA; arA23[ 'h1] = 'X; end + 1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + 2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h3AB; end + 3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h3AB; end + 4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h3AB; end + 5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h3AB; end + 6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h3AB; end + 7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h3AB; end + 8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h3AB; end + 9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h3AB; end + 10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h3AB; end + 11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h2FA; end + default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + endcase + +3: // Row: 3 + unique case ( col) + 0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h2FE; arA23[ 'h1] = 'X; end + 1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + 2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h3AF; end + 3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h3AF; end + 4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h3AF; end + 5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h3AF; end + 6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h3AF; end + 7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h3AF; end + 8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h3AF; end + 9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h3AF; end + 10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h3AF; end + 11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h2FE; end + default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + endcase + +4: // Row: 4 + unique case ( col) + 0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h2F8; arA23[ 'h1] = 'X; end + 1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + 2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h38B; end + 3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h38B; end + 4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h38B; end + 5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h38B; end + 6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h38B; end + 7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h38B; end + 8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h38B; end + 9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h38B; end + 10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h38B; end + 11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h2F8; end + default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + endcase + +5: // Row: 5 + unique case ( col) + 0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h2DA; arA23[ 'h1] = 'X; end + 1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + 2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h38A; end + 3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h38A; end + 4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h38A; end + 5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h38A; end + 6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h38A; end + 7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h38A; end + 8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h38A; end + 9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h38A; end + 10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h38A; end + 11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h2DA; end + default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + endcase + +6: // Row: 6 + unique case ( col) + 0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1EB; arA23[ 'h1] = 'X; end + 1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + 2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h298; end + 3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h298; end + 4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h298; end + 5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h298; end + 6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h298; end + 7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h298; end + 8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h298; end + 9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h298; end + 10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h298; end + 11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h1EB; end + default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + endcase + +7: // Row: 7 + unique case ( col) + 0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h2D9; arA23[ 'h1] = 'X; end + 1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + 2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h388; end + 3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h388; end + 4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h388; end + 5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h388; end + 6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h388; end + 7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h388; end + 8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h388; end + 9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h388; end + 10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h388; end + 11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h2D9; end + default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + endcase + +8: // Row: 8 + unique case ( col) + 0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1EA; arA23[ 'h1] = 'X; end + 1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + 2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h32B; end + 3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h32B; end + 4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h32B; end + 5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h32B; end + 6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h32B; end + 7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h32B; end + 8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h32B; end + 9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h32B; end + 10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h32B; end + 11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h1EA; end + default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end + endcase +default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X ; arA23[ 'h1] = 'X; end +endcase + +// +// Line: 2 +// +unique case( movEa) + +0: // Row: 0 + unique case ( col) + 0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h129; arA23[ 'h2] = 'X; end + 1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h129; arA23[ 'h2] = 'X; end + 2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h29F; end + 3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h29F; end + 4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h29F; end + 5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29F; end + 6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29F; end + 7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h29F; end + 8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h29F; end + 9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29F; end + 10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29F; end + 11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h129; end + default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X ; arA23[ 'h2] = 'X; end + endcase + +1: // Row: 1 + unique case ( col) + 0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h129; arA23[ 'h2] = 'X; end + 1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h129; arA23[ 'h2] = 'X; end + 2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h29F; end + 3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h29F; end + 4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h29F; end + 5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29F; end + 6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29F; end + 7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h29F; end + 8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h29F; end + 9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29F; end + 10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29F; end + 11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h129; end + default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X ; arA23[ 'h2] = 'X; end + endcase + +2: // Row: 2 + unique case ( col) + 0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2F9; arA23[ 'h2] = 'X; end + 1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2F9; arA23[ 'h2] = 'X; end + 2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h3A9; end + 3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h3A9; end + 4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h3A9; end + 5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h3A9; end + 6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h3A9; end + 7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h3A9; end + 8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h3A9; end + 9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h3A9; end + 10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h3A9; end + 11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h2F9; end + default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X ; arA23[ 'h2] = 'X; end + endcase + +3: // Row: 3 + unique case ( col) + 0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2FD; arA23[ 'h2] = 'X; end + 1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2FD; arA23[ 'h2] = 'X; end + 2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h3AD; end + 3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h3AD; end + 4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h3AD; end + 5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h3AD; end + 6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h3AD; end + 7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h3AD; end + 8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h3AD; end + 9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h3AD; end + 10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h3AD; end + 11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h2FD; end + default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X ; arA23[ 'h2] = 'X; end + endcase + +4: // Row: 4 + unique case ( col) + 0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2FC; arA23[ 'h2] = 'X; end + 1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2FC; arA23[ 'h2] = 'X; end + 2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h38F; end + 3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h38F; end + 4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h38F; end + 5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38F; end + 6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38F; end + 7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h38F; end + 8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h38F; end + 9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38F; end + 10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38F; end + 11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h2FC; end + default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X ; arA23[ 'h2] = 'X; end + endcase + +5: // Row: 5 + unique case ( col) + 0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2DE; arA23[ 'h2] = 'X; end + 1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2DE; arA23[ 'h2] = 'X; end + 2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h38E; end + 3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h38E; end + 4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h38E; end + 5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38E; end + 6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38E; end + 7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h38E; end + 8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h38E; end + 9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38E; end + 10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38E; end + 11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h2DE; end + default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X ; arA23[ 'h2] = 'X; end + endcase + +6: // Row: 6 + unique case ( col) + 0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1EF; arA23[ 'h2] = 'X; end + 1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1EF; arA23[ 'h2] = 'X; end + 2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h29C; end + 3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h29C; end + 4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h29C; end + 5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29C; end + 6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29C; end + 7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h29C; end + 8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h29C; end + 9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29C; end + 10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29C; end + 11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h1EF; end + default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X ; arA23[ 'h2] = 'X; end + endcase + +7: // Row: 7 + unique case ( col) + 0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2DD; arA23[ 'h2] = 'X; end + 1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2DD; arA23[ 'h2] = 'X; end + 2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h38C; end + 3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h38C; end + 4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h38C; end + 5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38C; end + 6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38C; end + 7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h38C; end + 8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h38C; end + 9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38C; end + 10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38C; end + 11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h2DD; end + default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X ; arA23[ 'h2] = 'X; end + endcase + +8: // Row: 8 + unique case ( col) + 0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1EE; arA23[ 'h2] = 'X; end + 1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1EE; arA23[ 'h2] = 'X; end + 2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h30F; end + 3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h30F; end + 4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h30F; end + 5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h30F; end + 6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h30F; end + 7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h30F; end + 8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h30F; end + 9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h30F; end + 10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h30F; end + 11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h1EE; end + default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X ; arA23[ 'h2] = 'X; end + endcase +default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X ; arA23[ 'h2] = 'X; end +endcase + +// +// Line: 3 +// +unique case( movEa) + +0: // Row: 0 + unique case ( col) + 0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h121; arA23[ 'h3] = 'X; end + 1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h121; arA23[ 'h3] = 'X; end + 2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h29B; end + 3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h29B; end + 4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h29B; end + 5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h29B; end + 6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h29B; end + 7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h29B; end + 8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h29B; end + 9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h29B; end + 10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h29B; end + 11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h121; end + default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X ; arA23[ 'h3] = 'X; end + endcase + +1: // Row: 1 + unique case ( col) + 0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h279; arA23[ 'h3] = 'X; end + 1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h279; arA23[ 'h3] = 'X; end + 2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h158; end + 3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h158; end + 4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h158; end + 5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h158; end + 6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h158; end + 7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h158; end + 8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h158; end + 9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h158; end + 10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h158; end + 11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h279; end + default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X ; arA23[ 'h3] = 'X; end + endcase + +2: // Row: 2 + unique case ( col) + 0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2FA; arA23[ 'h3] = 'X; end + 1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2FA; arA23[ 'h3] = 'X; end + 2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h3AB; end + 3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h3AB; end + 4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h3AB; end + 5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h3AB; end + 6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h3AB; end + 7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h3AB; end + 8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h3AB; end + 9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h3AB; end + 10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h3AB; end + 11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h2FA; end + default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X ; arA23[ 'h3] = 'X; end + endcase + +3: // Row: 3 + unique case ( col) + 0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2FE; arA23[ 'h3] = 'X; end + 1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2FE; arA23[ 'h3] = 'X; end + 2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h3AF; end + 3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h3AF; end + 4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h3AF; end + 5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h3AF; end + 6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h3AF; end + 7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h3AF; end + 8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h3AF; end + 9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h3AF; end + 10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h3AF; end + 11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h2FE; end + default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X ; arA23[ 'h3] = 'X; end + endcase + +4: // Row: 4 + unique case ( col) + 0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2F8; arA23[ 'h3] = 'X; end + 1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2F8; arA23[ 'h3] = 'X; end + 2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h38B; end + 3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h38B; end + 4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h38B; end + 5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h38B; end + 6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h38B; end + 7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h38B; end + 8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h38B; end + 9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h38B; end + 10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h38B; end + 11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h2F8; end + default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X ; arA23[ 'h3] = 'X; end + endcase + +5: // Row: 5 + unique case ( col) + 0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2DA; arA23[ 'h3] = 'X; end + 1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2DA; arA23[ 'h3] = 'X; end + 2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h38A; end + 3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h38A; end + 4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h38A; end + 5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h38A; end + 6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h38A; end + 7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h38A; end + 8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h38A; end + 9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h38A; end + 10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h38A; end + 11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h2DA; end + default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X ; arA23[ 'h3] = 'X; end + endcase + +6: // Row: 6 + unique case ( col) + 0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1EB; arA23[ 'h3] = 'X; end + 1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1EB; arA23[ 'h3] = 'X; end + 2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h298; end + 3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h298; end + 4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h298; end + 5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h298; end + 6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h298; end + 7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h298; end + 8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h298; end + 9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h298; end + 10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h298; end + 11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h1EB; end + default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X ; arA23[ 'h3] = 'X; end + endcase + +7: // Row: 7 + unique case ( col) + 0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2D9; arA23[ 'h3] = 'X; end + 1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2D9; arA23[ 'h3] = 'X; end + 2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h388; end + 3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h388; end + 4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h388; end + 5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h388; end + 6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h388; end + 7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h388; end + 8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h388; end + 9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h388; end + 10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h388; end + 11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h2D9; end + default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X ; arA23[ 'h3] = 'X; end + endcase + +8: // Row: 8 + unique case ( col) + 0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1EA; arA23[ 'h3] = 'X; end + 1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1EA; arA23[ 'h3] = 'X; end + 2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h32B; end + 3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h32B; end + 4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h32B; end + 5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h32B; end + 6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h32B; end + 7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h32B; end + 8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h32B; end + 9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h32B; end + 10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h32B; end + 11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h1EA; end + default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X ; arA23[ 'h3] = 'X; end + endcase +default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X ; arA23[ 'h3] = 'X; end +endcase + +// +// Line: 5 +// +unique case( row86) + +3'b000: // Row: 0 + unique case ( col) + 0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2D8; arA23[ 'h5] = 'X; end + 1: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X ; arA23[ 'h5] = 'X; end + 2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h2F3; end + 3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h2F3; end + 4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h2F3; end + 5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h2F3; end + 6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h2F3; end + 7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h2F3; end + 8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h2F3; end + default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X ; arA23[ 'h5] = 'X; end + endcase + +3'b001: // Row: 1 + unique case ( col) + 0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2D8; arA23[ 'h5] = 'X; end + 1: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = 'X; end + 2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h2F3; end + 3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h2F3; end + 4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h2F3; end + 5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h2F3; end + 6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h2F3; end + 7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h2F3; end + 8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h2F3; end + default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X ; arA23[ 'h5] = 'X; end + endcase + +3'b010: // Row: 2 + unique case ( col) + 0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = 'X; end + 1: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = 'X; end + 2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00B; arA23[ 'h5] = 'h2F7; end + 3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00F; arA23[ 'h5] = 'h2F7; end + 4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h179; arA23[ 'h5] = 'h2F7; end + 5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C6; arA23[ 'h5] = 'h2F7; end + 6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E7; arA23[ 'h5] = 'h2F7; end + 7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00E; arA23[ 'h5] = 'h2F7; end + 8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E6; arA23[ 'h5] = 'h2F7; end + default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X ; arA23[ 'h5] = 'X; end + endcase + +3'b011: // Row: 3 + unique case ( col) + 0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h384; arA23[ 'h5] = 'X; end + 1: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h06C; arA23[ 'h5] = 'X; end + 2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h380; end + 3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h380; end + 4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h380; end + 5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h380; end + 6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h380; end + 7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h380; end + 8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h380; end + default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X ; arA23[ 'h5] = 'X; end + endcase + +3'b100: // Row: 4 + unique case ( col) + 0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2D8; arA23[ 'h5] = 'X; end + 1: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X ; arA23[ 'h5] = 'X; end + 2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h2F3; end + 3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h2F3; end + 4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h2F3; end + 5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h2F3; end + 6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h2F3; end + 7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h2F3; end + 8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h2F3; end + default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X ; arA23[ 'h5] = 'X; end + endcase + +3'b101: // Row: 5 + unique case ( col) + 0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2D8; arA23[ 'h5] = 'X; end + 1: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = 'X; end + 2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h2F3; end + 3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h2F3; end + 4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h2F3; end + 5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h2F3; end + 6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h2F3; end + 7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h2F3; end + 8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h2F3; end + default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X ; arA23[ 'h5] = 'X; end + endcase + +3'b110: // Row: 6 + unique case ( col) + 0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = 'X; end + 1: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = 'X; end + 2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00B; arA23[ 'h5] = 'h2F7; end + 3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00F; arA23[ 'h5] = 'h2F7; end + 4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h179; arA23[ 'h5] = 'h2F7; end + 5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C6; arA23[ 'h5] = 'h2F7; end + 6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E7; arA23[ 'h5] = 'h2F7; end + 7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00E; arA23[ 'h5] = 'h2F7; end + 8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E6; arA23[ 'h5] = 'h2F7; end + default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X ; arA23[ 'h5] = 'X; end + endcase + +3'b111: // Row: 7 + unique case ( col) + 0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h384; arA23[ 'h5] = 'X; end + 1: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h06C; arA23[ 'h5] = 'X; end + 2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h380; end + 3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h380; end + 4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h380; end + 5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h380; end + 6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h380; end + 7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h380; end + 8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h380; end + default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X ; arA23[ 'h5] = 'X; end + endcase +endcase + +// +// Line: 8 +// +unique case( row86) + +3'b000: // Row: 0 + unique case ( col) + 0: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C1; arA23[ 'h8] = 'X; end + 1: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + 2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h1C3; end + 3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h1C3; end + 4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h1C3; end + 5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h1C3; end + 6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h1C3; end + 7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h1C3; end + 8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h1C3; end + 9: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h1C3; end + 10: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h1C3; end + 11: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0EA; arA23[ 'h8] = 'h1C1; end + default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + endcase + +3'b001: // Row: 1 + unique case ( col) + 0: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C1; arA23[ 'h8] = 'X; end + 1: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + 2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h1C3; end + 3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h1C3; end + 4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h1C3; end + 5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h1C3; end + 6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h1C3; end + 7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h1C3; end + 8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h1C3; end + 9: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h1C3; end + 10: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h1C3; end + 11: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0EA; arA23[ 'h8] = 'h1C1; end + default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + endcase + +3'b010: // Row: 2 + unique case ( col) + 0: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C5; arA23[ 'h8] = 'X; end + 1: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + 2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00B; arA23[ 'h8] = 'h1CB; end + 3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00F; arA23[ 'h8] = 'h1CB; end + 4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h179; arA23[ 'h8] = 'h1CB; end + 5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C6; arA23[ 'h8] = 'h1CB; end + 6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E7; arA23[ 'h8] = 'h1CB; end + 7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00E; arA23[ 'h8] = 'h1CB; end + 8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E6; arA23[ 'h8] = 'h1CB; end + 9: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C6; arA23[ 'h8] = 'h1CB; end + 10: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E7; arA23[ 'h8] = 'h1CB; end + 11: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0A7; arA23[ 'h8] = 'h1C5; end + default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + endcase + +3'b011: // Row: 3 + unique case ( col) + 0: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0A6; arA23[ 'h8] = 'X; end + 1: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + 2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h0A4; end + 3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h0A4; end + 4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h0A4; end + 5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h0A4; end + 6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h0A4; end + 7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h0A4; end + 8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h0A4; end + 9: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h0A4; end + 10: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h0A4; end + 11: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0EA; arA23[ 'h8] = 'h0A6; end + default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + endcase + +3'b100: // Row: 4 + unique case ( col) + 0: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1CD; arA23[ 'h8] = 'X; end + 1: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h107; arA23[ 'h8] = 'X; end + 2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h299; end + 3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h299; end + 4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h299; end + 5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h299; end + 6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h299; end + 7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h299; end + 8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h299; end + 9: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + 10: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + 11: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + endcase + +3'b101: // Row: 5 + unique case ( col) + 0: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + 1: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + 2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h299; end + 3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h299; end + 4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h299; end + 5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h299; end + 6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h299; end + 7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h299; end + 8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h299; end + 9: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + 10: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + 11: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + endcase + +3'b110: // Row: 6 + unique case ( col) + 0: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + 1: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + 2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00B; arA23[ 'h8] = 'h29D; end + 3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00F; arA23[ 'h8] = 'h29D; end + 4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h179; arA23[ 'h8] = 'h29D; end + 5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C6; arA23[ 'h8] = 'h29D; end + 6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E7; arA23[ 'h8] = 'h29D; end + 7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00E; arA23[ 'h8] = 'h29D; end + 8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E6; arA23[ 'h8] = 'h29D; end + 9: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + 10: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + 11: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + endcase + +3'b111: // Row: 7 + unique case ( col) + 0: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0AE; arA23[ 'h8] = 'X; end + 1: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + 2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h0AC; end + 3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h0AC; end + 4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h0AC; end + 5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h0AC; end + 6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h0AC; end + 7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h0AC; end + 8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h0AC; end + 9: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h0AC; end + 10: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h0AC; end + 11: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0EA; arA23[ 'h8] = 'h0AE; end + default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X ; arA23[ 'h8] = 'X; end + endcase +endcase + +// +// Line: 9 +// +unique case( row86) + +3'b000: // Row: 0 + unique case ( col) + 0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C1; arA23[ 'h9] = 'X; end + 1: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + 2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h006; arA23[ 'h9] = 'h1C3; end + 3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h21C; arA23[ 'h9] = 'h1C3; end + 4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h103; arA23[ 'h9] = 'h1C3; end + 5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C3; end + 6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C3; end + 7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00A; arA23[ 'h9] = 'h1C3; end + 8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E2; arA23[ 'h9] = 'h1C3; end + 9: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C3; end + 10: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C3; end + 11: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h0EA; arA23[ 'h9] = 'h1C1; end + default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + endcase + +3'b001: // Row: 1 + unique case ( col) + 0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C1; arA23[ 'h9] = 'X; end + 1: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C1; arA23[ 'h9] = 'X; end + 2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h006; arA23[ 'h9] = 'h1C3; end + 3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h21C; arA23[ 'h9] = 'h1C3; end + 4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h103; arA23[ 'h9] = 'h1C3; end + 5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C3; end + 6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C3; end + 7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00A; arA23[ 'h9] = 'h1C3; end + 8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E2; arA23[ 'h9] = 'h1C3; end + 9: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C3; end + 10: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C3; end + 11: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h0EA; arA23[ 'h9] = 'h1C1; end + default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + endcase + +3'b010: // Row: 2 + unique case ( col) + 0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C5; arA23[ 'h9] = 'X; end + 1: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C5; arA23[ 'h9] = 'X; end + 2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00B; arA23[ 'h9] = 'h1CB; end + 3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00F; arA23[ 'h9] = 'h1CB; end + 4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h179; arA23[ 'h9] = 'h1CB; end + 5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C6; arA23[ 'h9] = 'h1CB; end + 6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E7; arA23[ 'h9] = 'h1CB; end + 7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00E; arA23[ 'h9] = 'h1CB; end + 8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E6; arA23[ 'h9] = 'h1CB; end + 9: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C6; arA23[ 'h9] = 'h1CB; end + 10: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E7; arA23[ 'h9] = 'h1CB; end + 11: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h0A7; arA23[ 'h9] = 'h1C5; end + default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + endcase + +3'b011: // Row: 3 + unique case ( col) + 0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C9; arA23[ 'h9] = 'X; end + 1: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C9; arA23[ 'h9] = 'X; end + 2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h006; arA23[ 'h9] = 'h1C7; end + 3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h21C; arA23[ 'h9] = 'h1C7; end + 4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h103; arA23[ 'h9] = 'h1C7; end + 5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C7; end + 6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C7; end + 7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00A; arA23[ 'h9] = 'h1C7; end + 8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E2; arA23[ 'h9] = 'h1C7; end + 9: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C7; end + 10: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C7; end + 11: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h0EA; arA23[ 'h9] = 'h1C9; end + default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + endcase + +3'b100: // Row: 4 + unique case ( col) + 0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C1; arA23[ 'h9] = 'X; end + 1: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h10F; arA23[ 'h9] = 'X; end + 2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h006; arA23[ 'h9] = 'h299; end + 3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h21C; arA23[ 'h9] = 'h299; end + 4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h103; arA23[ 'h9] = 'h299; end + 5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h299; end + 6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h299; end + 7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00A; arA23[ 'h9] = 'h299; end + 8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E2; arA23[ 'h9] = 'h299; end + 9: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + 10: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + 11: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + endcase + +3'b101: // Row: 5 + unique case ( col) + 0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C1; arA23[ 'h9] = 'X; end + 1: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h10F; arA23[ 'h9] = 'X; end + 2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h006; arA23[ 'h9] = 'h299; end + 3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h21C; arA23[ 'h9] = 'h299; end + 4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h103; arA23[ 'h9] = 'h299; end + 5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h299; end + 6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h299; end + 7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00A; arA23[ 'h9] = 'h299; end + 8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E2; arA23[ 'h9] = 'h299; end + 9: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + 10: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + 11: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + endcase + +3'b110: // Row: 6 + unique case ( col) + 0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C5; arA23[ 'h9] = 'X; end + 1: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h10B; arA23[ 'h9] = 'X; end + 2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00B; arA23[ 'h9] = 'h29D; end + 3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00F; arA23[ 'h9] = 'h29D; end + 4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h179; arA23[ 'h9] = 'h29D; end + 5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C6; arA23[ 'h9] = 'h29D; end + 6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E7; arA23[ 'h9] = 'h29D; end + 7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00E; arA23[ 'h9] = 'h29D; end + 8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E6; arA23[ 'h9] = 'h29D; end + 9: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + 10: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + 11: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + endcase + +3'b111: // Row: 7 + unique case ( col) + 0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C5; arA23[ 'h9] = 'X; end + 1: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C5; arA23[ 'h9] = 'X; end + 2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00B; arA23[ 'h9] = 'h1CB; end + 3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00F; arA23[ 'h9] = 'h1CB; end + 4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h179; arA23[ 'h9] = 'h1CB; end + 5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C6; arA23[ 'h9] = 'h1CB; end + 6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E7; arA23[ 'h9] = 'h1CB; end + 7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00E; arA23[ 'h9] = 'h1CB; end + 8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E6; arA23[ 'h9] = 'h1CB; end + 9: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C6; arA23[ 'h9] = 'h1CB; end + 10: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E7; arA23[ 'h9] = 'h1CB; end + 11: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h0A7; arA23[ 'h9] = 'h1C5; end + default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X ; arA23[ 'h9] = 'X; end + endcase +endcase + +// +// Line: B +// +unique case( row86) + +3'b000: // Row: 0 + unique case ( col) + 0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D1; arA23[ 'hb] = 'X; end + 1: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + 2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h006; arA23[ 'hb] = 'h1D3; end + 3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h21C; arA23[ 'hb] = 'h1D3; end + 4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h103; arA23[ 'hb] = 'h1D3; end + 5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1D3; end + 6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1D3; end + 7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00A; arA23[ 'hb] = 'h1D3; end + 8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E2; arA23[ 'hb] = 'h1D3; end + 9: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1D3; end + 10: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1D3; end + 11: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h0EA; arA23[ 'hb] = 'h1D1; end + default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + endcase + +3'b001: // Row: 1 + unique case ( col) + 0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D1; arA23[ 'hb] = 'X; end + 1: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D1; arA23[ 'hb] = 'X; end + 2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h006; arA23[ 'hb] = 'h1D3; end + 3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h21C; arA23[ 'hb] = 'h1D3; end + 4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h103; arA23[ 'hb] = 'h1D3; end + 5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1D3; end + 6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1D3; end + 7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00A; arA23[ 'hb] = 'h1D3; end + 8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E2; arA23[ 'hb] = 'h1D3; end + 9: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1D3; end + 10: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1D3; end + 11: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h0EA; arA23[ 'hb] = 'h1D1; end + default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + endcase + +3'b010: // Row: 2 + unique case ( col) + 0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D5; arA23[ 'hb] = 'X; end + 1: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D5; arA23[ 'hb] = 'X; end + 2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00B; arA23[ 'hb] = 'h1D7; end + 3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00F; arA23[ 'hb] = 'h1D7; end + 4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h179; arA23[ 'hb] = 'h1D7; end + 5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C6; arA23[ 'hb] = 'h1D7; end + 6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E7; arA23[ 'hb] = 'h1D7; end + 7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00E; arA23[ 'hb] = 'h1D7; end + 8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E6; arA23[ 'hb] = 'h1D7; end + 9: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C6; arA23[ 'hb] = 'h1D7; end + 10: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E7; arA23[ 'hb] = 'h1D7; end + 11: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h0A7; arA23[ 'hb] = 'h1D5; end + default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + endcase + +3'b011: // Row: 3 + unique case ( col) + 0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D9; arA23[ 'hb] = 'X; end + 1: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D9; arA23[ 'hb] = 'X; end + 2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h006; arA23[ 'hb] = 'h1CF; end + 3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h21C; arA23[ 'hb] = 'h1CF; end + 4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h103; arA23[ 'hb] = 'h1CF; end + 5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1CF; end + 6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1CF; end + 7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00A; arA23[ 'hb] = 'h1CF; end + 8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E2; arA23[ 'hb] = 'h1CF; end + 9: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1CF; end + 10: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1CF; end + 11: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h0EA; arA23[ 'hb] = 'h1D9; end + default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + endcase + +3'b100: // Row: 4 + unique case ( col) + 0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h100; arA23[ 'hb] = 'X; end + 1: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h06B; arA23[ 'hb] = 'X; end + 2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h006; arA23[ 'hb] = 'h299; end + 3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h21C; arA23[ 'hb] = 'h299; end + 4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h103; arA23[ 'hb] = 'h299; end + 5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h299; end + 6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h299; end + 7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00A; arA23[ 'hb] = 'h299; end + 8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E2; arA23[ 'hb] = 'h299; end + 9: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + 10: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + 11: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + endcase + +3'b101: // Row: 5 + unique case ( col) + 0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h100; arA23[ 'hb] = 'X; end + 1: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h06B; arA23[ 'hb] = 'X; end + 2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h006; arA23[ 'hb] = 'h299; end + 3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h21C; arA23[ 'hb] = 'h299; end + 4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h103; arA23[ 'hb] = 'h299; end + 5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h299; end + 6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h299; end + 7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00A; arA23[ 'hb] = 'h299; end + 8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E2; arA23[ 'hb] = 'h299; end + 9: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + 10: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + 11: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + endcase + +3'b110: // Row: 6 + unique case ( col) + 0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h10C; arA23[ 'hb] = 'X; end + 1: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h06F; arA23[ 'hb] = 'X; end + 2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00B; arA23[ 'hb] = 'h29D; end + 3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00F; arA23[ 'hb] = 'h29D; end + 4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h179; arA23[ 'hb] = 'h29D; end + 5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C6; arA23[ 'hb] = 'h29D; end + 6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E7; arA23[ 'hb] = 'h29D; end + 7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00E; arA23[ 'hb] = 'h29D; end + 8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E6; arA23[ 'hb] = 'h29D; end + 9: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + 10: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + 11: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + endcase + +3'b111: // Row: 7 + unique case ( col) + 0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D5; arA23[ 'hb] = 'X; end + 1: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D5; arA23[ 'hb] = 'X; end + 2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00B; arA23[ 'hb] = 'h1D7; end + 3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00F; arA23[ 'hb] = 'h1D7; end + 4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h179; arA23[ 'hb] = 'h1D7; end + 5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C6; arA23[ 'hb] = 'h1D7; end + 6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E7; arA23[ 'hb] = 'h1D7; end + 7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00E; arA23[ 'hb] = 'h1D7; end + 8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E6; arA23[ 'hb] = 'h1D7; end + 9: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C6; arA23[ 'hb] = 'h1D7; end + 10: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E7; arA23[ 'hb] = 'h1D7; end + 11: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h0A7; arA23[ 'hb] = 'h1D5; end + default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X ; arA23[ 'hb] = 'X; end + endcase +endcase + +// +// Line: C +// +unique case( row86) + +3'b000: // Row: 0 + unique case ( col) + 0: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C1; arA23[ 'hc] = 'X; end + 1: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + 2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h1C3; end + 3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h1C3; end + 4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h1C3; end + 5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h1C3; end + 6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h1C3; end + 7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h1C3; end + 8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h1C3; end + 9: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h1C3; end + 10: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h1C3; end + 11: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h0EA; arA23[ 'hc] = 'h1C1; end + default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + endcase + +3'b001: // Row: 1 + unique case ( col) + 0: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C1; arA23[ 'hc] = 'X; end + 1: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + 2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h1C3; end + 3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h1C3; end + 4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h1C3; end + 5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h1C3; end + 6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h1C3; end + 7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h1C3; end + 8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h1C3; end + 9: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h1C3; end + 10: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h1C3; end + 11: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h0EA; arA23[ 'hc] = 'h1C1; end + default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + endcase + +3'b010: // Row: 2 + unique case ( col) + 0: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C5; arA23[ 'hc] = 'X; end + 1: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + 2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00B; arA23[ 'hc] = 'h1CB; end + 3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00F; arA23[ 'hc] = 'h1CB; end + 4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h179; arA23[ 'hc] = 'h1CB; end + 5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C6; arA23[ 'hc] = 'h1CB; end + 6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E7; arA23[ 'hc] = 'h1CB; end + 7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00E; arA23[ 'hc] = 'h1CB; end + 8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E6; arA23[ 'hc] = 'h1CB; end + 9: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C6; arA23[ 'hc] = 'h1CB; end + 10: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E7; arA23[ 'hc] = 'h1CB; end + 11: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h0A7; arA23[ 'hc] = 'h1C5; end + default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + endcase + +3'b011: // Row: 3 + unique case ( col) + 0: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h15B; arA23[ 'hc] = 'X; end + 1: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + 2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h15A; end + 3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h15A; end + 4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h15A; end + 5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h15A; end + 6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h15A; end + 7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h15A; end + 8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h15A; end + 9: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h15A; end + 10: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h15A; end + 11: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h0EA; arA23[ 'hc] = 'h15B; end + default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + endcase + +3'b100: // Row: 4 + unique case ( col) + 0: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1CD; arA23[ 'hc] = 'X; end + 1: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h107; arA23[ 'hc] = 'X; end + 2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h299; end + 3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h299; end + 4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h299; end + 5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h299; end + 6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h299; end + 7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h299; end + 8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h299; end + 9: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + 10: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + 11: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + endcase + +3'b101: // Row: 5 + unique case ( col) + 0: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h3E3; arA23[ 'hc] = 'X; end + 1: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h3E3; arA23[ 'hc] = 'X; end + 2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h299; end + 3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h299; end + 4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h299; end + 5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h299; end + 6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h299; end + 7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h299; end + 8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h299; end + 9: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + 10: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + 11: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + endcase + +3'b110: // Row: 6 + unique case ( col) + 0: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + 1: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h3E3; arA23[ 'hc] = 'X; end + 2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00B; arA23[ 'hc] = 'h29D; end + 3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00F; arA23[ 'hc] = 'h29D; end + 4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h179; arA23[ 'hc] = 'h29D; end + 5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C6; arA23[ 'hc] = 'h29D; end + 6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E7; arA23[ 'hc] = 'h29D; end + 7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00E; arA23[ 'hc] = 'h29D; end + 8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E6; arA23[ 'hc] = 'h29D; end + 9: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + 10: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + 11: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + endcase + +3'b111: // Row: 7 + unique case ( col) + 0: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h15B; arA23[ 'hc] = 'X; end + 1: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + 2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h15A; end + 3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h15A; end + 4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h15A; end + 5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h15A; end + 6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h15A; end + 7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h15A; end + 8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h15A; end + 9: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h15A; end + 10: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h15A; end + 11: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h0EA; arA23[ 'hc] = 'h15B; end + default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X ; arA23[ 'hc] = 'X; end + endcase +endcase + +// +// Line: D +// +unique case( row86) + +3'b000: // Row: 0 + unique case ( col) + 0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C1; arA23[ 'hd] = 'X; end + 1: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + 2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h006; arA23[ 'hd] = 'h1C3; end + 3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h21C; arA23[ 'hd] = 'h1C3; end + 4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h103; arA23[ 'hd] = 'h1C3; end + 5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C3; end + 6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C3; end + 7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00A; arA23[ 'hd] = 'h1C3; end + 8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E2; arA23[ 'hd] = 'h1C3; end + 9: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C3; end + 10: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C3; end + 11: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h0EA; arA23[ 'hd] = 'h1C1; end + default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + endcase + +3'b001: // Row: 1 + unique case ( col) + 0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C1; arA23[ 'hd] = 'X; end + 1: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C1; arA23[ 'hd] = 'X; end + 2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h006; arA23[ 'hd] = 'h1C3; end + 3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h21C; arA23[ 'hd] = 'h1C3; end + 4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h103; arA23[ 'hd] = 'h1C3; end + 5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C3; end + 6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C3; end + 7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00A; arA23[ 'hd] = 'h1C3; end + 8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E2; arA23[ 'hd] = 'h1C3; end + 9: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C3; end + 10: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C3; end + 11: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h0EA; arA23[ 'hd] = 'h1C1; end + default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + endcase + +3'b010: // Row: 2 + unique case ( col) + 0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C5; arA23[ 'hd] = 'X; end + 1: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C5; arA23[ 'hd] = 'X; end + 2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00B; arA23[ 'hd] = 'h1CB; end + 3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00F; arA23[ 'hd] = 'h1CB; end + 4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h179; arA23[ 'hd] = 'h1CB; end + 5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C6; arA23[ 'hd] = 'h1CB; end + 6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E7; arA23[ 'hd] = 'h1CB; end + 7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00E; arA23[ 'hd] = 'h1CB; end + 8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E6; arA23[ 'hd] = 'h1CB; end + 9: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C6; arA23[ 'hd] = 'h1CB; end + 10: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E7; arA23[ 'hd] = 'h1CB; end + 11: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h0A7; arA23[ 'hd] = 'h1C5; end + default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + endcase + +3'b011: // Row: 3 + unique case ( col) + 0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C9; arA23[ 'hd] = 'X; end + 1: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C9; arA23[ 'hd] = 'X; end + 2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h006; arA23[ 'hd] = 'h1C7; end + 3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h21C; arA23[ 'hd] = 'h1C7; end + 4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h103; arA23[ 'hd] = 'h1C7; end + 5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C7; end + 6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C7; end + 7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00A; arA23[ 'hd] = 'h1C7; end + 8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E2; arA23[ 'hd] = 'h1C7; end + 9: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C7; end + 10: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C7; end + 11: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h0EA; arA23[ 'hd] = 'h1C9; end + default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + endcase + +3'b100: // Row: 4 + unique case ( col) + 0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C1; arA23[ 'hd] = 'X; end + 1: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h10F; arA23[ 'hd] = 'X; end + 2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h006; arA23[ 'hd] = 'h299; end + 3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h21C; arA23[ 'hd] = 'h299; end + 4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h103; arA23[ 'hd] = 'h299; end + 5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h299; end + 6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h299; end + 7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00A; arA23[ 'hd] = 'h299; end + 8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E2; arA23[ 'hd] = 'h299; end + 9: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + 10: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + 11: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + endcase + +3'b101: // Row: 5 + unique case ( col) + 0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C1; arA23[ 'hd] = 'X; end + 1: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h10F; arA23[ 'hd] = 'X; end + 2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h006; arA23[ 'hd] = 'h299; end + 3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h21C; arA23[ 'hd] = 'h299; end + 4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h103; arA23[ 'hd] = 'h299; end + 5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h299; end + 6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h299; end + 7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00A; arA23[ 'hd] = 'h299; end + 8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E2; arA23[ 'hd] = 'h299; end + 9: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + 10: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + 11: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + endcase + +3'b110: // Row: 6 + unique case ( col) + 0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C5; arA23[ 'hd] = 'X; end + 1: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h10B; arA23[ 'hd] = 'X; end + 2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00B; arA23[ 'hd] = 'h29D; end + 3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00F; arA23[ 'hd] = 'h29D; end + 4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h179; arA23[ 'hd] = 'h29D; end + 5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C6; arA23[ 'hd] = 'h29D; end + 6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E7; arA23[ 'hd] = 'h29D; end + 7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00E; arA23[ 'hd] = 'h29D; end + 8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E6; arA23[ 'hd] = 'h29D; end + 9: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + 10: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + 11: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + endcase + +3'b111: // Row: 7 + unique case ( col) + 0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C5; arA23[ 'hd] = 'X; end + 1: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C5; arA23[ 'hd] = 'X; end + 2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00B; arA23[ 'hd] = 'h1CB; end + 3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00F; arA23[ 'hd] = 'h1CB; end + 4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h179; arA23[ 'hd] = 'h1CB; end + 5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C6; arA23[ 'hd] = 'h1CB; end + 6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E7; arA23[ 'hd] = 'h1CB; end + 7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00E; arA23[ 'hd] = 'h1CB; end + 8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E6; arA23[ 'hd] = 'h1CB; end + 9: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C6; arA23[ 'hd] = 'h1CB; end + 10: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E7; arA23[ 'hd] = 'h1CB; end + 11: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h0A7; arA23[ 'hd] = 'h1C5; end + default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X ; arA23[ 'hd] = 'X; end + endcase +endcase +end + + +endmodule diff --git a/rtl/iwm.v b/rtl/iwm.v index d2594d8..1bed612 100644 --- a/rtl/iwm.v +++ b/rtl/iwm.v @@ -35,8 +35,6 @@ module iwm input cep, input cen, - input clk8, - input _reset, input selectIWM, input _cpuRW, @@ -181,7 +179,7 @@ module iwm selectExternalDriveNext <= selectExternalDrive; q6Next <= q6; q7Next <= q7; - + if (selectIWM == 1'b1 && _cpuLDS == 1'b0) begin case (cpuAddrRegHi[3:1]) 3'h0: // ca0 @@ -206,7 +204,7 @@ module iwm endcase end end - + // update IWM bit registers always @(posedge clk or negedge _reset) begin if (_reset == 1'b0) begin @@ -220,7 +218,7 @@ module iwm q6 <= 0; q7 <= 0; end - else if(cen) begin + else begin ca0 <= ca0Next; ca1 <= ca1Next; ca2 <= ca2Next; @@ -249,7 +247,7 @@ module iwm dataOutLo <= 0; endcase end - + // write IWM state always @(posedge clk or negedge _reset) begin if (_reset == 1'b0) begin @@ -270,16 +268,14 @@ module iwm end end end - + // Manage incoming bytes from the disk drive wire iwmRead = (_cpuRW == 1'b1 && selectIWM == 1'b1 && _cpuLDS == 1'b0); - reg iwmReadPrev; reg [3:0] readLatchClearTimer; always @(posedge clk or negedge _reset) begin if (_reset == 1'b0) begin readDataLatch <= 0; readLatchClearTimer <= 0; - iwmReadPrev <= 0; end else if(cen) begin // a countdown timer governs how long after a data latch read before the latch is cleared @@ -288,10 +284,10 @@ module iwm end // the conclusion of a valid CPU read from the IWM will start the timer to clear the latch - if (iwmReadPrev && !iwmRead && readDataLatch[7]) begin + if (iwmRead && readDataLatch[7]) begin readLatchClearTimer <= 4'hD; // clear latch 14 clocks after the conclusion of a valid read end - + // when the drive indicates that a new byte is ready, latch it // NOTE: the real IWM must self-synchronize with the incoming data to determine when to latch it if (newByteReady) begin @@ -300,8 +296,6 @@ module iwm else if (readLatchClearTimer == 1'b1) begin readDataLatch <= 0; end - - iwmReadPrev <= iwmRead; end end assign advanceDriveHead = readLatchClearTimer == 1'b1; // prevents overrun when debugging, does not exist on a real Mac! diff --git a/rtl/ncr5380.v b/rtl/ncr5380.v index d8f3e53..3a4d8b2 100644 --- a/rtl/ncr5380.v +++ b/rtl/ncr5380.v @@ -1,297 +1,368 @@ -/* verilator lint_off UNUSED */ +/* verilator lint_off UNUSED */ + +/* based on minimigmac by Benjamin Herrenschmidt */ + +/* Read registers */ +`define RREG_CDR 3'h0 /* Current SCSI data */ +`define RREG_ICR 3'h1 /* Initiator Command */ +`define RREG_MR 3'h2 /* Mode register */ +`define RREG_TCR 3'h3 /* Target Command */ +`define RREG_CSR 3'h4 /* SCSI bus status */ +`define RREG_BSR 3'h5 /* Bus and status */ +`define RREG_IDR 3'h6 /* Input data */ +`define RREG_RST 3'h7 /* Reset */ + +/* Write registers */ +`define WREG_ODR 3'h0 /* Output data */ +`define WREG_ICR 3'h1 /* Initiator Command */ +`define WREG_MR 3'h2 /* Mode register */ +`define WREG_TCR 3'h3 /* Target Command */ +`define WREG_SER 3'h4 /* Select Enable */ +`define WREG_DMAS 3'h5 /* Start DMA Send */ +`define WREG_DMATR 3'h6 /* Start DMA Target receive */ +`define WREG_IDMAR 3'h7 /* Start DMA Initiator receive */ + +/* MR bit numbers */ +`define MR_DMA_MODE 1 +`define MR_ARB 0 + +/* ICR bit numbers */ +`define ICR_A_RST 7 +`define ICR_TEST_MODE 6 +`define ICR_DIFF_ENBL 5 +`define ICR_A_ACK 4 +`define ICR_A_BSY 3 +`define ICR_A_SEL 2 +`define ICR_A_ATN 1 +`define ICR_A_DATA 0 + +/* TCR bit numbers */ +`define TCR_A_REQ 3 +`define TCR_A_MSG 2 +`define TCR_A_CD 1 +`define TCR_A_IO 0 + +module ncr5380 +( + input clk, + input ce, + + input reset, + + /* Bus interface. 3-bit address, to be wired + * appropriately upstream (to A4..A6) plus one + * more bit (A9) wired as dack. + */ + input bus_cs, + input bus_we, + input [2:0] bus_rs, + input dack, + input [7:0] wdata, + output [7:0] rdata, + + + // connections to io controller + input [1:0] img_mounted, + input [31:0] img_size, + + output [15:0] io_req_type, + output [31:0] io_lba, + output [1:0] io_rd, + output [1:0] io_wr, + input io_ack, + + input [8:0] sd_buff_addr, + input [7:0] sd_buff_dout, + output [7:0] sd_buff_din, + input sd_buff_wr +); + + reg [7:0] mr; /* Mode Register */ + reg [7:0] icr; /* Initiator Command Register */ + reg [3:0] tcr; /* Target Command Register */ + wire [7:0] csr; /* SCSI bus status register */ + + /* Data in and out latches and associated + * control logic for DMA + */ + wire [7:0] din; + reg [7:0] dout; + reg dphase; + reg dma_en; + + /* --- Main host-side interface --- */ + + /* Register & DMA accesses decodes */ + reg dma_rd; + reg dma_wr; + reg reg_wr; + + wire i_dma_rd = bus_cs & dack & ~bus_we; + wire i_dma_wr = bus_cs & dack & bus_we; + wire i_reg_wr = bus_cs & ~dack & bus_we; + + always @(posedge clk) begin + reg old_dma_rd, old_dma_wr, old_reg_wr; + + old_dma_rd <= i_dma_rd; + old_dma_wr <= i_dma_wr; + old_reg_wr <= i_reg_wr; + + dma_rd <= 0; + dma_wr <= 0; + reg_wr <= 0; + + if(~old_dma_wr & i_dma_wr) dma_wr <= 1; + else if(~old_dma_rd & i_dma_rd) dma_rd <= 1; + else if(~old_reg_wr & i_reg_wr) reg_wr <= 1; + end + + /* System bus reads */ + assign rdata = dack ? cur_data : + bus_rs == `RREG_CDR ? cur_data : + bus_rs == `RREG_ICR ? icr_read : + bus_rs == `RREG_MR ? mr : + bus_rs == `RREG_TCR ? { 4'h0, tcr } : + bus_rs == `RREG_CSR ? csr : + bus_rs == `RREG_BSR ? bsr : + bus_rs == `RREG_IDR ? cur_data : + bus_rs == `RREG_RST ? 8'hff : + 8'hff; + + /* DMA handhsaking logic. Two phase logic, in phase 0 + * DRQ follows SCSI _REQ until we see DACK. In phase 1 + * we just wait for SCSI _REQ to go down and go back to + * phase 0. We assert SCSI _ACK in phase 1. + */ + always@(posedge clk or posedge reset) begin + if (reset) begin + dphase <= 0; + end else begin + if (!dma_en) begin + dphase <= 0; + end else if (dphase == 0) begin + /* Be careful to do that in bus phase 1, + * not phase 0, or we would incorrectly + * assert bus_hold and lock up the system + */ + if ((dma_rd || dma_wr) && scsi_req) begin + dphase <= 1; + end + end else if (!scsi_req) begin + dphase <= 0; + end + end + end + + /* Data out latch (in DMA mode, this is one cycle after we've + * asserted ACK) + */ + always@(posedge clk) if((reg_wr && bus_rs == `WREG_ODR) || dma_wr) dout <= wdata; + + /* Current data register. Simplified logic: We loop back the + * output data if we are asserting the bus, else we get the + * input latch + */ + wire [7:0] cur_data = out_en ? dout : din; + + /* Logic for "asserting the bus" simplified */ + wire out_en = icr[`ICR_A_DATA] | mr[`MR_ARB]; + + /* ICR read wires */ + wire [7:0] icr_read = { icr[`ICR_A_RST], + icr_aip, + icr_la, + icr[`ICR_A_ACK], + icr[`ICR_A_BSY], + icr[`ICR_A_SEL], + icr[`ICR_A_ATN], + icr[`ICR_A_DATA] }; + + /* ICR write */ + always@(posedge clk or posedge reset) begin + if (reset) begin + icr <= 0; + end else if (reg_wr && (bus_rs == `WREG_ICR)) begin + icr <= wdata; + end + end + + /* MR write */ + always@(posedge clk or posedge reset) begin + if (reset) mr <= 8'b0; + else if (reg_wr && (bus_rs == `WREG_MR)) mr <= wdata; + end + + /* TCR write */ + always@(posedge clk or posedge reset) begin + if (reset) tcr <= 4'b0; + else if (reg_wr && (bus_rs == `WREG_TCR)) tcr <= wdata[3:0]; + end + + /* DMA start send & receive registers. We currently ignore + * the direction. + */ + always@(posedge clk or posedge reset) begin + if (reset) begin + dma_en <= 0; + end else begin + if (!mr[`MR_DMA_MODE]) begin + dma_en <= 0; + end else if (reg_wr && (bus_rs == `WREG_DMAS)) begin + dma_en <= 1; + end else if (reg_wr && (bus_rs == `WREG_IDMAR)) begin + dma_en <= 1; + end + end + end -/* based on minimigmac by Benjamin Herrenschmidt */ - -/* Read registers */ -`define RREG_CDR 3'h0 /* Current SCSI data */ -`define RREG_ICR 3'h1 /* Initiator Command */ -`define RREG_MR 3'h2 /* Mode register */ -`define RREG_TCR 3'h3 /* Target Command */ -`define RREG_CSR 3'h4 /* SCSI bus status */ -`define RREG_BSR 3'h5 /* Bus and status */ -`define RREG_IDR 3'h6 /* Input data */ -`define RREG_RST 3'h7 /* Reset */ - -/* Write registers */ -`define WREG_ODR 3'h0 /* Output data */ -`define WREG_ICR 3'h1 /* Initiator Command */ -`define WREG_MR 3'h2 /* Mode register */ -`define WREG_TCR 3'h3 /* Target Command */ -`define WREG_SER 3'h4 /* Select Enable */ -`define WREG_DMAS 3'h5 /* Start DMA Send */ -`define WREG_DMATR 3'h6 /* Start DMA Target receive */ -`define WREG_IDMAR 3'h7 /* Start DMA Initiator receive */ - -/* MR bit numbers */ -`define MR_DMA_MODE 1 -`define MR_ARB 0 - -/* ICR bit numbers */ -`define ICR_A_RST 7 -`define ICR_TEST_MODE 6 -`define ICR_DIFF_ENBL 5 -`define ICR_A_ACK 4 -`define ICR_A_BSY 3 -`define ICR_A_SEL 2 -`define ICR_A_ATN 1 -`define ICR_A_DATA 0 - -/* TCR bit numbers */ -`define TCR_A_REQ 3 -`define TCR_A_MSG 2 -`define TCR_A_CD 1 -`define TCR_A_IO 0 - -module ncr5380 -( - input clk, - input ce, - - input reset, - - /* Bus interface. 3-bit address, to be wired - * appropriately upstream (to A4..A6) plus one - * more bit (A9) wired as dack. - */ - input bus_cs, - input bus_we, - input [2:0] bus_rs, - input dack, - input [7:0] wdata, - output [7:0] rdata, - - - // connections to io controller - output [31:0] io_lba, - output io_rd, - output io_wr, - input io_ack, - - input [8:0] sd_buff_addr, - input [7:0] sd_buff_dout, - output [7:0] sd_buff_din, - input sd_buff_wr -); - - reg [7:0] mr; /* Mode Register */ - reg [7:0] icr; /* Initiator Command Register */ - reg [3:0] tcr; /* Target Command Register */ - wire [7:0] csr; /* SCSI bus status register */ - - /* Data in and out latches and associated - * control logic for DMA - */ - wire [7:0] din; - reg [7:0] dout; - reg dphase; - reg dma_en; - - /* --- Main host-side interface --- */ - - /* Register & DMA accesses decodes */ - reg dma_rd; - reg dma_wr; - reg reg_wr; + /* CSR (read only). We don't do parity */ + assign csr = { scsi_rst, scsi_bsy, scsi_req, scsi_msg, + scsi_cd, scsi_io, scsi_sel, 1'b0 }; + + /* Bus and Status register */ + /* BSR (read only). We don't do a few things... */ + wire bsr_eodma = 1'b0; /* We don't do EOP */ + wire bsr_dmarq = scsi_req & dma_en; + wire bsr_perr = 1'b0; /* We don't do parity */ + wire bsr_irq = 1'b0; /* XXX ? Does MacOS use this ? */ + wire bsr_pmatch = + tcr[`TCR_A_MSG] == scsi_msg && + tcr[`TCR_A_CD ] == scsi_cd && + tcr[`TCR_A_IO ] == scsi_io; + + wire bsr_berr = 1'b0; /* XXX ? Does MacOS use this ? */ + wire [7:0] bsr = { bsr_eodma, bsr_dmarq, bsr_perr, bsr_irq, + bsr_pmatch, bsr_berr, scsi_atn, scsi_ack }; + + /* --- Simulated SCSI Signals --- */ + + /* BSY logic (simplified arbitration, see notes) */ + wire scsi_bsy = + icr[`ICR_A_BSY] | + scsi2_bsy | + scsi6_bsy | + mr[`MR_ARB]; + + /* Remains of simplified arbitration logic */ + wire icr_aip = mr[`MR_ARB]; + wire icr_la = 0; + + reg dma_ack; + always @(posedge clk) if(ce) dma_ack <= dphase; + + /* Other ORed SCSI signals */ + wire scsi_sel = icr[`ICR_A_SEL]; + wire scsi_rst = icr[`ICR_A_RST]; + wire scsi_ack = icr[`ICR_A_ACK] | dma_ack; + wire scsi_atn = icr[`ICR_A_ATN]; +/* + wire scsi_cd = scsi2_cd; + wire scsi_io = scsi2_io; + wire scsi_msg = scsi2_msg; + wire scsi_req = scsi2_req; - wire i_dma_rd = bus_cs & dack & ~bus_we; - wire i_dma_wr = bus_cs & dack & bus_we; - wire i_reg_wr = bus_cs & ~dack & bus_we; - - always @(posedge clk) begin - reg old_dma_rd, old_dma_wr, old_reg_wr; - - old_dma_rd <= i_dma_rd; - old_dma_wr <= i_dma_wr; - old_reg_wr <= i_reg_wr; - - dma_rd <= 0; - dma_wr <= 0; - reg_wr <= 0; - - if(~old_dma_wr & i_dma_wr) dma_wr <= 1; - else if(~old_dma_rd & i_dma_rd) dma_rd <= 1; - else if(~old_reg_wr & i_reg_wr) reg_wr <= 1; - end - - /* System bus reads */ - assign rdata = dack ? cur_data : - bus_rs == `RREG_CDR ? cur_data : - bus_rs == `RREG_ICR ? icr_read : - bus_rs == `RREG_MR ? mr : - bus_rs == `RREG_TCR ? { 4'h0, tcr } : - bus_rs == `RREG_CSR ? csr : - bus_rs == `RREG_BSR ? bsr : - bus_rs == `RREG_IDR ? cur_data : - bus_rs == `RREG_RST ? 8'hff : - 8'hff; - - /* DMA handhsaking logic. Two phase logic, in phase 0 - * DRQ follows SCSI _REQ until we see DACK. In phase 1 - * we just wait for SCSI _REQ to go down and go back to - * phase 0. We assert SCSI _ACK in phase 1. - */ - always@(posedge clk or posedge reset) begin - if (reset) begin - dphase <= 0; - end else begin - if (!dma_en) begin - dphase <= 0; - end else if (dphase == 0) begin - /* Be careful to do that in bus phase 1, - * not phase 0, or we would incorrectly - * assert bus_hold and lock up the system - */ - if ((dma_rd || dma_wr) && scsi_req) begin - dphase <= 1; - end - end else if (!scsi_req) begin - dphase <= 0; - end - end - end - - /* Data out latch (in DMA mode, this is one cycle after we've - * asserted ACK) - */ - always@(posedge clk) if((reg_wr && bus_rs == `WREG_ODR) || dma_wr) dout <= wdata; - - /* Current data register. Simplified logic: We loop back the - * output data if we are asserting the bus, else we get the - * input latch - */ - wire [7:0] cur_data = out_en ? dout : din; - - /* Logic for "asserting the bus" simplified */ - wire out_en = icr[`ICR_A_DATA] | mr[`MR_ARB]; - - /* ICR read wires */ - wire [7:0] icr_read = { icr[`ICR_A_RST], - icr_aip, - icr_la, - icr[`ICR_A_ACK], - icr[`ICR_A_BSY], - icr[`ICR_A_SEL], - icr[`ICR_A_ATN], - icr[`ICR_A_DATA] }; - - /* ICR write */ - always@(posedge clk or posedge reset) begin - if (reset) begin - icr <= 0; - end else if (reg_wr && (bus_rs == `WREG_ICR)) begin - icr <= wdata; - end - end - - /* MR write */ - always@(posedge clk or posedge reset) begin - if (reset) mr <= 8'b0; - else if (reg_wr && (bus_rs == `WREG_MR)) mr <= wdata; - end - - /* TCR write */ - always@(posedge clk or posedge reset) begin - if (reset) tcr <= 4'b0; - else if (reg_wr && (bus_rs == `WREG_TCR)) tcr <= wdata[3:0]; - end - - /* DMA start send & receive registers. We currently ignore - * the direction. - */ - always@(posedge clk or posedge reset) begin - if (reset) begin - dma_en <= 0; - end else begin - if (!mr[`MR_DMA_MODE]) begin - dma_en <= 0; - end else if (reg_wr && (bus_rs == `WREG_DMAS)) begin - dma_en <= 1; - end else if (reg_wr && (bus_rs == `WREG_IDMAR)) begin - dma_en <= 1; - end - end - end - - /* CSR (read only). We don't do parity */ - assign csr = { scsi_rst, scsi_bsy, scsi_req, scsi_msg, - scsi_cd, scsi_io, scsi_sel, 1'b0 }; - - /* Bus and Status register */ - /* BSR (read only). We don't do a few things... */ - wire bsr_eodma = 1'b0; /* We don't do EOP */ - wire bsr_dmarq = scsi_req & dma_en; - wire bsr_perr = 1'b0; /* We don't do parity */ - wire bsr_irq = 1'b0; /* XXX ? Does MacOS use this ? */ - wire bsr_pmatch = - tcr[`TCR_A_MSG] == scsi_msg && - tcr[`TCR_A_CD ] == scsi_cd && - tcr[`TCR_A_IO ] == scsi_io; - - wire bsr_berr = 1'b0; /* XXX ? Does MacOS use this ? */ - wire [7:0] bsr = { bsr_eodma, bsr_dmarq, bsr_perr, bsr_irq, - bsr_pmatch, bsr_berr, scsi_atn, scsi_ack }; - - /* --- Simulated SCSI Signals --- */ + assign din = scsi2_dout; - /* BSY logic (simplified arbitration, see notes) */ - wire scsi_bsy = - icr[`ICR_A_BSY] | - scsi2_bsy | - mr[`MR_ARB]; - - /* Remains of simplified arbitration logic */ - wire icr_aip = mr[`MR_ARB]; - wire icr_la = 0; + assign io_lba = io_lba_2; + assign sd_buff_din = sd_buff_din_2; +*/ + /* Other trivial lines set by target */ - reg dma_ack; - always @(posedge clk) if(ce) dma_ack <= dphase; - - /* Other ORed SCSI signals */ - wire scsi_sel = icr[`ICR_A_SEL]; - wire scsi_rst = icr[`ICR_A_RST]; - wire scsi_ack = icr[`ICR_A_ACK] | dma_ack; - wire scsi_atn = icr[`ICR_A_ATN]; - - /* Other trivial lines set by target */ - wire scsi_cd = scsi2_cd; - wire scsi_io = scsi2_io; - wire scsi_msg = scsi2_msg; - wire scsi_req = scsi2_req; - - assign din = scsi2_bsy?scsi2_dout:8'h55; - - // input signals from target 2 - wire scsi2_bsy, scsi2_msg, scsi2_io, scsi2_cd, scsi2_req; - wire [7:0] scsi2_dout; - - // connect a target - scsi #(.ID(2)) scsi2 - ( - .clk ( clk ), - .rst ( scsi_rst ), - .sel ( scsi_sel ), - .atn ( scsi_atn ), - .bsy ( scsi2_bsy ), - .msg ( scsi2_msg ), - .cd ( scsi2_cd ), - .io ( scsi2_io ), - .req ( scsi2_req ), - .ack ( scsi_ack ), - .dout ( scsi2_dout ), - .din ( dout ), - - // connection to io controller to read and write sectors - // to sd card - .io_lba ( io_lba ), - .io_rd ( io_rd ), - .io_wr ( io_wr ), - .io_ack ( io_ack ), - - .sd_buff_addr(sd_buff_addr), - .sd_buff_dout(sd_buff_dout), - .sd_buff_din(sd_buff_din), - .sd_buff_wr(sd_buff_wr) - ); - - -endmodule + wire scsi_cd = (scsi2_bsy) ? scsi2_cd : scsi6_cd; + wire scsi_io = (scsi2_bsy) ? scsi2_io : scsi6_io; + wire scsi_msg = (scsi2_bsy) ? scsi2_msg : scsi6_msg; + wire scsi_req = (scsi2_bsy) ? scsi2_req : scsi6_req; + + assign din = scsi2_bsy ? scsi2_dout : + scsi6_bsy ? scsi6_dout : + 8'h55; + + assign io_lba = (scsi2_bsy) ? io_lba_2 : io_lba_6; + assign sd_buff_din = (scsi2_bsy) ? sd_buff_din_2 : sd_buff_din_6; + assign io_req_type = 16'h0000; // Not used atm. Could be used for CD-ROM sector requests later. ElectronAsh. + + // input signals from target 2 + wire scsi2_bsy, scsi2_msg, scsi2_io, scsi2_cd, scsi2_req; + wire [7:0] scsi2_dout; + + wire [31:0] io_lba_2; + wire [7:0] sd_buff_din_2; + + // connect a target + scsi #(.ID(2)) scsi2 + ( + .clk ( clk ), + .rst ( scsi_rst ), + .sel ( scsi_sel ), + .atn ( scsi_atn ), + + .ack ( scsi_ack ), + + .bsy ( scsi2_bsy ), + .msg ( scsi2_msg ), + .cd ( scsi2_cd ), + .io ( scsi2_io ), + .req ( scsi2_req ), + .dout ( scsi2_dout ), + + .din ( dout ), + + // connection to io controller to read and write sectors + // to sd card + .img_mounted(img_mounted[1]), + .img_blocks(img_size[31:9]), + .io_lba ( io_lba_2 ), + .io_rd ( io_rd[1] ), + .io_wr ( io_wr[1] ), + .io_ack ( io_ack & scsi2_bsy ), + + .sd_buff_addr( sd_buff_addr ), + .sd_buff_dout( sd_buff_dout ), + .sd_buff_din( sd_buff_din_2 ), + .sd_buff_wr( sd_buff_wr & scsi2_bsy ) + ); + + + // input signals from target 6 + wire scsi6_bsy, scsi6_msg, scsi6_io, scsi6_cd, scsi6_req; + wire [7:0] scsi6_dout; + + wire [31:0] io_lba_6; + wire [7:0] sd_buff_din_6; + + scsi #(.ID(6)) scsi6 + ( + .clk ( clk ) , // input clk + .rst ( scsi_rst ) , // input rst + .sel ( scsi_sel ) , // input sel + .atn ( scsi_atn ) , // input atn + + .ack ( scsi_ack ) , // input ack + + .bsy ( scsi6_bsy ) , // output bsy + .msg ( scsi6_msg ) , // output msg + .cd ( scsi6_cd ) , // output cd + .io ( scsi6_io ) , // output io + .req ( scsi6_req ) , // output req + .dout ( scsi6_dout ) , // output [7:0] dout + + .din ( dout ) , // input [7:0] din + + // connection to io controller to read and write sectors + // to sd card + .img_mounted( img_mounted[0] ), + .img_blocks( img_size[31:9] ), + .io_lba ( io_lba_6 ) , // output [31:0] io_lba + .io_rd ( io_rd[0] ) , // output io_rd + .io_wr ( io_wr[0] ) , // output io_wr + .io_ack ( io_ack & scsi6_bsy ) , // input io_ack + + .sd_buff_addr( sd_buff_addr ) , // input [8:0] sd_buff_addr + .sd_buff_dout( sd_buff_dout ) , // input [7:0] sd_buff_dout + .sd_buff_din( sd_buff_din_6 ) , // output [7:0] sd_buff_din + .sd_buff_wr( sd_buff_wr & scsi6_bsy ) // input sd_buff_wr + ); + + +endmodule diff --git a/rtl/pll.qip b/rtl/pll.qip index 1a47ba6..b82e49d 100644 --- a/rtl/pll.qip +++ b/rtl/pll.qip @@ -35,16 +35,16 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MTM=::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NjIuNjY4OA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NjUuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MTA=::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzMyMjcyNDA1Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::NDI5NDk2NzMw::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Nw==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" @@ -53,14 +53,14 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::NjIuNjY4OA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MzIuNQ==::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MTA=::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTM=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MzM4MDcyMzM3OA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MTE=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::OQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::NDI5NDk2NzMw::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MTQ=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::LTQzNTI=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MTgwLjA=::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" @@ -256,10 +256,10 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NjIuNjY4ODAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NjUuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MzIuNTAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" @@ -317,8 +317,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw0LDMsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDM4LjY4MTU5OSBNSHosMzMyMjcyNDA1Myxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NSw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSx0cnVlLGZhbHNlLDQsMywxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDcsNywxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwyLDIwLDQwMDAsNDU1LjAgTUh6LDQyOTQ5NjczMCxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" diff --git a/rtl/pll.v b/rtl/pll.v index cafefff..60d7f20 100644 --- a/rtl/pll.v +++ b/rtl/pll.v @@ -9,6 +9,7 @@ module pll ( input wire refclk, // refclk.clk input wire rst, // reset.reset output wire outclk_0, // outclk0.clk + output wire outclk_1, // outclk1.clk output wire locked // locked.export ); @@ -16,6 +17,7 @@ module pll ( .refclk (refclk), // refclk.clk .rst (rst), // reset.reset .outclk_0 (outclk_0), // outclk0.clk + .outclk_1 (outclk_1), // outclk1.clk .locked (locked) // locked.export ); @@ -26,7 +28,7 @@ endmodule // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // ************************************************************ -// Copyright (C) 1991-2020 Altera Corporation +// Copyright (C) 1991-2021 Altera Corporation // Any megafunction design, and related net list (encrypted or decrypted), // support information, device programming or simulation file, and any other // associated documentation or information provided by Altera or a partner @@ -61,12 +63,12 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -75,11 +77,11 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: diff --git a/rtl/pll/pll_0002.v b/rtl/pll/pll_0002.v index 3354a5a..ae89a7e 100644 --- a/rtl/pll/pll_0002.v +++ b/rtl/pll/pll_0002.v @@ -10,6 +10,9 @@ module pll_0002( // interface 'outclk0' output wire outclk_0, + // interface 'outclk1' + output wire outclk_1, + // interface 'locked' output wire locked ); @@ -18,11 +21,11 @@ module pll_0002( .fractional_vco_multiplier("true"), .reference_clock_frequency("50.0 MHz"), .operation_mode("direct"), - .number_of_clocks(1), - .output_clock_frequency0("62.668800 MHz"), + .number_of_clocks(2), + .output_clock_frequency0("65.000000 MHz"), .phase_shift0("0 ps"), .duty_cycle0(50), - .output_clock_frequency1("0 MHz"), + .output_clock_frequency1("32.500000 MHz"), .phase_shift1("0 ps"), .duty_cycle1(50), .output_clock_frequency2("0 MHz"), @@ -77,7 +80,7 @@ module pll_0002( .pll_subtype("General") ) altera_pll_i ( .rst (rst), - .outclk ({outclk_0}), + .outclk ({outclk_1, outclk_0}), .locked (locked), .fboutclk ( ), .fbclk (1'b0), diff --git a/rtl/rtc.v b/rtl/rtc.v new file mode 100644 index 0000000..d77f443 --- /dev/null +++ b/rtl/rtc.v @@ -0,0 +1,125 @@ +/* PRAM - RTC implementation for plus_too */ + +module rtc ( + input clk, + input reset, + + input [32:0] timestamp, // unix timestamp + input _cs, + input ck, + input dat_i, + output reg dat_o +); + +reg [2:0] bit_cnt; +reg ck_d; +reg [7:0] din; +reg [7:0] cmd; +reg [7:0] dout; +reg cmd_mode; +reg receiving; +reg [31:0] secs; +reg [31:0] secs2; +reg [7:0] ram[20]; +reg [24:0] clocktoseconds; + +initial begin + ram[5'h00] = 8'hA8; + ram[5'h01] = 8'h00; + ram[5'h02] = 8'h00; + ram[5'h03] = 8'h22; + ram[5'h04] = 8'hCC; + ram[5'h05] = 8'h0A; + ram[5'h06] = 8'hCC; + ram[5'h07] = 8'h0A; + ram[5'h08] = 8'h00; + ram[5'h09] = 8'h00; + ram[5'h0A] = 8'h00; + ram[5'h0B] = 8'h00; + ram[5'h0C] = 8'h00; + ram[5'h0D] = 8'h02; + ram[5'h0E] = 8'h63; + ram[5'h0F] = 8'h00; + ram[5'h10] = 8'h03; + ram[5'h11] = 8'h88; + ram[5'h12] = 8'h00; + ram[5'h13] = 8'h6C; +end + +initial secs = 0; + +always @(posedge clk) begin + if (reset) begin + bit_cnt <= 0; + receiving <= 1; + cmd_mode <= 1; + dat_o <= 1; + // sec_cnt <= 0; + end + else begin + + // timestamp is only sent at core load + if (secs==0) + secs <= timestamp[31:0] + 2082844800; // difference between unix epoch and mac epoch + + // we need to add one to the seconds + clocktoseconds<= clocktoseconds + 1'd1; + if (32499999==clocktoseconds) // every 32mhz we increment secs by one + begin + clocktoseconds<=0; + secs<=secs+1; + end + + if (_cs) begin + bit_cnt <= 0; + receiving <= 1; + cmd_mode <= 1; + dat_o <= 1; + end + else begin + ck_d <= ck; + + // transmit at the falling edge + if (ck_d & ~ck & !receiving) + dat_o <= dout[7-bit_cnt]; + // receive at the rising edge of ck + if (~ck_d & ck) begin + bit_cnt <= bit_cnt + 1'd1; + if (receiving) + din <= {din[6:0], dat_i}; + + if (bit_cnt == 7) begin + if (receiving && cmd_mode) begin + // command byte received + cmd_mode <= 0; + receiving <= ~din[6]; + cmd <= {din[6:0], dat_i}; + casez ({din[5:0], dat_i}) + 7'b00?0001: dout <= secs[7:0]; + 7'b00?0101: dout <= secs[15:8]; + 7'b00?1001: dout <= secs[23:16]; + 7'b00?1101: dout <= secs[31:24]; + 7'b010??01: dout <= ram[{3'b100, din[2:1]}]; + 7'b1????01: dout <= ram[din[4:1]]; + default: ; + endcase + end + if (receiving && !cmd_mode) begin + // data byte received + casez (cmd[6:0]) + 7'b0000001: secs[7:0] <= {din[6:0], dat_i}; + 7'b0000101: secs[15:8] <= {din[6:0], dat_i}; + 7'b0001001: secs[23:16] <= {din[6:0], dat_i}; + 7'b0001101: secs[31:24] <= {din[6:0], dat_i}; + 7'b010??01: ram[{3'b100, cmd[3:2]}] <= {din[6:0], dat_i}; + 7'b1????01: ram[cmd[5:2]] <= {din[6:0], dat_i}; + default: ; + endcase + end + end + end + end + end +end + +endmodule diff --git a/rtl/scc.v b/rtl/scc.v index 92a0323..bc3f8b7 100644 --- a/rtl/scc.v +++ b/rtl/scc.v @@ -124,32 +124,41 @@ module scc reg ex_irq_ip_a; reg ex_irq_ip_b; wire [2:0] rr2_vec_stat; - + /* Register/Data access helpers */ assign wreg_a = cs & we & (~rs[1]) & rs[0]; assign wreg_b = cs & we & (~rs[1]) & ~rs[0]; // make sure rindex changes after the cpu cycle has ended so // read data is still stable while cpu advances - always@(posedge clk) if(cen) rindex <= rindex_latch; + always@(posedge clk) if(~cs) rindex <= rindex_latch; /* Register index is set by a write to WR0 and reset * after any subsequent write. We ignore the side */ always@(posedge clk or posedge reset) begin - if (reset) - rindex_latch <= 0; - else if (cen && cs && !rs[1]) begin - /* Default, reset index */ - rindex_latch <= 0; + if (reset) begin + rindex_latch <= 0; + data_a <= 0; + data_b <= 0; + end else if (cen && cs) begin + if (!rs[1]) begin + /* Default, reset index */ + rindex_latch <= 0; - /* Write to WR0 */ - if (we && rindex == 0) begin - /* Get low index bits */ - rindex_latch[2:0] <= wdata[2:0]; + /* Write to WR0 */ + if (we && rindex == 0) begin + /* Get low index bits */ + rindex_latch[2:0] <= wdata[2:0]; - /* Add point high */ - rindex_latch[3] <= (wdata[5:3] == 3'b001); + /* Add point high */ + rindex_latch[3] <= (wdata[5:3] == 3'b001); + end + end else begin + if (we) begin + if (rs[0]) data_a <= wdata; + else data_b <= wdata; + end end end end diff --git a/rtl/scsi.v b/rtl/scsi.v index 5fd494d..1267ba1 100644 --- a/rtl/scsi.v +++ b/rtl/scsi.v @@ -24,11 +24,13 @@ module scsi input [7:0] din, // data from initiator to target output [7:0] dout, // data from target to initiator - // interface to io controller + // interface to io controller + input img_mounted, + input [23:0] img_blocks, output [31:0] io_lba, output reg io_rd, output reg io_wr, - input io_ack, + input io_ack, input [8:0] sd_buff_addr, input [7:0] sd_buff_dout, @@ -38,7 +40,7 @@ module scsi // SCSI device id -parameter ID = 0; +parameter [7:0] ID = 0; `define PHASE_IDLE 3'd0 `define PHASE_CMD_IN 3'd1 @@ -104,11 +106,17 @@ wire [7:0] inquiry_dout = (data_cnt == 32'd26)?"S":(data_cnt == 32'd27)?"T": (data_cnt == 32'd28)?"2":(data_cnt == 32'd29)?"2": - (data_cnt == 32'd30)?"5":(data_cnt == 32'd31)?"N": + (data_cnt == 32'd30)?"5":(data_cnt == 32'd31)?"N" + ID: // TESTING. ElectronAsh. 8'h00; // output of read capacity command -wire [31:0] capacity = 32'd41056; // 40960 + 96 blocks = 20MB +//wire [31:0] capacity = 32'd41056; // 40960 + 96 blocks = 20MB +//wire [31:0] capacity = 32'd1024096; // 1024000 + 96 blocks = 500MB +reg [31:0] capacity; +always @(posedge clk) begin + if (img_mounted) capacity <= img_blocks + 8'd96; +end + wire [31:0] capacity_m1 = capacity - 32'd1; wire [7:0] read_capacity_dout = (data_cnt == 32'd0 )?capacity_m1[31:24]: @@ -169,8 +177,8 @@ always @(posedge clk) begin reg old_ack; old_ack <= ack; - stb_ack <= (~old_ack & ack); - stb_adv <= stb_ack; + stb_ack <= (~old_ack & ack); // on rising edge + stb_adv <= (old_ack & ~ack); // on falling edge end // store data on rising edge of ack, ... @@ -254,10 +262,13 @@ wire cmd_mode_select = (op_code == 8'h15); wire cmd_mode_sense = (op_code == 8'h1a); wire cmd_test_unit_ready = (op_code == 8'h00); wire cmd_read_capacity = (op_code == 8'h25); +wire cmd_read_buffer = (op_code == 8'h3b); // fake +wire cmd_write_buffer = (op_code == 8'h3c); // fake // valid command in buffer? TODO: check for valid command parameters wire cmd_ok = cmd_read || cmd_write || cmd_inquiry || cmd_test_unit_ready || - cmd_read_capacity || cmd_mode_select || cmd_format || cmd_mode_sense; + cmd_read_capacity || cmd_mode_select || cmd_format || cmd_mode_sense || + cmd_read_buffer | cmd_write_buffer; // latch parameters once command is complete reg [31:0] lba; @@ -302,9 +313,9 @@ always @(posedge clk) begin // continue according to command // these commands return data - if(cmd_read || cmd_inquiry || cmd_read_capacity || cmd_mode_sense) phase <= `PHASE_DATA_OUT; + if(cmd_read || cmd_inquiry || cmd_read_capacity || cmd_mode_sense || cmd_read_buffer) phase <= `PHASE_DATA_OUT; // these commands receive dataa - else if(cmd_write || cmd_mode_select) phase <= `PHASE_DATA_IN; + else if(cmd_write || cmd_mode_select || cmd_write_buffer) phase <= `PHASE_DATA_IN; // and all other valid commands are just "ok" else phase <= `PHASE_STATUS_OUT; end else begin diff --git a/rtl/sdram.sv b/rtl/sdram.v similarity index 52% rename from rtl/sdram.sv rename to rtl/sdram.v index 4791940..894c0da 100644 --- a/rtl/sdram.sv +++ b/rtl/sdram.v @@ -1,9 +1,9 @@ // +// sdram.v // -// sdram controller implementation for the MiST/MiSTer boards +// sdram controller implementation for the MiST board // // Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig // // This source file is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published @@ -19,36 +19,30 @@ // along with this program. If not, see . // -// -// -// This SDRAM module provides/writes the data in 8 cycles of clock. -// So, with 64MHz of system clock, it can emulate 8MHz asynchronous DRAM. -// -// - -module sdram +module sdram ( - output sd_clk, - inout reg [15:0] sd_data, // 16 bit bidirectional data bus - output reg [12:0] sd_addr, // 13 bit multiplexed address bus - output [1:0] sd_dqm, // two byte masks - output reg [1:0] sd_ba, // two banks - output sd_cs, // a single chip select - output sd_we, // write enable - output sd_ras, // row address select - output sd_cas, // columns address select + // interface to the MT48LC16M16 chip + output sd_clk, + inout reg [15:0] sd_data, // 16 bit bidirectional data bus + output reg [12:0] sd_addr, // 13 bit multiplexed address bus + output [1:0] sd_dqm, // two byte masks + output reg [1:0] sd_ba, // two banks + output sd_cs, // a single chip select + output sd_we, // write enable + output sd_ras, // row address select + output sd_cas, // columns address select // cpu/chipset interface - input init, // init signal after FPGA config to initialize RAM - input clk, // sdram is accessed at 64MHz - input sync, + input init, // init signal after FPGA config to initialize RAM + input clk_64, // sdram is accessed at 64MHz + input clk_8, // 8MHz chipset clock to which sdram state machine is synchonized - input [15:0] din, // data input from chipset/cpu - output reg [15:0] dout, // data output to chipset/cpu - input [23:0] addr, // 24 bit word address - input [1:0] ds, // upper/lower data strobe - input oe, // cpu/chipset requests read - input we // cpu/chipset requests write + input [15:0] din, // data input from chipset/cpu + output reg [15:0] dout, // data output to chipset/cpu + input [23:0] addr, // 24 bit word address + input [1:0] ds, // upper/lower data strobe + input oe, // cpu/chipset requests read + input we // cpu/chipset requests write ); localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 3 cycles@128MHz @@ -69,10 +63,20 @@ localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, B // It wraps from T15 to T0 on the rising edge of clk_8 localparam STATE_FIRST = 3'd0; // first state in cycle -localparam STATE_CMD_START = 3'd1; // state in which a new command can be started -localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY; // command can be continued +localparam STATE_CMD_START = 3'd0; // state in which a new command can be started +localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY; // command can be continued localparam STATE_READ = STATE_CMD_CONT + CAS_LATENCY + 4'd1; +localparam STATE_LAST = 3'd7; // last state in cycle +reg [2:0] t; +always @(posedge clk_64) begin + // 128Mhz counter synchronous to 8 Mhz clock + // force counter to pass state 0 exactly after the rising edge of clk_8 + if(((t == STATE_LAST) && ( clk_8 == 0)) || + ((t == STATE_FIRST) && ( clk_8 == 1)) || + ((t != STATE_LAST) && (t != STATE_FIRST))) + t <= t + 3'd1; +end // --------------------------------------------------------------------- // --------------------------- startup/reset --------------------------- @@ -81,98 +85,89 @@ localparam STATE_READ = STATE_CMD_CONT + CAS_LATENCY + 4'd1; // wait 1ms (32 8Mhz cycles) after FPGA config is done before going // into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0) reg [4:0] reset; -always @(posedge clk) begin +always @(posedge clk_64) begin if(init) reset <= 5'h1f; - else if((stage == STATE_FIRST) && (reset != 0)) + else if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1; end +initial reset = 5'h1F; + // --------------------------------------------------------------------- // ------------------ generate ram control signals --------------------- // --------------------------------------------------------------------- // all possible commands -localparam CMD_NOP = 3'b111; -localparam CMD_ACTIVE = 3'b011; -localparam CMD_READ = 3'b101; -localparam CMD_WRITE = 3'b100; -localparam CMD_BURST_TERMINATE = 3'b110; -localparam CMD_PRECHARGE = 3'b010; -localparam CMD_AUTO_REFRESH = 3'b001; -localparam CMD_LOAD_MODE = 3'b000; +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; -reg [2:0] sd_cmd; // current command sent to sd ram +reg [3:0] sd_cmd; // current command sent to sd ram // drive control signals according to current command -assign sd_cs = 1'b0; +assign sd_cs = sd_cmd[3]; assign sd_ras = sd_cmd[2]; assign sd_cas = sd_cmd[1]; assign sd_we = sd_cmd[0]; assign sd_dqm = sd_addr[12:11]; -reg [1:0] mode; -reg [15:0] din_r; -reg [2:0] stage; +reg oe_latch, we_latch; -always @(posedge clk) begin - reg [12:0] addr_r; - reg old_sync; - - sd_data <= 16'hZZZZ; - - if(|stage) stage <= stage + 1'd1; - - old_sync <= sync; - if(~old_sync & sync) stage <= 1; - - sd_cmd <= CMD_NOP; // default: idle +always @(posedge clk_64) begin + sd_cmd <= CMD_INHIBIT; // default: idle + sd_data <= 16'bZZZZZZZZZZZZZZZZ; if(reset != 0) begin // initialization takes place at the end of the reset phase - if(stage == STATE_CMD_START) begin + if(t == STATE_CMD_START) begin if(reset == 13) begin sd_cmd <= CMD_PRECHARGE; sd_addr[10] <= 1'b1; // precharge all banks end - + if(reset == 2) begin sd_cmd <= CMD_LOAD_MODE; sd_addr <= MODE; end - + end - mode <= 0; end else begin - // normal operation - if(stage == STATE_CMD_START) begin - if(we || oe) begin - mode <= {we, oe}; - - // RAS phase - sd_cmd <= CMD_ACTIVE; + // RAS phase + // ------------------- cpu/chipset read/write ---------------------- + if(t == STATE_CMD_START) begin + {oe_latch, we_latch} <= {oe, we}; + if (we || oe) begin + sd_cmd <= CMD_ACTIVE; sd_addr <= { 1'b0, addr[19:8] }; - sd_ba <= addr[21:20]; - - din_r <= din; - addr_r <= {we ? ~ds : 2'b00, 2'b10, addr[22], addr[7:0] }; // auto precharge + sd_ba <= addr[21:20]; end + // ------------------------ no access -------------------------- else begin sd_cmd <= CMD_AUTO_REFRESH; - mode <= 0; end end // CAS phase - if(stage == STATE_CMD_CONT && mode) begin - sd_cmd <= mode[1] ? CMD_WRITE : CMD_READ; - sd_addr <= addr_r; - if(mode[1]) sd_data <= din_r; + if(t == STATE_CMD_CONT && (we_latch || oe_latch)) begin + sd_cmd <= we_latch?CMD_WRITE:CMD_READ; + if (we_latch) sd_data <= din; + // always return both bytes in a read. The cpu may not + // need it, but the caches need to be able to store everything + sd_addr <= { we_latch ? ~ds : 2'b00, 2'b10, addr[22], addr[7:0] }; // auto precharge end - if(stage == STATE_READ && mode[0]) dout <= sd_data; + // Data ready + if (t == STATE_READ && oe_latch) dout <= sd_data; + end end @@ -191,7 +186,7 @@ sdramclk_ddr ( .datain_h(1'b0), .datain_l(1'b1), - .outclock(clk), + .outclock(clk_64), .dataout(sd_clk), .aclr(1'b0), .aset(1'b0), diff --git a/rtl/tg68k/TG68K.qip b/rtl/tg68k/TG68K.qip index 8daf12b..c3a0fb5 100644 --- a/rtl/tg68k/TG68K.qip +++ b/rtl/tg68k/TG68K.qip @@ -1,3 +1,4 @@ set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) TG68K_ALU.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) TG68K_Pack.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) TG68KdotC_Kernel.vhd ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) tg68k.v ] diff --git a/rtl/tg68k/TG68K_ALU.vhd b/rtl/tg68k/TG68K_ALU.vhd index 9ddd1b6..7430387 100644 --- a/rtl/tg68k/TG68K_ALU.vhd +++ b/rtl/tg68k/TG68K_ALU.vhd @@ -44,6 +44,7 @@ generic( exec_tas : in std_logic; long_start : in bit; non_aligned : in std_logic; + check_aligned : in std_logic; movem_presub : in bit; set_stop : in bit; Z_error : in bit; @@ -286,7 +287,7 @@ PROCESS (OP2out, reg_QB, opcode, OP1out, OP1in, exe_datatype, addsub_q, execOPC, -- addsub ----------------------------------------------------------------------------- PROCESS (OP1out, OP2out, execOPC, Flags, long_start, movem_presub, exe_datatype, exec, addsub_a, addsub_b, opaddsub, - notaddsub_b, add_result, c_in, sndOPC, non_aligned) + notaddsub_b, add_result, c_in, sndOPC, non_aligned, check_aligned) BEGIN addsub_a <= OP1out; IF exec(get_bfoffset)='1' THEN @@ -327,7 +328,7 @@ PROCESS (OP1out, OP2out, execOPC, Flags, long_start, movem_presub, exe_datatype, END IF; -- patch for un-aligned movem --mikej - if (exec(movem_action) = '1') then + if exec(movem_action)='1' OR check_aligned='1' then if (movem_presub = '0') then -- up if (non_aligned = '1') and (long_start = '0') then -- hold addsub_b <= (others => '0'); @@ -840,7 +841,49 @@ process (OP1out, OP2out, opcode, bit_nr, bit_msb, bs_shift, bs_shift_mod, ring, END IF; -- calc shift count - bs_shift_mod <= std_logic_vector(unsigned(bs_shift) rem unsigned(ring)); + -- bs_shift_mod <= std_logic_vector(unsigned(bs_shift) rem unsigned(ring)); + -- replace the divider with logic + CASE ring IS + WHEN "001001" => + IF bs_shift = 63 THEN + bs_shift_mod <= "000000"; + ELSIF bs_shift > 6*9-1 THEN + bs_shift_mod <= bs_shift - 6*9; + ELSIF bs_shift > 5*9-1 THEN + bs_shift_mod <= bs_shift - 5*9; + ELSIF bs_shift > 4*9-1 THEN + bs_shift_mod <= bs_shift - 4*9; + ELSIF bs_shift > 3*9-1 THEN + bs_shift_mod <= bs_shift - 3*9; + ELSIF bs_shift > 2*9-1 THEN + bs_shift_mod <= bs_shift - 2*9; + ELSIF bs_shift > 9-1 THEN + bs_shift_mod <= bs_shift - 9; + ELSE + bs_shift_mod <= bs_shift; + END IF; + WHEN "010001" => + IF bs_shift > 3*17-1 THEN + bs_shift_mod <= bs_shift - 3*17; + ELSIF bs_shift > 2*17-1 THEN + bs_shift_mod <= bs_shift - 2*17; + ELSIF bs_shift > 17-1 THEN + bs_shift_mod <= bs_shift - 17; + ELSE + bs_shift_mod <= bs_shift; + END IF; + WHEN "100001" => + IF bs_shift > 32 THEN + bs_shift_mod <= bs_shift - 33; + ELSE + bs_shift_mod <= bs_shift; + END IF; + WHEN "001000" => bs_shift_mod <= "000" & bs_shift(2 downto 0); + WHEN "010000" => bs_shift_mod <= "00" & bs_shift(3 downto 0); + WHEN "100000" => bs_shift_mod <= "0" & bs_shift(4 downto 0); + WHEN OTHERS => bs_shift_mod <= (OTHERS => '0'); + END CASE; + bit_nr <= bs_shift_mod(5 downto 0); IF exe_opcode(8)='0' THEN --right shift bit_nr <= ring-bs_shift_mod; @@ -969,12 +1012,15 @@ PROCESS (clk, Reset, exe_opcode, exe_datatype, Flags, last_data_read, OP2out, fl IF exec(to_CCR)='1' THEN Flags(7 downto 0) <= CCRin(7 downto 0); --CCR ELSIF Z_error='1' THEN - IF exe_opcode(8)='0' THEN + IF micro_state = trap0 THEN + -- Undocumented behavior (flags when div by zero) + IF exe_opcode(8)='0' THEN -- Flags(3 downto 0) <= reg_QA(31)&"000"; - Flags(3 downto 0) <= '0'&NOT reg_QA(31)&"00"; - ELSE - Flags(3 downto 0) <= "0100"; - END IF; + Flags(3 downto 0) <= '0'&NOT reg_QA(31)&"00"; + ELSE + Flags(3 downto 0) <= "0100"; + END IF; + END IF; ELSIF exec(no_Flags)='0' THEN last_Flags1 <= Flags(3 downto 0); IF exec(opcADD)='1' THEN @@ -1025,16 +1071,19 @@ PROCESS (clk, Reset, exe_opcode, exe_datatype, Flags, last_data_read, OP2out, fl Flags(1) <= BS_V; ELSIF exec(opcBITS)='1' THEN Flags(2) <= NOT one_bit_in; - ELSIF exec(opcCHK2)='1' THEN - Flags(0) <= '0'; - Flags(2) <= Flags(2) OR set_flags(2); + ELSIF exec(opcCHK2)='1' THEN --micro_state = chk23 +--micro_state chk21 chk22 chk23 +--OP1out UB R R +--OP2out LB LB UB ----lower bound first IF last_Flags1(0)='0' THEN --unsigned OP Flags(0) <= Flags(0) OR (NOT set_flags(0) AND NOT set_flags(2)); ELSE --signed OP - Flags(0) <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR --LT - (set_flags(3) AND set_flags(1) AND NOT set_flags(2)) OR (NOT set_flags(3) AND NOT set_flags(1) AND NOT set_flags(2)); --GT + Flags(0) <= (Flags(0) XOR set_flags(0)) AND NOT Flags(2) AND NOT set_flags(2); END IF; + Flags(1) <= '0'; + Flags(2) <= Flags(2) OR set_flags(2); + Flags(3) <= NOT last_Flags1(0); ELSIF exec(opcCHK)='1' THEN IF exe_datatype="01" THEN --Word Flags(3) <= OP1out(15); @@ -1242,7 +1291,9 @@ PROCESS (clk) BEGIN IF rising_edge(clk) THEN IF clkena_lw='1' THEN - V_Flag <= set_V_Flag; + IF micro_state/=div_end2 THEN + V_Flag <= set_V_Flag; + END IF; signedOP <= divs; IF micro_state=div1 THEN nozero <= '0'; @@ -1262,7 +1313,7 @@ PROCESS (clk) IF DIV_Mode=0 THEN div_over(32 downto 16) <= ('0'&div_reg(47 downto 32))-('0'&OP2out(15 downto 0)); ELSE - div_over <= ('0'&div_reg(63 downto 32))-('0'&OP2out); + div_over <= ('0'&div_reg(63 downto 32))-('0'&OP2outext(15 downto 0)&OP2out(15 downto 0)); END IF; END IF; IF exec(write_reminder)='0' THEN diff --git a/rtl/tg68k/TG68K_Pack.vhd b/rtl/tg68k/TG68K_Pack.vhd index 1d5eb5d..13580f3 100644 --- a/rtl/tg68k/TG68K_Pack.vhd +++ b/rtl/tg68k/TG68K_Pack.vhd @@ -143,7 +143,8 @@ package TG68K_Pack is exe_condition : in std_logic; exec_tas : in std_logic; long_start : in bit; - non_aligned : in std_logic; + non_aligned : in std_logic; + check_aligned : in std_logic; movem_presub : in bit; set_stop : in bit; Z_error : in bit; diff --git a/rtl/tg68k/TG68KdotC_Kernel.vhd b/rtl/tg68k/TG68KdotC_Kernel.vhd index 6bfcb01..1b361f5 100644 --- a/rtl/tg68k/TG68KdotC_Kernel.vhd +++ b/rtl/tg68k/TG68KdotC_Kernel.vhd @@ -21,6 +21,12 @@ ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ +-- 14.10.2020 TG bugfix chk2.b +-- 13.10.2020 TG go back to old aligned design and bugfix chk2 +-- 11.10.2020 TG next try CHK2 flags +-- 10.10.2020 TG bugfix division N-flag +-- 09.10.2020 TG bugfix division overflow +-- 2/3.10.2020 some tweaks by retrofun, gyurco and robinsonb5 -- 17.03.2020 TG bugfix move data to (extended address) -- 13.03.2020 TG bugfix extended addess mode - thanks Adam Polkosnik -- 15.02.2020 TG bugfix DIVS.W with result $8000 @@ -123,7 +129,8 @@ entity TG68KdotC_Kernel is nWr : out std_logic; nUDS : out std_logic; nLDS : out std_logic; - busstate : out std_logic_vector(1 downto 0); -- 00-> fetch code 10->read data 11->write data 01->no memaccess + busstate : out std_logic_vector(1 downto 0); -- 00-> fetch code 10->read data 11->write data 01->no memaccess + longword : out std_logic; nResetOut : out std_logic; FC : out std_logic_vector(2 downto 0); clr_berr : out std_logic; @@ -185,6 +192,8 @@ architecture logic of TG68KdotC_Kernel is signal addr : std_logic_vector(31 downto 0); signal memaddr_reg : std_logic_vector(31 downto 0); signal memaddr_delta : std_logic_vector(31 downto 0); + signal memaddr_delta_rega : std_logic_vector(31 downto 0); + signal memaddr_delta_regb : std_logic_vector(31 downto 0); signal use_base : bit; signal ea_data : std_logic_vector(31 downto 0); @@ -220,6 +229,7 @@ architecture logic of TG68KdotC_Kernel is signal writePC : bit; signal writePCbig : bit; signal set_writePCbig : bit; + signal writePCnext : bit; signal setopcode : bit; signal decodeOPC : bit; signal execOPC : bit; @@ -315,6 +325,7 @@ architecture logic of TG68KdotC_Kernel is signal long_start : bit; signal long_start_alu : bit; signal non_aligned : std_logic; + signal check_aligned : std_logic; signal long_done : bit; signal memmask : std_logic_vector(5 downto 0); signal set_memmask : std_logic_vector(5 downto 0); @@ -376,6 +387,7 @@ ALU: TG68K_ALU exec_tas => exec_tas, --: in std_logic; long_start => long_start_alu, --: in bit; non_aligned => non_aligned, + check_aligned => check_aligned, movem_presub => movem_presub, --: in bit; set_stop => set_stop, --: in bit; Z_error => Z_error, --: in bit; @@ -407,7 +419,10 @@ ALU: TG68K_ALU addsub_q => addsub_q, --: buffer std_logic_vector(31 downto 0); ALUout => ALUout --: buffer std_logic_vector(31 downto 0) ); - + + -- AMR - let the parent module know this is a longword access. (Easy way to enable burst writes.) + longword <= not memmaskmux(3); + long_start_alu <= to_bit(NOT memmaskmux(3)); execOPC_ALU <= execOPC OR exec(alu_exec); process (memmaskmux) @@ -731,6 +746,7 @@ PROCESS (clk) direct_data <= '0'; use_direct_data <= '0'; Z_error <= '0'; + writePCnext <= '0'; ELSIF clkena_lw='1' THEN useStackframe2<='0'; direct_data <= '0'; @@ -747,7 +763,8 @@ PROCESS (clk) IF endOPC='1' THEN store_in_tmp <='0'; - Z_error <= '0'; + Z_error <= '0'; + writePCnext <= '0'; ELSE IF set_Z_error='1' THEN Z_error <= '1'; @@ -780,6 +797,7 @@ PROCESS (clk) elsif micro_state=trap00 THEN data_write_tmp <= exe_pc; --TH useStackframe2<='1'; + writePCnext <= trap_trap OR trap_trapv OR exec(trap_chk) OR Z_error; elsif micro_state = trap0 then -- this is only active for 010+ since in 000 writePC is -- true in state trap0 @@ -789,6 +807,7 @@ PROCESS (clk) data_write_tmp(15 downto 0) <= "0010" & trap_vector(11 downto 0); --TH else data_write_tmp(15 downto 0) <= "0000" & trap_vector(11 downto 0); + writePCnext <= trap_trap OR trap_trapv OR exec(trap_chk) OR Z_error; end if; ------------------------------------ -- ELSIF micro_state=trap0 THEN @@ -845,7 +864,7 @@ PROCESS (brief, OP1out, OP1outbrief, cpu) -- MEM_IO ----------------------------------------------------------------------------- PROCESS (clk, setdisp, memaddr_a, briefdata, memaddr_delta, setdispbyte, datatype, interrupt, rIPL_nr, IPL_vec, - memaddr_reg, reg_QA, use_base, VBR, last_data_read, trap_vector, exec, set, cpu, use_VBR_Stackframe) + memaddr_reg, memaddr_delta_rega, memaddr_delta_regb, reg_QA, use_base, VBR, last_data_read, trap_vector, exec, set, cpu, use_VBR_Stackframe) BEGIN IF rising_edge(clk) THEN @@ -925,24 +944,26 @@ PROCESS (clk, setdisp, memaddr_a, briefdata, memaddr_delta, setdispbyte, datatyp tmp_TG68_PC <= addr; END IF; use_base <= '0'; + memaddr_delta_regb <= (others => '0'); IF memmaskmux(3)='0' OR exec(mem_addsub)='1' THEN - memaddr_delta <= addsub_q; - ELSIF set(restore_ADDR)='1' THEN - memaddr_delta <= tmp_TG68_PC; + memaddr_delta_rega <= addsub_q; + ELSIF set(restore_ADDR)='1' THEN + memaddr_delta_rega <= tmp_TG68_PC; ELSIF exec(direct_delta)='1' THEN - memaddr_delta <= data_read; + memaddr_delta_rega <= data_read; ELSIF exec(ea_to_pc)='1' AND setstate="00" THEN - memaddr_delta <= addr; + memaddr_delta_rega <= addr; ELSIF set(addrlong)='1' THEN - memaddr_delta <= last_data_read; - ELSIF setstate="00" THEN - memaddr_delta <= TG68_PC_add; + memaddr_delta_rega <= last_data_read; + ELSIF setstate="00" THEN + memaddr_delta_rega <= TG68_PC_add; ELSIF exec(dispouter)='1' THEN - memaddr_delta <= ea_data+memaddr_a; - ELSIF set_vectoraddr='1' THEN - memaddr_delta <= trap_vector_vbr; + memaddr_delta_rega <= ea_data; + memaddr_delta_regb <= memaddr_a; + ELSIF set_vectoraddr='1' THEN + memaddr_delta_rega <= trap_vector_vbr; ELSE - memaddr_delta <= memaddr_a; + memaddr_delta_rega <= memaddr_a; IF interrupt='0' AND Suppress_Base='0' THEN -- IF interrupt='0' AND Suppress_Base='0' AND setstate(1)='1' THEN use_base <= '1'; @@ -956,11 +977,12 @@ PROCESS (clk, setdisp, memaddr_a, briefdata, memaddr_delta, setdispbyte, datatyp END IF; END IF; END IF; - + + memaddr_delta <= memaddr_delta_rega + memaddr_delta_regb; -- if access done, and not aligned, don't increment addr <= memaddr_reg+memaddr_delta; addr_out <= memaddr_reg + memaddr_delta; - + IF use_base='0' THEN memaddr_reg <= (others=>'0'); ELSE @@ -972,7 +994,7 @@ PROCESS (clk, setdisp, memaddr_a, briefdata, memaddr_delta, setdispbyte, datatyp -- PC Calc + fetch opcode ----------------------------------------------------------------------------- PROCESS (clk, IPL, setstate, addrvalue, state, exec_write_back, set_direct_data, next_micro_state, stop, make_trace, make_berr, IPL_nr, FlagsSR, set_rot_cnt, opcode, writePCbig, set_exec, exec, - PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, interrupt, tmp_TG68_PC, TG68_PC) + PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, interrupt, tmp_TG68_PC, TG68_PC, use_VBR_Stackframe, writePCnext) BEGIN PC_dataa <= TG68_PC; @@ -995,7 +1017,7 @@ PROCESS (clk, IPL, setstate, addrvalue, state, exec_write_back, set_direct_data, ELSE PC_datab(2) <= '1'; END IF; - IF trap_trap='1' OR trap_trapv='1' OR exec(trap_chk)='1' OR Z_error='1' THEN + IF (use_VBR_Stackframe='0' AND (trap_trap='1' OR trap_trapv='1' OR exec(trap_chk)='1' OR Z_error='1')) OR writePCnext='1' THEN PC_datab(1) <= '1'; END IF; ELSIF state="00" THEN @@ -1354,7 +1376,11 @@ PROCESS (clk, Reset, FlagsSR, last_data_read, OP2out, exec) ELSE SVmode <= preSVmode; END IF; - END IF; + END IF; + IF trap_berr='1' OR trap_illegal='1' OR trap_addr_error='1' OR trap_priv='1' OR trap_1010='1' OR trap_1111='1' THEN + make_trace <= '0'; + FlagsSR(7) <= '0'; + END IF; IF set(changeMode)='1' THEN preSVmode <= NOT preSVmode; FlagsSR(5) <= NOT preSVmode; @@ -1397,7 +1423,7 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, build_bcd, set_Z_error, trapd, movem_run, last_data_read, set, set_V_Flag, z_error, trap_trace, trap_interrupt, SVmode, preSVmode, stop, long_done, ea_only, setstate, addrvalue, execOPC, exec_write_back, exe_datatype, datatype, interrupt, c_out, trapmake, rot_cnt, brief, addr, trap_trapv, last_data_in, use_VBR_Stackframe, - long_start, set_datatype, sndOPC, set_exec, exec, ea_build_now, reg_QA, reg_QB, make_berr, trap_berr) + long_start, set_datatype, sndOPC, set_exec, exec, ea_build_now, reg_QA, reg_QB, make_berr, trap_berr) BEGIN TG68_PC_brw <= '0'; setstate <= "00"; @@ -1449,6 +1475,7 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, -- illegal_read_mode <= '0'; -- illegal_byteaddr <= '0'; set_Z_error <= '0'; + check_aligned <='0'; next_micro_state <= idle; build_logical <= '0'; @@ -1489,13 +1516,12 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, setstate <= "01"; END IF; IF trapmake='1' AND trapd='0' THEN --- IF use_VBR_Stackframe='1' AND (trap_trapv='1' OR set_Z_error='1' OR exec(opcCHK)='1') THEN - IF use_VBR_Stackframe='1' AND (trap_trapv='1' OR set_Z_error='1' OR exec(trap_chk)='1') THEN + IF cpu(1)='1' AND (trap_trapv='1' OR set_Z_error='1' OR exec(trap_chk)='1') THEN next_micro_state <= trap00; else next_micro_state <= trap0; end if; - IF use_VBR_Stackframe='0' THEN + IF use_VBR_Stackframe='0' THEN set(writePC_add) <= '1'; -- set_datatype <= "10"; END IF; @@ -1506,7 +1532,7 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, END IF; IF micro_state=int1 OR (interrupt='1' AND trap_trace='1') THEN -- paste and copy form TH --------- - if trap_trace='1' AND use_VBR_Stackframe='1' then + if trap_trace='1' AND cpu(1) = '1' then next_micro_state <= trap00; --TH else next_micro_state <= trap0; @@ -1720,6 +1746,9 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, IF micro_state=idle AND nextpass='1' THEN setstate <= "10"; set(hold_OP2) <='1'; + IF exe_datatype/="00" THEN + check_aligned <='1'; + END IF; next_micro_state <= chk20; END IF; ELSE @@ -1748,7 +1777,7 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, ELSE --andi, ...xxxi IF opcode(7 downto 6)/="11" AND opcode(5 downto 3)/="001" THEN --ea An illegal mode IF opcode(11 downto 9)="000" THEN --ORI - IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" OR opcode(2 downto 0)="100" THEN + IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" OR (opcode(2 downto 0)="100" AND opcode(7)='0') THEN set_exec(opcOR) <= '1'; ELSE trap_illegal <= '1'; @@ -1756,7 +1785,7 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, END IF; END IF; IF opcode(11 downto 9)="001" THEN --ANDI - IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" OR opcode(2 downto 0)="100" THEN + IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" OR (opcode(2 downto 0)="100" AND opcode(7)='0') THEN set_exec(opcAND) <= '1'; ELSE trap_illegal <= '1'; @@ -1772,7 +1801,7 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, END IF; END IF; IF opcode(11 downto 9)="101" THEN --EORI - IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" OR opcode(2 downto 0)="100" THEN + IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" OR (opcode(2 downto 0)="100" AND opcode(7)='0') THEN set_exec(opcEOR) <= '1'; ELSE trap_illegal <= '1'; @@ -2628,7 +2657,7 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, trap_illegal <= '1'; trapmake <= '1'; END IF; - ELSE --Scc + ELSIF (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --Scc datatype <= "00"; --Byte ea_build_now <= '1'; write_back <= '1'; @@ -2638,7 +2667,10 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, END IF; IF opcode(5 downto 4)="00" THEN set_exec(Regwrena) <= '1'; - END IF; + END IF; + ELSE + trap_illegal <= '1'; + trapmake <= '1'; END IF; ELSE --addq, subq IF opcode(7 downto 3)/="00001" AND @@ -3970,7 +4002,7 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, ----------------------------------------------------------------------------- -- MOVEC ----------------------------------------------------------------------------- - process (clk, VBR, CACR, brief) + process (clk, SFC, DFC, VBR, CACR, brief) begin -- all other hexa codes should give illegal isntruction exception if rising_edge(clk) then @@ -3979,8 +4011,8 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, CACR <= (others => '0'); elsif clkena_lw = '1' and exec(movec_wr) = '1' then case brief(11 downto 0) is - when X"000" => NULL; -- SFC -- 68010+ - when X"001" => NULL; -- DFC -- 68010+ + when X"000" => SFC <= reg_QA(2 downto 0); -- SFC -- 68010+ + when X"001" => DFC <= reg_QA(2 downto 0); -- DFC -- 68010+ when X"002" => CACR <= reg_QA(3 downto 0); -- 68020+ when X"800" => NULL; -- USP -- 68010+ when X"801" => VBR <= reg_QA; -- 68010+ @@ -3994,6 +4026,8 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, movec_data <= (others => '0'); case brief(11 downto 0) is + when X"000" => movec_data <= "00000000000000000000000000000" & SFC; + when X"001" => movec_data <= "00000000000000000000000000000" & DFC; when X"002" => movec_data <= "0000000000000000000000000000" & (CACR AND "0011"); when X"801" => diff --git a/rtl/tg68k/tg68k.v b/rtl/tg68k/tg68k.v new file mode 100644 index 0000000..c7a40ac --- /dev/null +++ b/rtl/tg68k/tg68k.v @@ -0,0 +1,226 @@ +/* + 68000 compatible bus-wrapper for TG68K + */ + +module tg68k ( + input clk, + input reset, + input phi1, + input phi2, + input [1:0] cpu, + + input dtack_n, + output rw_n, + output as_n, + output uds_n, + output lds_n, + output [2:0] fc, + output reset_n, + + output reg E, + input E_div, + output E_PosClkEn, + output E_NegClkEn, + output vma_n, + input vpa_n, + + input br_n, + output bg_n, + input bgack_n, + + input [2:0] ipl, + input berr, + input [15:0] din, + output [15:0] dout, + output reg [31:0] addr +); + +wire [1:0] tg68_busstate; +wire tg68_clkena = phi1 && (s_state == 7 || tg68_busstate == 2'b01); +wire [31:0] tg68_addr; +wire [15:0] tg68_din; +reg [15:0] tg68_din_r; +wire tg68_uds_n; +wire tg68_lds_n; +wire tg68_rw; + +// The tg68k core doesn't reliably support mixed usage of autovector and non-autovector +// interrupts, so the TG68K kernel switched to non-autovector interrupts, and the +// auto-vectors are provided here. +wire auto_iack = fc == 3'b111 && !vpa_n; +wire [7:0] auto_vector = {4'h1, 1'b1, addr[3:1]}; +assign tg68_din = auto_iack ? {auto_vector, auto_vector} : din; + +reg uds_n_r; +reg lds_n_r; +reg rw_r; +reg as_n_r; + +assign as_n = as_n_r; +assign uds_n = uds_n_r; +assign lds_n = lds_n_r; +assign rw_n = rw_r; + +reg [2:0] s_state; + +always @(posedge clk) begin + if (reset) begin + s_state <= 0; + as_n_r <= 1; + rw_r <= 1; + uds_n_r <= 1; + lds_n_r <= 1; + end else begin + addr <= tg68_addr; + + if (phi1) begin + + if (s_state != 4) s_state <= s_state + 1'd1; + if (busreq_ack || bus_granted) s_state <= s_state; + if (tg68_busstate == 2'b01) s_state <= 0; + + case (s_state) + 1: if (tg68_busstate != 2'b01) begin + rw_r <= tg68_rw; + if (tg68_rw) begin + uds_n_r <= tg68_uds_n; + lds_n_r <= tg68_lds_n; + end + as_n_r <= 0; + end + 3: if (tg68_busstate != 2'b01) begin + if (!tg68_rw) begin + uds_n_r <= tg68_uds_n; + lds_n_r <= tg68_lds_n; + end + end + 7: rw_r <= 1; + default :; + endcase + + end else if (phi2) begin + + if (s_state != 4 || tg68_busstate == 2'b01 || !dtack_n || xVma || berr) + s_state <= s_state + 1'd1; + if ((busreq_ack || bus_granted) && !busrel_ack) s_state <= s_state; + if (tg68_busstate == 2'b01) s_state <= 0; + + case (s_state) + + 6: begin + tg68_din_r <= tg68_din; + uds_n_r <= 1; + lds_n_r <= 1; + as_n_r <= 1; + end + default :; + endcase + + end + end +end + +// from FX68K +// E clock and counter, VMA +reg [3:0] eCntr; +reg rVma; +reg Vpai; +assign vma_n = rVma; + +// Internal stop just one cycle before E falling edge +wire xVma = ~rVma & (eCntr == 8) & en_E; + +assign E_PosClkEn = (phi2 & (eCntr == 5) & en_E); +assign E_NegClkEn = (phi2 & (eCntr == 9) & en_E); + +reg en_E; + +always @( posedge clk) begin + if (reset) begin + E <= 1'b0; + eCntr <=0; + rVma <= 1'b1; + en_E <= 1'b1; + end else begin + if (phi1) begin + Vpai <= vpa_n; + if (E_div) en_E <= !en_E; else en_E <= 1'b1; + end + + if (phi2 & en_E) begin + if (eCntr == 9) + E <= 1'b0; + else if (eCntr == 5) + E <= 1'b1; + + if (eCntr == 9) + eCntr <= 0; + else + eCntr <= eCntr + 1'b1; + end + + if (phi2 & s_state != 0 & ~Vpai & (eCntr == 3) & en_E) + rVma <= 1'b0; + else if (phi1 & eCntr == 0 & en_E) + rVma <= 1'b1; + end +end + +// Bus arbitration +reg bg_n_r; +assign bg_n = bg_n_r; + +// process the bus request at the start of any bus cycle +// (start at only instruction fetch doesn't work well with ACSI DMA) +wire busreq_ack = !br_n /*&& tg68_busstate == 0*/ && s_state == 0; +wire busrel_ack = bus_acked && !bgack; + +reg bgack, bus_granted, bus_acked, bus_acked_d; + +always @(posedge clk) begin + if (reset) begin + bg_n_r <= 1; + bus_granted <= 0; + bus_acked <= 0; + end else begin + if (phi1) begin + bgack <= ~bgack_n; + bus_acked_d <= bus_acked; + end + if (phi2) begin + if (busreq_ack) begin + bg_n_r <= 0; + bus_granted <= 1; + bus_acked <= bgack; + end + if (bus_granted && bgack) bus_acked <= 1; + if (bus_granted && bus_acked_d) bg_n_r <= 1; + if (busrel_ack) begin + bus_acked <= 0; + bus_granted <= 0; + end + end + end +end + +TG68KdotC_Kernel #(2,2,2,2,2,2,2,1) tg68k ( + .clk ( clk ), + .nReset ( ~reset ), + .clkena_in ( tg68_clkena ), + .data_in ( tg68_din_r ), + .IPL ( ipl ), + .IPL_autovector ( 1'b0 ), + .berr ( berr ), + .clr_berr ( /*tg68_clr_berr*/ ), + .CPU ( cpu ), // 00->68000 01->68010 11->68020(only some parts - yet) + .addr_out ( tg68_addr ), + .data_write ( dout ), + .nUDS ( tg68_uds_n ), + .nLDS ( tg68_lds_n ), + .nWr ( tg68_rw ), + .busstate ( tg68_busstate ), // 00-> fetch code 10->read data 11->write data 01->no memaccess + .nResetOut ( reset_n ), + .FC ( fc ) +); + +endmodule diff --git a/rtl/via.v b/rtl/via.v deleted file mode 100644 index 16930b8..0000000 --- a/rtl/via.v +++ /dev/null @@ -1,365 +0,0 @@ -/* VIA - - This implementation assumes the I/O data directions and PCR edge triggers used in the Macintosh, - and ignores most writes to the VIA data direction registers and the PCR. - - The 16 VIA registers are mapped to addresses {8'hEF, 8'b111xxxx1, 8'hFE}: - 0 $0 vBufB register B - 1 $200 ????? register A (controls handshake) - 2 $400 vDirB register B direction register - 3 $600 vDirA register A direction register - 4 $800 vT1C timer 1 counter (low-order byte) - for sound? - 5 $A00 vT1CH timer 1 counter (high-order byte) - 6 $C00 vT1L timer 1 latch (low-order byte) - 7 $E00 vT1LH timer 1 latch (high-order byte) - 8 $1000 vT2C timer 2 counter (low-order byte) - W: writes T2L-L R: read T2C-L and clear interrupt flag - 9 $1200 vT2CH timer 2 counter (high-order byte) - W: write T2C-H, transfer T2L-L to T2C-L, clear interrupt flag R: read T2C-H - 10 $1400 vSR shift register (keyboard) - 11 $1600 vACR auxiliary control register - 12 $1800 vPCR peripheral control register - 13 $1A00 vIFR interrupt flag register - 14 $1C00 vIER interrupt enable register - 15 $1E00 vBufA register A (no handshake) - - Register A: - Bit(s) Name Dir Description - - 7 vSCCWReq in SCC wait/request - 6 vPage2 out Alternate screen buffer (1 = main buffer) - 5 vHeadSel out Disk SEL line - 4 vOverlay out ROM low-memory overlay (1 = overlay on) - 3 vSndPg2 out Alternate sound buffer (1 = main buffer) - 0-2 vSound (mask) out Sound volume - - Register B: - Bit Name Dir Description - - 7 vSndEnb out Sound enable/disable - 6 vH4 in Horizontal blanking - 5 vY2 in Mouse Y2 - 4 vX2 in Mouse X2 - 3 vSW in Mouse switch - 2 rTCEnb out Real-time clock serial enable (active low I think) - 1 rTCClk out Real-time clock data-clock line - 0 rTCData in/out Real-time clock serial data - - Interrupt flag and enable registers: - IFR bit 7: remains set (and the IRQ line to the processor is held low) as long as any enabled VIA - interrupt is occurring. - IER bit 7: "enable/disable": If bit 7 is a 1, each 1 in bits 0-6 enables the corresponding interrupt; - if bit 7 is a 0, each 1 in bits 0-6 disables that interrupt. In either case, 0's in bits 0-6 do not - change the status of those interrupts. Bit 7 is always read as a 1. - - Bit Interrupting device - - 7 IRQ (IFR) or enable (IER) - 6 Timer 1 timeout - 5 Timer 2 timeout - 4 Keyboard clock (CB1) - 3 Keyboard data bit (CB2) - 2 Keyboard data ready (completion of 8 shifts) (SR) - 1 Vertical blanking interrupt (CA1) - 0 One-second interrupt (CA2) - - Peripheral control register: - Bit Description - - 5-7 CB2 control (keyboard data bit) - 4 CB1 control (keyboard clock) - 1-3 CA2 control (one-second interrupt) - 0 CA1 control (vertical blanking interrupt) - - 1-bit controls: 0 = negative edge trigger (normal Macintosh mode), 1 = positive edge trigger - 3-bit controls: - 000 set IFR on negative edge, clear IFR on read/write from register A/B. Normal Macintosh mode. - 001 set IFR on negative edge - 010 set IFR on positive edge, clear IFR on read/write from register A/B - 011 set IFR on positive edge - 100-111 not used in Macintosh (output mode) - - Auxiliary control register: - Bit Description - 6-7 T1 control, 00 = one-shot mode, output to PB7 disabled, 11 = free running mode, output to PB7 enabled - 5 T2 control, 0 = interval timer in one-shot mode (Mac mode), 1 = counts a predetermined number of pulses on pin PB6 (not used) - 2-4 shift register control - 1 PB latch enable - 0 PA latch enable - - Timer 2: - For Macintosh, always operates as a one-shot inerval timer. - 8 $1000 vT2C W: write T2L-L R: read T2C-L and clear interrupt flag - 9 $1200 vT2CH W: write T2C-H, transfer T2L-L to T2C-L, clear interrupt, arms timer flag R: read T2C-H -*/ - -`define INT_ONESEC 0 -`define INT_VBLANK 1 -`define INT_KEYREADY 2 -`define INT_KEYBIT 3 -`define INT_KEYCLK 4 -`define INT_T2 5 -`define INT_T1 6 - -module via -( - input clk, - input cep, - input cen, - - input _reset, - input selectVIA, - input _cpuRW, - input _cpuUDS, - input [15:0] dataIn, - input [3:0] cpuAddrRegHi, - input _hblank, - input _vblank, - input mouseY2, - input mouseX2, - input mouseButton, - input rtcData, - input sccWReq, - output _irq, - output [15:0] dataOut, - output memoryOverlayOn, - output SEL, // to IWM - - output snd_ena, - output snd_alt, - output [2:0] snd_vol, - - input [7:0] kbd_in_data, - input kbd_in_strobe, - output [7:0] kbd_out_data, - output reg kbd_out_strobe -); - - wire [7:0] dataInHi = dataIn[15:8]; - reg [7:0] dataOutHi; - assign dataOut = { dataOutHi, 8'hEF }; - - reg [7:0] viaADataOut; - reg [7:0] viaBDataOut; - reg viaB0DDR; - reg [6:0] viaIFR; - reg [6:0] viaIER; - reg [7:0] viaACR; - reg [7:0] viaSR; - reg [15:0] viaTimer1Count; - reg [15:0] viaTimer1Latch; - reg [15:0] viaTimer2Count; - reg [7:0] viaTimer2LatchLow; - reg viaTimer2Armed; - - - // shift register can be written by CPU and by external source - /* Write to SR (including external input) */ - assign kbd_out_data = viaSR; - always @(posedge clk or negedge _reset) begin - if (_reset == 1'b0) - viaSR <= 8'b0; - else if(cen) begin - if((selectVIA == 1'b1) && (_cpuUDS == 1'b0) && - (_cpuRW == 1'b0) && (cpuAddrRegHi == 4'hA)) - viaSR <= dataInHi; - - if (viaACR[4:2] == 3'b011 && kbd_in_strobe) - viaSR <= kbd_in_data; - end - end - - /* Generate sr_out_strobe */ - always @(posedge clk or negedge _reset) begin - if (_reset == 1'b0) - kbd_out_strobe <= 1'b0; - else if(cen) begin - if((selectVIA == 1'b1) && (_cpuUDS == 1'b0) && - (_cpuRW == 1'b0) && (cpuAddrRegHi == 4'hA) && - (viaACR[4:2] == 3'b111)) - kbd_out_strobe <= 1; - else - kbd_out_strobe <= 0; - end - end - - // divide by 10 clock divider for the VIA timers: 0.78336 MHz - reg [3:0] clkDiv; - always @(posedge clk) begin - if(cep) begin - if (clkDiv == 4'h9) - clkDiv <= 0; - else - clkDiv <= clkDiv + 1'b1; - end - end - wire timerStrobe = (clkDiv == 0); - - // store previous vblank value, for edge detection - reg _lastVblank; - always @(posedge clk) if(cen) _lastVblank <= _vblank; - - // count vblanks, and set 1 second interrupt after 60 vblanks - reg [5:0] vblankCount; - always @(posedge clk) begin - if(cen) begin - if (_vblank == 1'b0 && _lastVblank == 1'b1) begin - if (vblankCount != 59) begin - vblankCount <= vblankCount + 1'b1; - end - else begin - vblankCount <= 6'h0; - end - end - end - end - assign _irq = (viaIFR & viaIER) == 0 ? 1'b1 : 1'b0; - - // register write - wire loadT2 = selectVIA == 1'b1 && _cpuUDS == 1'b0 && _cpuRW == 1'b0 && cpuAddrRegHi == 4'h9; - always @(posedge clk or negedge _reset) begin - if (_reset == 1'b0) begin - viaB0DDR <= 1'b1; - viaADataOut <= 8'b01111111; - viaBDataOut <= 8'b11111111; - viaIFR <= 7'b0000000; - viaIER <= 7'b0000000; - viaACR <= 8'b00000000; - viaTimer1Count <= 16'h0000; - viaTimer1Latch <= 16'h0000; - viaTimer2Count <= 16'h0000; - viaTimer2LatchLow <= 8'h00; - viaTimer2Armed <= 0; - end - else if(cen) begin - if (selectVIA == 1'b1 && _cpuUDS == 1'b0) begin - if (_cpuRW == 1'b0) begin - // normal register writes - case (cpuAddrRegHi) - 4'h0: // B - viaBDataOut <= dataInHi; - 4'h2: // B DDR - viaB0DDR <= dataInHi[0]; - // 4'h3: ignore A DDR - 4'h4: // timer 1 count low - viaTimer1Count[7:0] <= dataInHi; - 4'h5: // timer 1 count high - viaTimer1Count[15:8] <= dataInHi; - 4'h6: // timer 1 latch low - viaTimer1Latch[7:0] <= dataInHi; - 4'h7: // timer 1 latch high - viaTimer1Latch[15:8] <= dataInHi; - 4'h8: // timer 2 latch low - viaTimer2LatchLow <= dataInHi; - 4'h9: begin // timer 2 count high - viaTimer2Count[15:8] <= dataInHi; - viaTimer2Count[7:0] <= viaTimer2LatchLow; - viaTimer2Armed = 1'b1; - viaIFR[`INT_T2] <= 1'b0; - end - 4'hA: begin // shift register - if( viaACR[4:2] == 3'b111 ) - viaIFR[`INT_KEYREADY] <= 1'b1; - end - 4'hB: // Aux control register - viaACR <= dataInHi; - // 4'hC: ignore PCR - 4'hD: // IFR - viaIFR <= viaIFR & ~dataInHi[6:0]; - 4'hE: // IER - if (dataInHi[7]) - viaIER <= viaIER | dataInHi[6:0]; - else - viaIER <= viaIER & ~dataInHi[6:0]; - 4'hF: // A - viaADataOut <= dataInHi; - endcase - end - else begin - // interrupt flag modifications due to register reads - case (cpuAddrRegHi) - 4'h0: begin // reading (and writing?) register B clears KEYCLK and KEYBIT interrupt flags - viaIFR[`INT_KEYCLK] <= 1'b0; - viaIFR[`INT_KEYBIT] <= 1'b0; - end - 4'h8: // reading T2C-L clears the T2 interrupt flag - viaIFR[`INT_T2] <= 1'b0; - 4'hA: // reading SR clears the SR interrupt flag - viaIFR[`INT_KEYREADY] <= 1'b0; - 4'hF: begin // reading (and writing?) register A clears VBLANK and ONESEC interrupt flags - viaIFR[`INT_ONESEC] <= 1'b0; - viaIFR[`INT_VBLANK] <= 1'b0; - end - endcase - end - end - // external interrupts - if (_vblank == 1'b0 && _lastVblank == 1'b1) begin - viaIFR[`INT_VBLANK] <= 1'b1; // set vblank interrupt - if (vblankCount == 59) - viaIFR[`INT_ONESEC] <= 1'b1; // set one second interrupt after 60 vblanks - end - // timer 2 - if (timerStrobe && !loadT2) begin - if (viaTimer2Armed && viaTimer2Count == 0) begin - viaIFR[`INT_T2] <= 1'b1; - viaTimer2Armed <= 0; - end - viaTimer2Count <= viaTimer2Count - 1'b1; - end - - // Shift in under control of external clock - if (viaACR[4:2] == 3'b011 && kbd_in_strobe) - viaIFR[`INT_KEYREADY] <= 1; - - end - end - - // register read - always @(*) begin - dataOutHi = 8'hBE; - - case (cpuAddrRegHi) - 4'h0: // B - // TODO: clear CB1 and CB2 interrupts - dataOutHi = { viaBDataOut[7], ~_hblank, mouseY2, mouseX2, mouseButton, viaBDataOut[2:1], viaB0DDR == 1'b1 ? viaBDataOut[0] : rtcData }; - 4'h2: // B DDR - dataOutHi = { 7'b1000011, viaB0DDR }; - 4'h3: // A DDR - dataOutHi = 8'b01111111; - 4'h4: // timer 1 count low - dataOutHi = viaTimer1Count[7:0]; - 4'h5: // timer 1 count high - dataOutHi = viaTimer1Count[15:8]; - 4'h6: // timer 1 latch low - dataOutHi = viaTimer1Latch[7:0]; - 4'h7: // timer 1 latch high - dataOutHi = viaTimer1Latch[15:8]; - 4'h8: // timer 2 count low - dataOutHi = viaTimer2Count[7:0]; - 4'h9: // timer 2 count high - dataOutHi = viaTimer2Count[15:8]; - 4'hA: // shift register - dataOutHi = viaSR; - 4'hB: // Aux control register - dataOutHi = viaACR; - 4'hC: // PCR - dataOutHi = 0; - 4'hD: // IFR - dataOutHi = { viaIFR & viaIER == 0 ? 1'b0 : 1'b1, viaIFR }; - 4'hE: // IER - dataOutHi = { 1'b1, viaIER }; - 4'hF: // A - // TODO: clear CA1 and CA2 interrupts - dataOutHi = { sccWReq, viaADataOut[6:0] }; - default: - dataOutHi = 8'hBE; - endcase - end - - assign snd_vol = viaADataOut[2:0]; - assign snd_alt = !viaADataOut[3]; - assign snd_ena = viaBDataOut[7]; - - assign memoryOverlayOn = viaADataOut[4]; - assign SEL = viaADataOut[5]; - -endmodule diff --git a/rtl/via6522.vhd b/rtl/via6522.vhd new file mode 100644 index 0000000..b3e65ed --- /dev/null +++ b/rtl/via6522.vhd @@ -0,0 +1,705 @@ +------------------------------------------------------------------------------- +-- Title : VIA 6522 +------------------------------------------------------------------------------- +-- Author : Gideon Zweijtzer +------------------------------------------------------------------------------- +-- Description: This module implements the 6522 VIA chip. +-- A LOT OF REVERSE ENGINEERING has been done to make this module +-- as accurate as it is now. Thanks to gyurco for ironing out some +-- differences that were left unnoticed. +------------------------------------------------------------------------------- +-- License: GPL 3.0 - Free to use, distribute and change to your own needs. +-- Leaving a reference to the author will be highly appreciated. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity via6522 is +port ( + clock : in std_logic; + rising : in std_logic; + falling : in std_logic; + reset : in std_logic; + + addr : in std_logic_vector(3 downto 0); + wen : in std_logic; + ren : in std_logic; + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0); + + phi2_ref : out std_logic; + + -- pio -- + port_a_o : out std_logic_vector(7 downto 0); + port_a_t : out std_logic_vector(7 downto 0); + port_a_i : in std_logic_vector(7 downto 0); + + port_b_o : out std_logic_vector(7 downto 0); + port_b_t : out std_logic_vector(7 downto 0); + port_b_i : in std_logic_vector(7 downto 0); + + -- handshake pins + ca1_i : in std_logic; + + ca2_o : out std_logic; + ca2_i : in std_logic; + ca2_t : out std_logic; + + cb1_o : out std_logic; + cb1_i : in std_logic; + cb1_t : out std_logic; + + cb2_o : out std_logic; + cb2_i : in std_logic; + cb2_t : out std_logic; + + irq : out std_logic ); + +end via6522; + +architecture Gideon of via6522 is + + type pio_t is + record + pra : std_logic_vector(7 downto 0); + ddra : std_logic_vector(7 downto 0); + prb : std_logic_vector(7 downto 0); + ddrb : std_logic_vector(7 downto 0); + end record; + + constant pio_default : pio_t := (others => (others => '0')); + constant latch_reset_pattern : std_logic_vector(15 downto 0) := X"5550"; + + --signal last_data : std_logic_vector(7 downto 0) := X"55"; + + signal pio_i : pio_t; + signal port_a_c : std_logic_vector(7 downto 0) := (others => '0'); + signal port_b_c : std_logic_vector(7 downto 0) := (others => '0'); + + signal irq_mask : std_logic_vector(6 downto 0) := (others => '0'); + signal irq_flags : std_logic_vector(6 downto 0) := (others => '0'); + signal irq_events : std_logic_vector(6 downto 0) := (others => '0'); + signal irq_out : std_logic; + + signal timer_a_latch : std_logic_vector(15 downto 0) := latch_reset_pattern; + signal timer_b_latch : std_logic_vector(15 downto 0) := latch_reset_pattern; + signal timer_a_count : std_logic_vector(15 downto 0) := latch_reset_pattern; + signal timer_b_count : std_logic_vector(15 downto 0) := latch_reset_pattern; + signal timer_a_out : std_logic; + signal timer_b_tick : std_logic; + + signal acr, pcr : std_logic_vector(7 downto 0) := X"00"; + signal shift_reg : std_logic_vector(7 downto 0) := X"00"; + signal serport_en : std_logic; + signal ser_cb2_o : std_logic; + signal hs_cb2_o : std_logic; + signal cb1_t_int : std_logic; + signal cb1_o_int : std_logic; + signal cb2_t_int : std_logic; + signal cb2_o_int : std_logic; + + alias ca2_event : std_logic is irq_events(0); + alias ca1_event : std_logic is irq_events(1); + alias serial_event : std_logic is irq_events(2); + alias cb2_event : std_logic is irq_events(3); + alias cb1_event : std_logic is irq_events(4); + alias timer_b_event : std_logic is irq_events(5); + alias timer_a_event : std_logic is irq_events(6); + + alias ca2_flag : std_logic is irq_flags(0); + alias ca1_flag : std_logic is irq_flags(1); + alias serial_flag : std_logic is irq_flags(2); + alias cb2_flag : std_logic is irq_flags(3); + alias cb1_flag : std_logic is irq_flags(4); + alias timer_b_flag : std_logic is irq_flags(5); + alias timer_a_flag : std_logic is irq_flags(6); + + alias tmr_a_output_en : std_logic is acr(7); + alias tmr_a_freerun : std_logic is acr(6); + alias tmr_b_count_mode : std_logic is acr(5); + alias shift_dir : std_logic is acr(4); + alias shift_clk_sel : std_logic_vector(1 downto 0) is acr(3 downto 2); + alias shift_mode_control : std_logic_vector(2 downto 0) is acr(4 downto 2); + alias pb_latch_en : std_logic is acr(1); + alias pa_latch_en : std_logic is acr(0); + + alias cb2_is_output : std_logic is pcr(7); + alias cb2_edge_select : std_logic is pcr(6); -- for when CB2 is input + alias cb2_no_irq_clr : std_logic is pcr(5); -- for when CB2 is input + alias cb2_out_mode : std_logic_vector(1 downto 0) is pcr(6 downto 5); + alias cb1_edge_select : std_logic is pcr(4); + + alias ca2_is_output : std_logic is pcr(3); + alias ca2_edge_select : std_logic is pcr(2); -- for when CA2 is input + alias ca2_no_irq_clr : std_logic is pcr(1); -- for when CA2 is input + alias ca2_out_mode : std_logic_vector(1 downto 0) is pcr(2 downto 1); + alias ca1_edge_select : std_logic is pcr(0); + + signal ira, irb : std_logic_vector(7 downto 0) := (others => '0'); + + signal write_t1c_l : std_logic; + signal write_t1c_h : std_logic; + signal write_t2c_h : std_logic; + + signal ca1_c, ca2_c : std_logic; + signal cb1_c, cb2_c : std_logic; + signal ca1_d, ca2_d : std_logic; + signal cb1_d, cb2_d : std_logic; + + signal ca2_handshake_o : std_logic; + signal ca2_pulse_o : std_logic; + signal cb2_handshake_o : std_logic; + signal cb2_pulse_o : std_logic; + signal shift_active : std_logic; +begin + irq <= irq_out; + + write_t1c_l <= '1' when (addr = X"4" or addr = x"6") and wen='1' and falling = '1' else '0'; + write_t1c_h <= '1' when addr = X"5" and wen='1' and falling = '1' else '0'; + write_t2c_h <= '1' when addr = X"9" and wen='1' and falling = '1' else '0'; + + ca1_event <= (ca1_c xor ca1_d) and (ca1_d xor ca1_edge_select); + ca2_event <= (ca2_c xor ca2_d) and (ca2_d xor ca2_edge_select); + cb1_event <= (cb1_c xor cb1_d) and (cb1_d xor cb1_edge_select); + cb2_event <= (cb2_c xor cb2_d) and (cb2_d xor cb2_edge_select); + + ca2_t <= ca2_is_output; + cb2_t_int <= cb2_is_output when serport_en='0' else shift_dir; + cb2_o_int <= hs_cb2_o when serport_en='0' else ser_cb2_o; + + cb1_t <= cb1_t_int; + cb1_o <= cb1_o_int; + cb2_t <= cb2_t_int; + cb2_o <= cb2_o_int; + + with ca2_out_mode select ca2_o <= + ca2_handshake_o when "00", + ca2_pulse_o when "01", + '0' when "10", + '1' when others; + + with cb2_out_mode select hs_cb2_o <= + cb2_handshake_o when "00", + cb2_pulse_o when "01", + '0' when "10", + '1' when others; + + process(irq_flags, irq_mask) + begin + if (irq_flags and irq_mask) = "0000000" then + irq_out <= '0'; + else + irq_out <= '1'; + end if; + end process; + + process(clock) + begin + if rising_edge(clock) then + if rising = '1' then + phi2_ref <= '1'; + elsif falling = '1' then + phi2_ref <= '0'; + end if; + end if; + end process; + + + process(clock) + begin + if rising_edge(clock) then + -- CA1/CA2/CB1/CB2 edge detect flipflops + ca1_c <= To_X01(ca1_i); + ca2_c <= To_X01(ca2_i); + if cb1_t_int = '0' then + cb1_c <= To_X01(cb1_i); + else + cb1_c <= cb1_o_int; + end if; + if cb2_t_int = '0' then + cb2_c <= To_X01(cb2_i); + else + cb2_c <= cb2_o_int; + end if; + + ca1_d <= ca1_c; + ca2_d <= ca2_c; + cb1_d <= cb1_c; + cb2_d <= cb2_c; + + -- input registers + port_a_c <= port_a_i; + port_b_c <= port_b_i; + + -- input latch emulation + if pa_latch_en = '0' or ca1_event = '1' then + ira <= port_a_c; + end if; + + if pb_latch_en = '0' or cb1_event = '1' then + irb <= port_b_c; + end if; + + -- CA2 logic + if ca1_event = '1' then + ca2_handshake_o <= '1'; + elsif (ren = '1' or wen = '1') and addr = X"1" and falling = '1' then + ca2_handshake_o <= '0'; + end if; + + if falling = '1' then + if (ren = '1' or wen = '1') and addr = X"1" then + ca2_pulse_o <= '0'; + else + ca2_pulse_o <= '1'; + end if; + end if; + + -- CB2 logic + if cb1_event = '1' then + cb2_handshake_o <= '1'; + elsif (ren = '1' or wen = '1') and addr = X"0" and falling = '1' then + cb2_handshake_o <= '0'; + end if; + + if falling = '1' then + if (ren = '1' or wen = '1') and addr = X"0" then + cb2_pulse_o <= '0'; + else + cb2_pulse_o <= '1'; + end if; + end if; + + -- Interrupt logic + irq_flags <= irq_flags or irq_events; + + -- Writes -- + if wen='1' and falling = '1' then + --last_data <= data_in; + case addr is + when X"0" => -- ORB + pio_i.prb <= data_in; + if cb2_no_irq_clr='0' then + cb2_flag <= '0'; + end if; + cb1_flag <= '0'; + + when X"1" => -- ORA + pio_i.pra <= data_in; + if ca2_no_irq_clr='0' then + ca2_flag <= '0'; + end if; + ca1_flag <= '0'; + + when X"2" => -- DDRB + pio_i.ddrb <= data_in; + + when X"3" => -- DDRA + pio_i.ddra <= data_in; + + when X"4" => -- TA LO counter (write=latch) + timer_a_latch(7 downto 0) <= data_in; + + when X"5" => -- TA HI counter + timer_a_latch(15 downto 8) <= data_in; + timer_a_flag <= '0'; + + when X"6" => -- TA LO latch + timer_a_latch(7 downto 0) <= data_in; + + when X"7" => -- TA HI latch + timer_a_latch(15 downto 8) <= data_in; + timer_a_flag <= '0'; + + when X"8" => -- TB LO latch + timer_b_latch(7 downto 0) <= data_in; + + when X"9" => -- TB HI counter + timer_b_flag <= '0'; + + when X"A" => -- Serial port + serial_flag <= '0'; + + when X"B" => -- ACR (Auxiliary Control Register) + acr <= data_in; + + when X"C" => -- PCR (Peripheral Control Register) + pcr <= data_in; + + when X"D" => -- IFR + irq_flags <= irq_flags and not data_in(6 downto 0); + + when X"E" => -- IER + if data_in(7)='1' then -- set + irq_mask <= irq_mask or data_in(6 downto 0); + else -- clear + irq_mask <= irq_mask and not data_in(6 downto 0); + end if; + + when X"F" => -- ORA no handshake + pio_i.pra <= data_in; + + when others => + null; + end case; + end if; + + -- Reads - Output only -- + data_out <= X"00"; + case addr is + when X"0" => -- ORB + --Port B reads its own output register for pins set to output. + data_out <= (pio_i.prb and pio_i.ddrb) or (irb and not pio_i.ddrb); + if tmr_a_output_en='1' then + data_out(7) <= timer_a_out; + end if; + when X"1" => -- ORA + data_out <= ira; + when X"2" => -- DDRB + data_out <= pio_i.ddrb; + when X"3" => -- DDRA + data_out <= pio_i.ddra; + when X"4" => -- TA LO counter + data_out <= timer_a_count(7 downto 0); + when X"5" => -- TA HI counter + data_out <= timer_a_count(15 downto 8); + when X"6" => -- TA LO latch + data_out <= timer_a_latch(7 downto 0); + when X"7" => -- TA HI latch + data_out <= timer_a_latch(15 downto 8); + when X"8" => -- TA LO counter + data_out <= timer_b_count(7 downto 0); + when X"9" => -- TA HI counter + data_out <= timer_b_count(15 downto 8); + when X"A" => -- SR + data_out <= shift_reg; + when X"B" => -- ACR + data_out <= acr; + when X"C" => -- PCR + data_out <= pcr; + when X"D" => -- IFR + data_out <= irq_out & irq_flags; + when X"E" => -- IER + data_out <= '1' & irq_mask; + when X"F" => -- ORA + data_out <= ira; + when others => + null; + end case; + + -- Read actions -- + if ren = '1' and falling = '1' then + case addr is + when X"0" => -- ORB + if cb2_no_irq_clr='0' then + cb2_flag <= '0'; + end if; + cb1_flag <= '0'; + + when X"1" => -- ORA + if ca2_no_irq_clr='0' then + ca2_flag <= '0'; + end if; + ca1_flag <= '0'; + + when X"4" => -- TA LO counter + timer_a_flag <= '0'; + + when X"8" => -- TB LO counter + timer_b_flag <= '0'; + + when X"A" => -- SR + serial_flag <= '0'; + + when others => + null; + end case; + end if; + + if reset='1' then + pio_i <= pio_default; + irq_mask <= (others => '0'); + irq_flags <= (others => '0'); + acr <= (others => '0'); + pcr <= (others => '0'); + ca2_handshake_o <= '1'; + ca2_pulse_o <= '1'; + cb2_handshake_o <= '1'; + cb2_pulse_o <= '1'; + timer_a_latch <= latch_reset_pattern; + timer_b_latch <= latch_reset_pattern; + end if; + end if; + end process; + + -- PIO Out select -- + port_a_o <= pio_i.pra; + port_b_o(6 downto 0) <= pio_i.prb(6 downto 0); + port_b_o(7) <= pio_i.prb(7) when tmr_a_output_en='0' else timer_a_out; + + port_a_t <= pio_i.ddra; + port_b_t(6 downto 0) <= pio_i.ddrb(6 downto 0); + port_b_t(7) <= pio_i.ddrb(7) or tmr_a_output_en; + + + -- Timer A + tmr_a: block + signal timer_a_reload : std_logic; + signal timer_a_toggle : std_logic; + signal timer_a_may_interrupt : std_logic; + begin + process(clock) + begin + if rising_edge(clock) then + if falling = '1' then + -- always count, or load + + if timer_a_reload = '1' then + timer_a_count <= timer_a_latch; + if write_t1c_l = '1' then + timer_a_count(7 downto 0) <= data_in; + end if; + timer_a_reload <= '0'; + timer_a_may_interrupt <= timer_a_may_interrupt and tmr_a_freerun; + else + if timer_a_count = X"0000" then + -- generate an event if we were triggered + timer_a_reload <= '1'; + end if; + --Timer coutinues to count in both free run and one shot. + timer_a_count <= timer_a_count - X"0001"; + end if; + end if; + + if rising = '1' then + if timer_a_event = '1' and tmr_a_output_en = '1' then + timer_a_toggle <= not timer_a_toggle; + end if; + end if; + + if write_t1c_h = '1' then + timer_a_may_interrupt <= '1'; + timer_a_toggle <= not tmr_a_output_en; + timer_a_count <= data_in & timer_a_latch(7 downto 0); + timer_a_reload <= '0'; + end if; + + if reset='1' then + timer_a_may_interrupt <= '0'; + timer_a_toggle <= '1'; + timer_a_count <= latch_reset_pattern; + timer_a_reload <= '0'; + end if; + end if; + end process; + + timer_a_out <= timer_a_toggle; + timer_a_event <= rising and timer_a_reload and timer_a_may_interrupt; + + end block tmr_a; + + -- Timer B + tmr_b: block + signal timer_b_reload_lo : std_logic; + signal timer_b_oneshot_trig : std_logic; + signal timer_b_timeout : std_logic; + signal pb6_c, pb6_d : std_logic; + begin + process(clock) + variable timer_b_decrement : std_logic; + begin + if rising_edge(clock) then + timer_b_decrement := '0'; + + if rising = '1' then + pb6_c <= To_X01(port_b_i(6)); + pb6_d <= pb6_c; + end if; + + if falling = '1' then + timer_b_timeout <= '0'; + timer_b_tick <= '0'; + + if tmr_b_count_mode = '1' then + if (pb6_d='1' and pb6_c='0') then + timer_b_decrement := '1'; + end if; + else -- one shot or used for shift register + timer_b_decrement := '1'; + end if; + + if timer_b_decrement = '1' then + if timer_b_count = X"0000" then + if timer_b_oneshot_trig = '1' then + timer_b_oneshot_trig <= '0'; + timer_b_timeout <= '1'; + end if; + end if; + if timer_b_count(7 downto 0) = X"00" then + case shift_mode_control is + when "001" | "101" | "100" => + timer_b_reload_lo <= '1'; + timer_b_tick <= '1'; + when others => + null; + end case; + end if; + timer_b_count <= timer_b_count - X"0001"; + end if; + if timer_b_reload_lo = '1' then + timer_b_count(7 downto 0) <= timer_b_latch(7 downto 0); + timer_b_reload_lo <= '0'; + end if; + end if; + + if write_t2c_h = '1' then + timer_b_count <= data_in & timer_b_latch(7 downto 0); + timer_b_oneshot_trig <= '1'; + end if; + + if reset='1' then + timer_b_count <= latch_reset_pattern; + timer_b_reload_lo <= '0'; + timer_b_oneshot_trig <= '0'; + end if; + end if; + end process; + + timer_b_event <= rising and timer_b_timeout; + + end block tmr_b; + + ser: block + signal trigger_serial: std_logic; + signal shift_clock_d : std_logic; + signal shift_clock : std_logic; + signal shift_tick_r : std_logic; + signal shift_tick_f : std_logic; + signal shift_timer_tick : std_logic; + signal cb2_c : std_logic := '0'; + signal bit_cnt : integer range 0 to 7; + signal shift_pulse : std_logic; + begin + process(shift_active, timer_b_tick, shift_clk_sel, shift_clock, shift_clock_d, shift_timer_tick) + begin + case shift_clk_sel is + when "10" => + shift_pulse <= '1'; + + when "00"|"01" => + shift_pulse <= shift_timer_tick; + + when others => + shift_pulse <= shift_clock and not shift_clock_d; + + end case; + + if shift_active = '0' then + -- Mode 0 still loads the shift register to external pulse (MMBEEB SD-Card interface uses this) + if shift_mode_control = "000" then + shift_pulse <= shift_clock and not shift_clock_d; + else + shift_pulse <= '0'; + end if; + end if; + + end process; + + + process(clock) + begin + if rising_edge(clock) then + + cb2_c <= To_X01(cb2_i); + + if rising = '1' then + + if shift_active='0' then + if shift_mode_control = "000" then + shift_clock <= To_X01(cb1_i); + else + shift_clock <= '1'; + end if; + elsif shift_clk_sel = "11" then + shift_clock <= To_X01(cb1_i); + elsif shift_pulse = '1' then + shift_clock <= not shift_clock; + end if; + + shift_clock_d <= shift_clock; + + end if; + + if falling = '1' then + shift_timer_tick <= timer_b_tick; + end if; + + if reset = '1' then + shift_clock <= '1'; + shift_clock_d <= '1'; + end if; + end if; + end process; + + cb1_t_int <= '0' when shift_clk_sel="11" else serport_en; + cb1_o_int <= shift_clock_d; + ser_cb2_o <= shift_reg(7); + + serport_en <= shift_dir or shift_clk_sel(1) or shift_clk_sel(0); + trigger_serial <= '1' when (ren='1' or wen='1') and addr=x"A" else '0'; + shift_tick_r <= not shift_clock_d and shift_clock; + shift_tick_f <= shift_clock_d and not shift_clock; + + process(clock) + begin + if rising_edge(clock) then + if reset = '1' then + shift_reg <= X"FF"; + elsif falling = '1' then + if wen = '1' and addr = X"A" then + shift_reg <= data_in; + elsif shift_dir='1' and shift_tick_f = '1' then -- output + shift_reg <= shift_reg(6 downto 0) & shift_reg(7); + elsif shift_dir='0' and shift_tick_r = '1' then -- input + shift_reg <= shift_reg(6 downto 0) & cb2_c; + end if; + end if; + end if; + end process; + + -- tell people that we're ready! + serial_event <= shift_tick_r and not shift_active and rising and serport_en; + + process(clock) + begin + if rising_edge(clock) then + if falling = '1' then + if shift_active = '0' and shift_mode_control /= "000" then + if trigger_serial = '1' then + bit_cnt <= 7; + shift_active <= '1'; + end if; + else -- we're active + if shift_clk_sel = "00" then + shift_active <= shift_dir; -- when '1' we're active, but for mode 000 we go inactive. + elsif shift_pulse = '1' and shift_clock = '1' then + if bit_cnt = 0 then + shift_active <= '0'; + else + bit_cnt <= bit_cnt - 1; + end if; + end if; + end if; + end if; + + if reset='1' then + shift_active <= '0'; + bit_cnt <= 0; + end if; + end if; + end process; + end block ser; +end Gideon; + diff --git a/rtl/video.v b/rtl/video.v deleted file mode 100644 index 4a493ca..0000000 --- a/rtl/video.v +++ /dev/null @@ -1,166 +0,0 @@ - -module video -( - input clk, - input ce, - - input [14:0] addr, - input [15:0] dataIn, - input [1:0] wr, - - output reg hsync, - output reg vsync, - output _hblank, - output _vblank, - - output video_en, - output pixelOut -); - -localparam kVisibleWidth = 128, - kTotalWidth = 176, - kVisibleHeightStart = 21, - kVisibleHeightEnd = 362, - kTotalHeight = 370, - kHsyncStart = 135, - kHsyncEnd = 152, - kVsyncStart = 365, - kVsyncEnd = 369, - kPixelLatency = 1; // number of clk8 cycles from xpos==0 to when pixel data actually exits the video shift register - -localparam videoStart = 'hA700 - (kVisibleHeightStart * kVisibleWidth/2); - -reg [7:0] xpos; -reg [9:0] ypos; - -assign _hblank = ~(xpos >= kVisibleWidth); -assign _vblank = ~(ypos < kVisibleHeightStart || ypos > kVisibleHeightEnd); - -wire [15:0] scrData; -vram buff -( - .clock(clk), - - .data(dataIn), - .wraddress(addr[13:0]), - .byteena_a(wr), - .wren(ram_wr), - - .rdaddress(videoStart[14:1] + {ypos[8:0], xpos[6:2]}), - .q(scrData) -); - -reg ram_wr; -always @(posedge clk) begin - reg old_wr; - - old_wr <= |wr; - ram_wr <= (~old_wr & |wr); -end - -reg [3:0] cycle; -always @(posedge clk) if(ce) cycle <= cycle + 1'd1; - -always @(posedge clk) begin - if(ce && !cycle[1:0]) begin - if (xpos == kTotalWidth-1) begin - xpos <= 0; - if (ypos == kTotalHeight-1) ypos <= 0; - else ypos <= ypos + 1'b1; - end else if (!xpos && cycle) begin - xpos <= 0; - end else begin - xpos <= xpos + 1'b1; - end - - if(xpos == kHsyncStart+kPixelLatency) begin - hsync <= 1; - vsync <= (ypos >= kVsyncStart && ypos <= kVsyncEnd); - end - if(xpos == kHsyncEnd+kPixelLatency) hsync <= 0; - end -end - -// a 0 bit is white, and a 1 bit is black -// data is shifted out MSB first -assign pixelOut = ~shiftRegister[15]; -assign video_en = paper[15]; - -reg [15:0] shiftRegister; -reg [15:0] paper; -always @(posedge clk) begin - if(ce) begin - if(_vblank && _hblank && cycle == 2) begin - shiftRegister <= scrData; - paper <= 16'hFFFF; - end - else begin - shiftRegister <= { shiftRegister[14:0], 1'b1 }; - paper <= { paper[14:0], 1'b0 }; - end - end -end - -endmodule - -module vram -( - input clock, - - input [15:0] data, - input [13:0] wraddress, - input [1:0] byteena_a, - input wren, - - input [13:0] rdaddress, - output [15:0] q -); - -altsyncram altsyncram_component ( - .address_a (wraddress), - .address_b (rdaddress), - .byteena_a (byteena_a), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .q_b (q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({16{1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); -defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.byte_size = 8, - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone V", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 16384, - altsyncram_component.numwords_b = 16384, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = 14, - altsyncram_component.widthad_b = 14, - altsyncram_component.width_a = 16, - altsyncram_component.width_b = 16, - altsyncram_component.width_byteena_a = 2; - - -endmodule diff --git a/rtl/videoShifter.v b/rtl/videoShifter.v new file mode 100644 index 0000000..0d5fe43 --- /dev/null +++ b/rtl/videoShifter.v @@ -0,0 +1,26 @@ +module videoShifter( + input clk32, + input memoryLatch, + input [15:0] dataIn, + input loadPixels, + output pixelOut + ); + + reg [15:0] shiftRegister; + + // a 0 bit is white, and a 1 bit is black + // data is shifted out MSB first + assign pixelOut = ~shiftRegister[15]; + + always @(posedge clk32) begin + // loadPixels is generated by a module running on the 8 MHz CPU clock. Therefore this module + // only honors loadPixels when clkPhase is 1, indicating the last quarter of the 8 MHz clock cycle. + if (loadPixels && memoryLatch) begin + shiftRegister <= dataIn; + end + else begin + shiftRegister <= { shiftRegister[14:0], 1'b1 }; + end + end + +endmodule diff --git a/rtl/videoTimer.v b/rtl/videoTimer.v new file mode 100644 index 0000000..9cf1c6e --- /dev/null +++ b/rtl/videoTimer.v @@ -0,0 +1,81 @@ +// generates 1024x768 (actually 512x768) @ 60Hz, from a 32.5MHz input clock +module videoTimer( + input clk, + input clk_en, + input [1:0] busCycle, + input vid_alt, + output [21:0] videoAddr, + output reg hsync, + output reg vsync, + output _hblank, + output _vblank, + output loadPixels +); + + // timing data from http://tinyvga.com/vga-timing/1024x768@60Hz + localparam kVisibleWidth = 128, // (1024/2)/4 + kTotalWidth = 168, // (1344/2)/4 + kVisibleHeightStart = 42, + kVisibleHeightEnd = 725, + kTotalHeight = 806, + kHsyncStart = 131, // (1048/2)/4 + kHsyncEnd = 147, // (1184/2)/4-1 + kVsyncStart = 771, + kVsyncEnd = 776, + kPixelLatency = 1; // number of clk8 cycles from xpos==0 to when pixel data actually exits the video shift register + + // use screen buffer address for a 4MB RAM layout-- it will wrap + // around to the proper address for 1MB, 512K, and 128K layouts + localparam kScreenBufferBase = 22'h3FA700; + localparam startAddr = kVisibleHeightStart/2 * kVisibleWidth/2; + + reg [7:0] xpos; + reg [9:0] ypos; + + wire endline = (xpos == kTotalWidth-1); + + always @(posedge clk) begin + if (clk_en) begin + if (endline) + xpos <= 0; + else if (xpos == 0 && busCycle != 0) + // hold xpos at 0, until xpos and busCycle are in phase + xpos <= 0; + else + xpos <= xpos + 1'b1; + end + end + + always @(posedge clk) begin + if (clk_en) begin + if (endline) begin + if (ypos == kTotalHeight-1) + ypos <= 0; + else + ypos <= ypos + 1'b1; + end + end + end + + always @(posedge clk) begin + if (clk_en) begin + hsync <= ~(xpos >= kHsyncStart+kPixelLatency && xpos <= kHsyncEnd+kPixelLatency); + vsync <= ~(ypos >= kVsyncStart && ypos <= kVsyncEnd); + end + end + + assign _hblank = ~(xpos >= kVisibleWidth+kPixelLatency); + assign _vblank = ~(ypos < kVisibleHeightStart || ypos > kVisibleHeightEnd); + + // The 0,0 address actually starts below kScreenBufferBase, because the Mac screen buffer is + // not displayed beginning at 0,0, but at 0,kVisibleHeightStart. + // kVisibleHeightStart divided by 2 to account for vertical pixel doubling. + // kVisibleWidth divided by 2 because it's the 8MHz visible width times 4 to get actual number of pixels, + // then divided by 8 bits per byte + assign videoAddr = kScreenBufferBase - (vid_alt ? 16'h0 : 16'h8000) - + startAddr[21:0] + + { ypos[9:1], xpos[6:2], 1'b0 }; + + assign loadPixels = _vblank == 1'b1 && _hblank == 1'b1 && busCycle == 2'b00; + +endmodule