Support for SDRAM v2.
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29
sdram.sv
29
sdram.sv
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@ -30,9 +30,9 @@ module sdram
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(
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// interface to the MT48LC16M16 chip
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inout [15:0] sd_data, // 16 bit bidirectional data bus
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inout reg [15:0] sd_data, // 16 bit bidirectional data bus
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output reg [12:0] sd_addr, // 13 bit multiplexed address bus
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output reg [1:0] sd_dqm, // two byte masks
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output [1:0] sd_dqm, // two byte masks
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output reg [1:0] sd_ba, // two banks
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output sd_cs, // a single chip select
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output sd_we, // write enable
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@ -73,7 +73,6 @@ localparam STATE_FIRST = 3'd0; // first state in cycle
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localparam STATE_CMD_START = 3'd1; // state in which a new command can be started
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localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY; // command can be continued
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localparam STATE_READ = STATE_CMD_CONT + CAS_LATENCY + 4'd1;
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localparam STATE_HIGHZ = STATE_READ - 4'd1; // disable output to prevent contention
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// ---------------------------------------------------------------------
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@ -111,9 +110,7 @@ assign sd_cs = sd_cmd[3];
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assign sd_ras = sd_cmd[2];
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assign sd_cas = sd_cmd[1];
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assign sd_we = sd_cmd[0];
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// drive ram data lines when writing, set them as inputs otherwise
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assign sd_data = mode[1] ? din_r : 16'bZZZZZZZZZZZZZZZZ;
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assign sd_dqm = sd_addr[12:11];
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reg [1:0] mode;
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reg [15:0] din_r;
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@ -121,9 +118,10 @@ reg [2:0] stage;
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always @(posedge clk) begin
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reg [12:0] addr_r;
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reg [1:0] ds_r;
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reg old_sync;
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sd_data <= 16'hZZZZ;
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if(|stage) stage <= stage + 1'd1;
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old_sync <= sync;
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@ -147,7 +145,6 @@ always @(posedge clk) begin
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end
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mode <= 0;
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sd_dqm <= 2'b11;
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end else begin
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// normal operation
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@ -161,9 +158,8 @@ always @(posedge clk) begin
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sd_addr <= { 1'b0, addr[19:8] };
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sd_ba <= addr[21:20];
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ds_r <= ds;
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din_r <= din;
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addr_r <= { 4'b0010, addr[22], addr[7:0] }; // auto precharge
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addr_r <= {we ? ~ds : 2'b00, 2'b10, addr[22], addr[7:0] }; // auto precharge
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end
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else begin
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sd_cmd <= CMD_AUTO_REFRESH;
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@ -175,19 +171,10 @@ always @(posedge clk) begin
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if(stage == STATE_CMD_CONT && mode) begin
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sd_cmd <= mode[1] ? CMD_WRITE : CMD_READ;
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sd_addr <= addr_r;
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if(mode[1]) sd_dqm <= ~ds_r;
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else sd_dqm <= 2'b00;
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if(mode[1]) sd_data <= din_r;
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end
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if(stage == STATE_HIGHZ) begin
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sd_dqm <= 2'b11; // disable chip output
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mode[1] <= 0; // disable data output
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end
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if(stage == STATE_READ && mode) begin
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dout <= sd_data;
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end
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if(stage == STATE_READ && mode[0]) dout <= sd_data;
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end
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end
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