mirror of
https://github.com/MiSTer-devel/MacPlus_MiSTer.git
synced 2024-09-29 19:55:25 +00:00
682 lines
15 KiB
Verilog
682 lines
15 KiB
Verilog
//============================================================================
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//
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// DE10-nano HAL top module
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// (c)2017 Sorgelig
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//
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//============================================================================
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module sys_top
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(
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/////////// CLOCK //////////
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input FPGA_CLK1_50,
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input FPGA_CLK2_50,
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input FPGA_CLK3_50,
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//////////// VGA ///////////
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output [5:0] VGA_R,
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output [5:0] VGA_G,
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output [5:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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input VGA_EN,
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/////////// AUDIO //////////
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output AUDIO_L,
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output AUDIO_R,
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output AUDIO_SPDIF,
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//////////// HDMI //////////
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output HDMI_I2C_SCL,
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inout HDMI_I2C_SDA,
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output HDMI_MCLK,
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output HDMI_SCLK,
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output HDMI_LRCLK,
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output HDMI_I2S,
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output HDMI_TX_CLK,
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output HDMI_TX_DE,
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output [23:0] HDMI_TX_D,
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output HDMI_TX_HS,
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output HDMI_TX_VS,
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//////////// SDR ///////////
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output [12:0] SDRAM_A,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nWE,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nCS,
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output [1:0] SDRAM_BA,
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output SDRAM_CLK,
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output SDRAM_CKE,
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//////////// I/O ///////////
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output LED_USER,
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output LED_HDD,
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output LED_POWER,
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input BTN_USER,
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input BTN_OSD,
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input BTN_RESET,
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//////////// SDIO ///////////
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inout [3:0] SDIO_DAT,
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inout SDIO_CMD,
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output SDIO_CLK,
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input SDIO_CD,
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////////// MB KEY ///////////
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input [1:0] KEY,
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////////// MB LED ///////////
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output [7:0] LED
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);
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assign SDIO_DAT[2:1] = 2'bZZ;
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////////////////////////// LEDs ///////////////////////////////////////
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wire led_p = led_power[1] ? ~led_power[0] : 1'b0;
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wire led_d = led_disk[1] ? ~led_disk[0] : ~(led_disk[0] | gp_out[29]);
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wire led_u = ~led_user;
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assign LED_POWER = led_p ? 1'bZ : 1'b0;
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assign LED_HDD = led_d ? 1'bZ : 1'b0;
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assign LED_USER = led_u ? 1'bZ : 1'b0;
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//LEDs on main board
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assign LED = {3'b000, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u};
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////////////////////////// Buttons ///////////////////////////////////
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reg btn_user, btn_osd;
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always @(posedge FPGA_CLK2_50) begin
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integer div;
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reg [7:0] deb_user;
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reg [7:0] deb_osd;
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div <= div + 1'b1;
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if(div > 100000) div <= 0;
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if(!div) begin
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deb_user <= {deb_user[6:0], ~(BTN_USER & KEY[1])};
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if(&deb_user) btn_user <= 1;
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if(!deb_user) btn_user <= 0;
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deb_osd <= {deb_osd[6:0], ~(BTN_OSD & KEY[0])};
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if(&deb_osd) btn_osd <= 1;
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if(!deb_osd) btn_osd <= 0;
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end
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end
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reg btn_reset = 1;
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always @(posedge FPGA_CLK2_50) btn_reset <= BTN_RESET;
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///////////////////////// HPS I/O /////////////////////////////////////
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// gp_in[31] = 0 - quick flag that FPGA is initialized (HPS reads 1 when FPGA is not in user mode)
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// used to avoid lockups while JTAG loading
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wire [31:0] gp_in = {1'b0, btn_user, btn_osd, 9'd0, io_ver, io_ack, io_wide, io_dout};
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wire [31:0] gp_out;
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wire [1:0] io_ver = 1; // 0 - standard MiST I/O (for quick porting of complex MiST cores). 1 - optimized HPS I/O. 2,3 - reserved for future.
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wire io_wait;
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wire io_wide;
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wire [15:0] io_dout;
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wire [15:0] io_din = gp_outr[15:0];
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wire io_clk = gp_outr[17];
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wire io_fpga = gp_outr[18];
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wire io_osd = gp_outr[19];
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wire io_uio = gp_outr[20];
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//wire io_sdd = gp_outr[21]; // used only in ST core
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reg io_ack;
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reg rack;
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wire io_strobe = ~rack & io_clk;
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always @(posedge clk_sys) begin
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if(~io_wait | io_strobe) begin
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rack <= io_clk;
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io_ack <= rack;
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end
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end
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reg [31:0] gp_outr;
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always @(posedge clk_sys) begin
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reg [31:0] gp_outd;
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gp_outr <= gp_outd;
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gp_outd <= gp_out;
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end
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wire [7:0] core_type = 'hA4; // A4 - generic core.
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// HPS will not communicate to core if magic is different
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wire [31:0] core_magic = {24'h5CA623, core_type};
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cyclonev_hps_interface_mpu_general_purpose h2f_gp
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(
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.gp_in({~gp_out[31] ? core_magic : gp_in}),
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.gp_out(gp_out)
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);
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reg [15:0] cfg;
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reg cfg_ready = 0;
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wire audio_96k = cfg[6];
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wire ypbpr_en = cfg[5];
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wire csync = cfg[3];
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`ifndef LITE
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wire vga_scaler= cfg[2];
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`endif
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always@(posedge clk_sys) begin
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reg [7:0] cmd;
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reg has_cmd;
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reg old_strobe;
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old_strobe <= io_strobe;
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if(~io_uio) has_cmd <= 0;
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else
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if(~old_strobe & io_strobe) begin
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if(!has_cmd) begin
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has_cmd <= 1;
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cmd <= io_din[7:0];
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end
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else
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if(cmd == 1) begin
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cfg <= io_din;
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cfg_ready <= 1;
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end
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end
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end
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/////////////////////////// RESET ///////////////////////////////////
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reg reset_req = 0;
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always @(posedge FPGA_CLK2_50) begin
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reg [1:0] resetd, resetd2;
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reg old_reset;
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//latch the reset
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old_reset <= reset;
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if(~old_reset & reset) reset_req <= 1;
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//special combination to set/clear the reset
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//preventing of accidental reset control
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if(resetd==1) reset_req <= 1;
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if(resetd==2 && resetd2==0) reset_req <= 0;
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resetd <= gp_out[31:30];
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resetd2 <= resetd;
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end
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// 100MHz
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wire ctl_clk;
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///////////////////////// VIP version ///////////////////////////////
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`ifndef LITE
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wire reset;
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vip vip
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(
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//Reset/Clock
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.reset_reset_req(reset_req),
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.reset_reset(reset),
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//DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button.
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.reset_cold_req(~btn_reset),
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.reset_warm_req(0),
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//control
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.ctl_address(ctl_address),
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.ctl_write(ctl_write),
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.ctl_writedata(ctl_writedata),
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.ctl_waitrequest(ctl_waitrequest),
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.ctl_clock(ctl_clk),
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.ctl_reset(ctl_reset),
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//64-bit DDR3 RAM access
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.ramclk1_clk(ram_clk),
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.ram1_address(ram_address),
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.ram1_burstcount(ram_burstcount),
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.ram1_waitrequest(ram_waitrequest),
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.ram1_readdata(ram_readdata),
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.ram1_readdatavalid(ram_readdatavalid),
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.ram1_read(ram_read),
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.ram1_writedata(ram_writedata),
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.ram1_byteenable(ram_byteenable),
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.ram1_write(ram_write),
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//Spare 64-bit DDR3 RAM access
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//currently unused
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//can combine with ram1 to make a wider RAM bus (although will increase the latency)
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.ramclk2_clk(0),
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.ram2_address(0),
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.ram2_burstcount(0),
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.ram2_waitrequest(),
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.ram2_readdata(),
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.ram2_readdatavalid(),
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.ram2_read(0),
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.ram2_writedata(0),
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.ram2_byteenable(0),
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.ram2_write(0),
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//Video input
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.in_vid_clk(clk_vid),
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.in_vid_data({r_out, g_out, b_out}),
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.in_vid_de(de),
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.in_vid_v_sync(vs),
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.in_vid_h_sync(hs),
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.in_vid_datavalid(ce_pix),
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.in_vid_locked(1),
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.in_vid_f(0),
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.in_vid_color_encoding(0),
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.in_vid_bit_width(0),
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//HDMI output
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.hdmi_vid_clk(~HDMI_TX_CLK),
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.hdmi_vid_data(hdmi_data),
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.hdmi_vid_datavalid(HDMI_TX_DE),
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.hdmi_vid_v_sync(HDMI_TX_VS),
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.hdmi_vid_h_sync(HDMI_TX_HS)
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);
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wire [8:0] ctl_address;
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wire ctl_write;
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wire [31:0] ctl_writedata;
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wire ctl_waitrequest;
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wire ctl_reset;
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wire [7:0] ARX, ARY;
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vip_config vip_config
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(
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.clk(ctl_clk),
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.reset(ctl_reset),
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.ARX(ARX),
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.ARY(ARY),
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.address(ctl_address),
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.write(ctl_write),
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.writedata(ctl_writedata),
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.waitrequest(ctl_waitrequest)
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);
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`endif
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///////////////////////// Lite version ////////////////////////////////
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`ifdef LITE
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wire INTERLACED = 0;
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wire [11:0] V_TOTAL_0 = 750;
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wire [11:0] V_FP_0 = 5;
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wire [11:0] V_BP_0 = 20;
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wire [11:0] V_SYNC_0 = 5;
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wire [11:0] V_TOTAL_1 = 0;
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wire [11:0] V_FP_1 = 0;
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wire [11:0] V_BP_1 = 0;
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wire [11:0] V_SYNC_1 = 0;
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wire [11:0] H_TOTAL = 1650;
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wire [11:0] H_FP = 110;
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wire [11:0] H_BP = 220;
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wire [11:0] H_SYNC = 40;
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wire [11:0] HV_OFFSET_0 = 0;
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wire [11:0] HV_OFFSET_1 = 0;
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wire [11:0] x;
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wire [12:0] y;
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sync_vg #(.X_BITS(12), .Y_BITS(12)) sync_vg
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(
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.clk(HDMI_TX_CLK),
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.reset(reset),
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.interlaced(INTERLACED),
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.clk_out(), // inverted output clock - unconnected
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.v_total_0(V_TOTAL_0),
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.v_fp_0(V_FP_0),
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.v_bp_0(V_BP_0),
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.v_sync_0(V_SYNC_0),
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.v_total_1(V_TOTAL_1),
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.v_fp_1(V_FP_1),
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.v_bp_1(V_BP_1),
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.v_sync_1(V_SYNC_1),
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.h_total(H_TOTAL),
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.h_fp(H_FP),
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.h_bp(H_BP),
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.h_sync(H_SYNC),
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.hv_offset_0(HV_OFFSET_0),
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.hv_offset_1(HV_OFFSET_1),
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.vde_out(vde),
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.hde_out(hde),
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.vs_out(vs_hdmi),
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.v_count_out(),
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.h_count_out(),
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.x_out(x),
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.y_out(y),
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.hs_out(hs_hdmi),
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.field_out(field)
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);
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wire vde, hde;
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wire vs_hdmi;
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wire hs_hdmi;
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wire field;
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pattern_vg
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#(
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.B(8), // Bits per channel
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.X_BITS(12),
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.Y_BITS(12),
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.FRACTIONAL_BITS(12) // Number of fractional bits for ramp pattern
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)
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pattern_vg
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(
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.reset(reset),
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.clk_in(HDMI_TX_CLK),
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.x(x),
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.y(y[11:0]),
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.vn_in(vs_hdmi),
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.hn_in(hs_hdmi),
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.dn_in(vde & hde),
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.r_in(0),
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.g_in(0),
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.b_in(0),
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.vn_out(HDMI_TX_VS),
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.hn_out(HDMI_TX_HS),
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.den_out(HDMI_TX_DE),
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.r_out(hdmi_data[23:16]),
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.g_out(hdmi_data[15:8]),
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.b_out(hdmi_data[7:0]),
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.total_active_pix(H_TOTAL - (H_FP + H_BP + H_SYNC)),
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.total_active_lines(INTERLACED ? (V_TOTAL_0 - (V_FP_0 + V_BP_0 + V_SYNC_0)) + (V_TOTAL_1 - (V_FP_1 + V_BP_1 + V_SYNC_1)) : (V_TOTAL_0 - (V_FP_0 + V_BP_0 + V_SYNC_0))), // originally: 13'd480
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.pattern(4),
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.ramp_step(20'h0333)
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);
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wire reset;
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sysmem_lite sysmem
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(
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//Reset/Clock
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.reset_reset_req(reset_req),
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.reset_reset(reset),
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.ctl_clock(ctl_clk),
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//DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button.
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.reset_cold_req(~btn_reset),
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.reset_warm_req(0),
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//64-bit DDR3 RAM access
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.ramclk1_clk(ram_clk),
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.ram1_address(ram_address),
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.ram1_burstcount(ram_burstcount),
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.ram1_waitrequest(ram_waitrequest),
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.ram1_readdata(ram_readdata),
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.ram1_readdatavalid(ram_readdatavalid),
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.ram1_read(ram_read),
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.ram1_writedata(ram_writedata),
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.ram1_byteenable(ram_byteenable),
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.ram1_write(ram_write),
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//Spare 64-bit DDR3 RAM access
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//currently unused
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//can combine with ram1 to make a wider RAM bus (although will increase the latency)
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.ramclk2_clk(0),
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.ram2_address(0),
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.ram2_burstcount(0),
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.ram2_waitrequest(),
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.ram2_readdata(),
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.ram2_readdatavalid(),
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.ram2_read(0),
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.ram2_writedata(0),
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.ram2_byteenable(0),
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.ram2_write(0)
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);
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`endif
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///////////////////////// HDMI output /////////////////////////////////
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pll_hdmi pll_hdmi
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(
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.refclk(FPGA_CLK1_50),
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.rst(reset),
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.outclk_0(HDMI_TX_CLK)
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);
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hdmi_config hdmi_config
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(
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.iCLK(FPGA_CLK1_50),
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.iRST_N(cfg_ready),
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.I2C_SCL(HDMI_I2C_SCL),
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.I2C_SDA(HDMI_I2C_SDA),
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.audio_48k(~audio_96k),
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.iRES(4), // 720p
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.iAR(1) // Aspect Ratio
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);
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wire [23:0] hdmi_data;
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osd hdmi_osd
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(
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.clk_sys(clk_sys),
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.io_osd(io_osd),
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.io_strobe(io_strobe),
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.io_din(io_din[7:0]),
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.clk_video(HDMI_TX_CLK),
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.din(hdmi_data),
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.dout(HDMI_TX_D),
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.de(HDMI_TX_DE)
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);
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assign HDMI_MCLK = 0;
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i2s i2s
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(
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.reset(~cfg_ready),
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.clk_sys(FPGA_CLK1_50),
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.half_rate(~audio_96k),
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.sclk(HDMI_SCLK),
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.lrclk(HDMI_LRCLK),
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.sdata(HDMI_I2S),
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//Could inverse the MSB but it will shift 0 level to -MAX level
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.left_chan (audio_l >> !audio_s),
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.right_chan(audio_r >> !audio_s)
|
|
);
|
|
|
|
|
|
///////////////////////// VGA output //////////////////////////////////
|
|
|
|
wire [23:0] vga_q;
|
|
osd vga_osd
|
|
(
|
|
.clk_sys(clk_sys),
|
|
|
|
.io_osd(io_osd),
|
|
.io_strobe(io_strobe),
|
|
.io_din(io_din[7:0]),
|
|
|
|
.clk_video(clk_vid),
|
|
.din(de ? {r_out, g_out, b_out} : 24'd0),
|
|
.dout(vga_q),
|
|
.de(de)
|
|
);
|
|
|
|
wire [23:0] vga_o;
|
|
|
|
vga_out vga_out
|
|
(
|
|
.ypbpr_full(1),
|
|
.ypbpr_en(ypbpr_en),
|
|
.dout(vga_o),
|
|
`ifdef LITE
|
|
.din(vga_q)
|
|
`else
|
|
.din(vga_scaler ? HDMI_TX_D : vga_q)
|
|
`endif
|
|
);
|
|
|
|
`ifdef LITE
|
|
wire vs1 = vs;
|
|
wire hs1 = hs;
|
|
`else
|
|
wire vs1 = vga_scaler ? HDMI_TX_VS : vs;
|
|
wire hs1 = vga_scaler ? HDMI_TX_HS : hs;
|
|
`endif
|
|
|
|
assign VGA_VS = VGA_EN ? 1'bZ : csync ? 1'b1 : ~vs1;
|
|
assign VGA_HS = VGA_EN ? 1'bZ : csync ? ~(vs1 ^ hs1) : ~hs1;
|
|
assign VGA_R = VGA_EN ? 6'bZZZZZZ : vga_o[23:18];
|
|
assign VGA_G = VGA_EN ? 6'bZZZZZZ : vga_o[15:10];
|
|
assign VGA_B = VGA_EN ? 6'bZZZZZZ : vga_o[7:2];
|
|
|
|
|
|
///////////////////////// Audio output ////////////////////////////////
|
|
|
|
sigma_delta_dac #(15) dac_l
|
|
(
|
|
.CLK(FPGA_CLK3_50),
|
|
.RESET(reset),
|
|
.DACin({audio_l[15] ^ audio_s, audio_l[14:0]}),
|
|
.DACout(AUDIO_L)
|
|
);
|
|
|
|
sigma_delta_dac #(15) dac_r
|
|
(
|
|
.CLK(FPGA_CLK3_50),
|
|
.RESET(reset),
|
|
.DACin({audio_r[15] ^ audio_s, audio_r[14:0]}),
|
|
.DACout(AUDIO_R)
|
|
);
|
|
|
|
spdif toslink
|
|
(
|
|
.clk_i(FPGA_CLK3_50),
|
|
|
|
.rst_i(reset),
|
|
.half_rate(0),
|
|
|
|
.audio_l(audio_l >> !audio_s),
|
|
.audio_r(audio_r >> !audio_s),
|
|
|
|
.spdif_o(AUDIO_SPDIF)
|
|
);
|
|
|
|
|
|
/////////////////// User module connection ////////////////////////////
|
|
|
|
wire [15:0] audio_l, audio_r;
|
|
wire audio_s;
|
|
wire [7:0] r_out, g_out, b_out;
|
|
wire vs, hs, de;
|
|
wire clk_sys, clk_vid, ce_pix;
|
|
|
|
wire ram_clk;
|
|
wire [28:0] ram_address;
|
|
wire [7:0] ram_burstcount;
|
|
wire ram_waitrequest;
|
|
wire [63:0] ram_readdata;
|
|
wire ram_readdatavalid;
|
|
wire ram_read;
|
|
wire [63:0] ram_writedata;
|
|
wire [7:0] ram_byteenable;
|
|
wire ram_write;
|
|
|
|
wire led_user;
|
|
wire [1:0] led_power;
|
|
wire [1:0] led_disk;
|
|
|
|
emu emu
|
|
(
|
|
.CLK_50M(FPGA_CLK3_50),
|
|
.RESET(reset),
|
|
.HPS_BUS({ctl_clk, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
|
|
|
|
.CLK_VIDEO(clk_vid),
|
|
.CE_PIXEL(ce_pix),
|
|
|
|
.VGA_R(r_out),
|
|
.VGA_G(g_out),
|
|
.VGA_B(b_out),
|
|
.VGA_HS(hs),
|
|
.VGA_VS(vs),
|
|
.VGA_DE(de),
|
|
|
|
.LED_USER(led_user),
|
|
.LED_POWER(led_power),
|
|
.LED_DISK(led_disk),
|
|
|
|
`ifndef LITE
|
|
.VIDEO_ARX(ARX),
|
|
.VIDEO_ARY(ARY),
|
|
`endif
|
|
|
|
.AUDIO_L(audio_l),
|
|
.AUDIO_R(audio_r),
|
|
.AUDIO_S(audio_s),
|
|
.TAPE_IN(0),
|
|
|
|
// SCK -> CLK
|
|
// MOSI -> CMD
|
|
// MISO <- DAT0
|
|
// Z -> DAT1
|
|
// Z -> DAT2
|
|
// CS -> DAT3
|
|
|
|
.SD_SCK(SDIO_CLK),
|
|
.SD_MOSI(SDIO_CMD),
|
|
.SD_MISO(SDIO_DAT[0]),
|
|
.SD_CS(SDIO_DAT[3]),
|
|
|
|
.DDRAM_CLK(ram_clk),
|
|
.DDRAM_ADDR(ram_address),
|
|
.DDRAM_BURSTCNT(ram_burstcount),
|
|
.DDRAM_BUSY(ram_waitrequest),
|
|
.DDRAM_DOUT(ram_readdata),
|
|
.DDRAM_DOUT_READY(ram_readdatavalid),
|
|
.DDRAM_RD(ram_read),
|
|
.DDRAM_DIN(ram_writedata),
|
|
.DDRAM_BE(ram_byteenable),
|
|
.DDRAM_WE(ram_write),
|
|
|
|
.SDRAM_DQ(SDRAM_DQ),
|
|
.SDRAM_A(SDRAM_A),
|
|
.SDRAM_DQML(SDRAM_DQML),
|
|
.SDRAM_DQMH(SDRAM_DQMH),
|
|
.SDRAM_BA(SDRAM_BA),
|
|
.SDRAM_nCS(SDRAM_nCS),
|
|
.SDRAM_nWE(SDRAM_nWE),
|
|
.SDRAM_nRAS(SDRAM_nRAS),
|
|
.SDRAM_nCAS(SDRAM_nCAS),
|
|
.SDRAM_CLK(SDRAM_CLK),
|
|
.SDRAM_CKE(SDRAM_CKE)
|
|
);
|
|
|
|
endmodule
|