mirror of
https://github.com/rdolbeau/NuBusFPGA.git
synced 2024-09-27 11:55:41 +00:00
204 lines
6.7 KiB
Coq
204 lines
6.7 KiB
Coq
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/*
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* NuBus controller
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*
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* Autor: Valeriya Pudova (hww.github.io)
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*/
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module nubus
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#(
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// All slots area starts with addrss $FXXX XXXX
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parameter SLOTS_ADDRESS = 'hF,
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// All superslots starts at $9000 0000
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parameter SUPERSLOTS_ADDRESS = 'h9,
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// Watch dog timer bits. Master controller will terminate transfer
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// after (2 ^ WDT_W) clocks
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parameter WDT_W = 8,
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// Local space of card start and end addres. For example 0-5
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// makes local space address $00000000-$50000000
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parameter LOCAL_SPACE_EXPOSED_TO_NUBUS = 0,
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parameter LOCAL_SPACE_START = 0,
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parameter LOCAL_SPACE_END = 5,
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// Generate parity without ECC memory
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parameter NON_ECC_PARITY = 0
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)
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(
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/* NuBus signals */
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input nub_clkn, // Clock (rising is driving edge, faling is sampling)
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input nub_resetn, // Reset
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input [ 3:0] nub_idn, // Slot Identificatjon
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// inout nub_pfwn, // Power Fail Warning
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inout [31:0] nub_adn, // Address/Data
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inout nub_tm0n, // Transfer Mode
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inout nub_tm1n, // Transfer Mode
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inout nub_startn, // Start
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inout nub_rqstn, // Request
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inout nub_ackn, // Acknowledge
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// inout [ 3:0] nub_arbn, // Arbitration
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output arb,
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input grant,
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output tmoen,
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output NUBUS_AD_DIR,
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inout nub_nmrqn, // Non-Master Request
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// inout nub_spn, // System Parity
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// inout nub_spvn, // System Parity Valid
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/* Memory bus signals connected to a memory, accesible by nubus or processor */
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output mem_valid,
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output [31:0] mem_addr,
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output [31:0] mem_wdata,
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output [ 3:0] mem_write,
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input mem_ready,
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input [31:0] mem_rdata,
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input mem_error,
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input mem_tryagain,
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// Access to slot area
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output mem_stdslot,
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// Access to superslot area ($sXXXXXXX where <s> is card id)
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output mem_super,
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// Access to local memory on the card
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output mem_local
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);
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`include "nubus.svh"
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// ==========================================================================
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// Colock and reset
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// ==========================================================================
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wire nub_clk = ~nub_clkn;
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wire nub_reset = ~nub_resetn;
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// ==========================================================================
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// Global signals
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// ==========================================================================
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wire slv_master, slv_slave, slv_tm1n, slv_tm0n, slv_ackcyn, slv_myslotcy;
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wire unsigned [31:0] slv_addr;
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wire drv_tmoen, drv_mstdn;
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wire mst_timeout;
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// ==========================================================================
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// Drive NuBus address-data line
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// ==========================================================================
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// Select nubus data signals
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wire [31:0] nub_ad = mem_rdata;
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// When 1 - drive the NuBus AD lines
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wire nub_adoe = slv_slave & slv_tm1n
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/*SLAVE read of card*/
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;
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// Output to nubus the
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assign nub_adn = nub_adoe ? ~nub_ad : 'bZ;
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assign mem_valid = slv_myslotcy;
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assign NUBUS_AD_DIR = ~nub_adoe;
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// ==========================================================================
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// Parity checking
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// ==========================================================================
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//wire parity = ~^nub_adn;
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//wire nub_noparity = NON_ECC_PARITY & ~nub_adoe & ~nub_spvn & nub_spn == parity;
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//assign nub_spn = NON_ECC_PARITY & nub_adoe ? parity : 'bZ;
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//assign nub_spvn = NON_ECC_PARITY & nub_adoe ? 0 : 'bZ;
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// ==========================================================================
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// Slave FSM
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// ==========================================================================
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nubus_slave
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#(
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.SLOTS_ADDRESS (SLOTS_ADDRESS),
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.SUPERSLOTS_ADDRESS(SUPERSLOTS_ADDRESS),
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.SIMPLE_MAP(0),
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.LOCAL_SPACE_EXPOSED_TO_NUBUS(LOCAL_SPACE_EXPOSED_TO_NUBUS),
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.LOCAL_SPACE_START(LOCAL_SPACE_START),
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.LOCAL_SPACE_END(LOCAL_SPACE_END)
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)
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USlave
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(
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.nub_clkn(nub_clkn), // Clock
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.nub_resetn(nub_resetn), // Reset
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.nub_idn(nub_idn), // Card ID
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.nub_adn(nub_adn), // Address Data
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.nub_startn(nub_startn), // Transfer start
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.nub_ackn(nub_ackn), // Transfer end
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.nub_tm1n(nub_tm1n), // Transition mode 1 (Read/Write)
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.nub_tm0n(nub_tm0n),
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.mem_ready(mem_ready),
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.mst_timeout(0),
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.slv_slave_o(slv_slave), // Slave mode
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.slv_tm1n_o(slv_tm1n), // Latched transition mode 1 (Read/Write)
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.slv_tm0n_o(slv_tm0n),
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.slv_ackcyn_o(slv_ackcyn), // Acknowlege
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.slv_addr_o(slv_addr), // Slave address
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.slv_stdslot_o(mem_stdslot), // Starndard slot
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.slv_super_o(mem_super), // Superslot
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.slv_local_o(mem_local), // Local area
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.slv_myslotcy_o(slv_myslotcy) // Any slot
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);
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// ==========================================================================
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// Driver Nubus
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// ==========================================================================
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assign tmoen = drv_tmoen;
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nubus_driver UNDriver
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(
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.slv_ackcyn(slv_ackcyn), // Achnowlege
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.mst_arbcyn(1), // Arbiter enabled
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.mst_adrcyn(1), // Address strobe
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.mst_dtacyn(1), // Data strobe
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.mst_ownern(1), // Master is owner of the bus
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.mst_lockedn(1), // Locked or not transfer
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.mst_tm1n(1), // Address ines
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.mst_tm0n(1), // Address ines
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.mst_timeout(0),
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.mis_errorn(TMN_COMPLETE),
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.nub_tm0n_o(nub_tm0n), // Transfer mode
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.nub_tm1n_o(nub_tm1n), // Transfer mode
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.nub_ackn_o(nub_ackn), // Achnowlege
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.nub_startn_o(nub_startn), // Transfer start
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.nub_rqstn_o(nub_rqstn), // Bus request
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.nub_rqstoen_o(nub_qstoen), // Bus request enable
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.drv_tmoen_o(drv_tmoen), // Transfer mode enable
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.drv_mstdn_o(drv_mstdn) // Guess: Slave sends /ACK. Master responds with /MSTDN, which allows slave to clear /ACK and listen for next transaction.
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);
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// ==========================================================================
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// Memory Interface
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// ==========================================================================
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nubus_membus UMemBus
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(
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.nub_clkn(nub_clkn), // Clock
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.nub_resetn(nub_resetn), // Reset
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.nub_adn(nub_adn),
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.slv_tm1n(slv_tm1n),
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.slv_tm0n(slv_tm0n),
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.slv_myslotcy(slv_myslotcy),
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.slv_addr(slv_addr),
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.mem_addr_o(mem_addr),
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.mem_write_o(mem_write),
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.mem_wdata_o(mem_wdata)
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);
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endmodule
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