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https://github.com/rdolbeau/NuBusFPGA.git
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track V1.2 pcb update
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13
nubus-to-ztex-gateware/do_V1.2
Normal file
13
nubus-to-ztex-gateware/do_V1.2
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@ -0,0 +1,13 @@
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(
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source /opt/Xilinx/Vivado/2020.1/settings64.sh
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export LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2020.1/lib/lnx64.o/SuSE
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python3 nubus_to_fpga_soc.py --build --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6 --goblin --goblin-res 1920x1080@60Hz --hdmi
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#python3 nubus_to_fpga_soc.py --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6
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) 2>&1 | tee build_V1_2.log
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# --goblin --goblin-res 1280x1024@60Hz
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# --hdmi
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grep -A10 'Design Timing Summary' build/ztex213_nubus_V1_2/gateware/ztex213_nubus_V1_2_timing.rpt
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@ -60,7 +60,11 @@ class NuBus(Module):
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self.nubus_oe = nubus_oe = Signal() # improveme
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self.nubus_oe = nubus_oe = Signal() # improveme
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# those are needed in both Nubus and cpld integrated part now
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# those are needed in both Nubus and cpld integrated part now
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broadcast_id_3v3_n = platform.request("id_3v3_n")
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raw_broadcast_id_3v3_n = platform.request("id_3v3_n")
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broadcast_id_3v3_n = Signal(4)
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self.comb += [
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broadcast_id_3v3_n.eq(Cat(raw_broadcast_id_3v3_n, Signal(1, reset = 0))) # add missing ID3 in V1_2
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]
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# those are 'return' signals (O part of IO separated in I and O)
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# those are 'return' signals (O part of IO separated in I and O)
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# the 3v3 signals 'see' the 5V signals from the external drivers
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# the 3v3 signals 'see' the 5V signals from the external drivers
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internal_start_3v3_n = Signal()
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internal_start_3v3_n = Signal()
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@ -7,14 +7,14 @@ import litex
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import wishbone
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class NuBus(Module):
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class NuBus(Module):
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def __init__(self, soc,
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def __init__(self, soc, version,
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burst_size, tosbus_fifo, fromsbus_fifo, fromsbus_req_fifo,
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burst_size, tosbus_fifo, fromsbus_fifo, fromsbus_req_fifo,
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wb_read, wb_write, wb_dma,
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wb_read, wb_write, wb_dma,
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usesampling=False,
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usesampling=False,
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cd_nubus="nubus", cd_nubus90="nubus90"):
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cd_nubus="nubus", cd_nubus90="nubus90"):
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platform = soc.platform
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platform = soc.platform
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self.add_sources(platform)
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self.add_sources(platform, version)
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#led0 = platform.request("user_led", 0)
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#led0 = platform.request("user_led", 0)
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#led1 = platform.request("user_led", 1)
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#led1 = platform.request("user_led", 1)
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@ -714,54 +714,91 @@ class NuBus(Module):
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# stuff at this end so we don't use the signals inadvertantly
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# stuff at this end so we don't use the signals inadvertantly
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# real NuBus signals
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# real NuBus signals
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nub_tm0n = platform.request("tm0_3v3_n")
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nub_tm0n = platform.request("tm0_3v3_n") # V1.0: from CPLD ; V1.2: from shifters
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nub_tm1n = platform.request("tm1_3v3_n")
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nub_tm1n = platform.request("tm1_3v3_n") # V1.0: from CPLD ; V1.2: from shifters
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nub_startn = platform.request("start_3v3_n")
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nub_startn = platform.request("start_3v3_n") # V1.0: from CPLD ; V1.2: from shifters
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nub_ackn = platform.request("ack_3v3_n")
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nub_ackn = platform.request("ack_3v3_n") # V1.0: from CPLD ; V1.2: from shifters
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nub_adn = platform.request("ad_3v3_n")
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nub_adn = platform.request("ad_3v3_n") # V1.0: from CPLD ; V1.2: from shifters
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nub_idn = platform.request("id_3v3_n")
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nub_idn = platform.request("id_3v3_n") # V1.0: from CPLD (4 bits) ; V1.2: from shifters (3 bits, /ID3 is always 0)
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# Tri-state
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# Tri-state
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self.specials += Tristate(nub_tm0n, tm0_o_n, tmo_oe, tm0_i_n)
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if (version == "V1.0"):
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self.specials += Tristate(nub_tm1n, tm1_o_n, tmo_oe, tm1_i_n)
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# tri-state communication with CPLD
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self.specials += Tristate(nub_ackn, ack_o_n, tmo_oe, ack_i_n)
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self.specials += Tristate(nub_tm0n, tm0_o_n, tmo_oe, tm0_i_n)
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self.specials += Tristate(nub_adn, ad_o_n, ad_oe, ad_i_n)
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self.specials += Tristate(nub_tm1n, tm1_o_n, tmo_oe, tm1_i_n)
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self.specials += Tristate(nub_startn, start_o_n, master_oe, start_i_n)
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self.specials += Tristate(nub_ackn, ack_o_n, tmo_oe, ack_i_n)
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self.comb += [
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self.specials += Tristate(nub_adn, ad_o_n, ad_oe, ad_i_n)
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id_i_n.eq(nub_idn),
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self.specials += Tristate(nub_startn, start_o_n, master_oe, start_i_n)
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]
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elif (version == "V1.2"):
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# input only
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self.comb += [
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tm0_i_n.eq(nub_tm0n),
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tm1_i_n.eq(nub_tm1n),
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ack_i_n.eq(nub_ackn),
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ad_i_n.eq(nub_adn),
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start_i_n.eq(nub_startn),
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]
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else:
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raise ValueError(f"Unsupported version {version}")
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# input only
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if (version == "V1.0"):
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self.comb += [
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id_i_n.eq(nub_idn),
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]
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elif (version == "V1.2"):
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self.comb += [
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id_i_n.eq(Cat(nub_idn, Signal(1, reset = 0))),
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]
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else:
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raise ValueError(f"Unsupported version {version}")
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# NubusFPGA-only signals
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# NubusFPGA-only signals
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nf_tmoen = platform.request("tmoen")
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nf_nubus_ad_dir = platform.request("nubus_ad_dir") # to drivers
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nf_nubus_ad_dir = platform.request("nubus_ad_dir")
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self.comb += [
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self.comb += [
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nf_tmoen.eq(~tmo_oe),
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nf_nubus_ad_dir.eq(~ad_oe),
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nf_nubus_ad_dir.eq(~ad_oe),
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]
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]
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if (version == "V1.0"):
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nf_tmoen = platform.request("tmoen") # to cpld
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self.comb += [
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nf_tmoen.eq(~tmo_oe),
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]
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# real Nubus signal, for master
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# real Nubus signal, for master
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nub_rqstn = platform.request("rqst_3v3_n")
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nub_rqstn = platform.request("rqst_3v3_n") # V1.0: from CPLD ; V1.2: from shifters
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# Tri-state
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# Tri-state
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self.specials += Tristate(nub_rqstn, rqst_o_n, rqst_oe, rqst_i_n)
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if (version == "V1.0"):
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# tri-state communication with CPLD
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self.specials += Tristate(nub_rqstn, rqst_o_n, rqst_oe, rqst_i_n)
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elif (version == "V1.2"):
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# input only
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self.comb += [
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rqst_i_n.eq(nub_rqstn),
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]
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else:
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raise ValueError(f"Unsupported version {version}")
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# NubusFPGA-only signals, for master
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# NubusFPGA-only signals, for master
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nub_arbcy_n = platform.request("arbcy_n")
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if (version == "V1.0"):
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nf_grant = platform.request("grant")
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nub_arbcy_n = platform.request("arbcy_n") # V1.0: from cpld
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nf_nubus_master_dir = platform.request("nubus_master_dir")
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nf_grant = platform.request("grant") # V1.0: from cpld
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nf_fpga_to_cpld_signal = platform.request("fpga_to_cpld_signal")
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nf_nubus_master_dir = platform.request("nubus_master_dir") # V1.0: to cpld
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nf_fpga_to_cpld_signal = platform.request("fpga_to_cpld_signal") # V1.0: to cpld, 'rqstoen'
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# NuBus90 signals, , for completeness
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# NuBus90 signals, , for completeness
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nub_clk2xn = ClockSignal(cd_nubus90)
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nub_clk2xn = ClockSignal(cd_nubus90)
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nub_tm2n = platform.request("tm2_3v3_n")
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nub_tm2n = platform.request("tm2_3v3_n") # V1.0: from CPLD ; V1.2: from shifters
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self.comb += [
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if (version == "V1.0"):
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nf_nubus_master_dir.eq(master_oe),
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self.comb += [
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nub_arbcy_n.eq(~start_arbitration),
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nf_nubus_master_dir.eq(master_oe),
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grant.eq(nf_grant),
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nub_arbcy_n.eq(~start_arbitration),
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nf_fpga_to_cpld_signal.eq(~rqst_oe),
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grant.eq(nf_grant),
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]
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nf_fpga_to_cpld_signal.eq(~rqst_oe),
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]
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if (usesampling):
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if (usesampling):
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self.sync += [
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self.sync += [
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@ -771,6 +808,50 @@ class NuBus(Module):
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)
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)
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]
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]
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def add_sources(self, platform):
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if (version == "V1.2"):
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self.nubus_oe = nubus_oe = Signal() # improveme
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self.specials += Instance("nubus_cpldinfpga",
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i_nubus_oe = nubus_oe, # improveme: handled in soc
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i_tmoen = ~tmo_oe,
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i_nubus_master_dir = master_oe,
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i_rqst_oe_n = ~rqst_oe,
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i_id_n_3v3 = id_i_n, # input only
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i_arbcy_n = ~start_arbitration,
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i_arb_n_3v3 = platform.request("arb_3v3_n"), # arb only seen by cpld
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o_arb_o_n = platform.request("arb_o_n"),
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o_grant = grant,
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i_tm0_n_3v3 = tm0_o_n, # tm0 driving controlled by tmoen
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o_tm0_o_n = platform.request("tm0_o_n"),
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i_tm1_n_3v3 = tm1_o_n, # tm1 driving controlled by tmoen
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o_tm1_o_n = platform.request("tm1_o_n"),
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o_tmx_oe_n = platform.request("tmx_oe_n"),
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i_tm2_n_3v3 = nub_tm2n, # tm2 currently never driven
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o_tm2_o_n = platform.request("tm2_o_n"),
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o_tm2_oe_n = platform.request("tm2_oe_n"),
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i_start_n_3v3 = start_o_n, # start driving enabled by nubus_master_dir
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o_start_o_n = platform.request("start_o_n"),
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o_start_oe_n = platform.request("start_oe_n"),
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i_ack_n_3v3 = ack_o_n, # ack driving controlled by tmoen
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o_ack_o_n = platform.request("ack_o_n"),
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o_ack_oe_n = platform.request("ack_oe_n"),
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i_rqst_n_3v3 = rqst_o_n, # rqst driving controller by rqst_oe_n
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o_rqst_o_n = platform.request("rqst_o_n")
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)
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def add_sources(self, platform, version):
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# sampling of data on falling edge of clock, done in verilog
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# sampling of data on falling edge of clock, done in verilog
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platform.add_source("nubus_sampling.v", "verilog")
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platform.add_source("nubus_sampling.v", "verilog")
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if (version == "V1.2"):
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platform.add_source("nubus_arbiter.v", "verilog") # for CPLDinfpga
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platform.add_source("nubus_cpldinfpga.v", "verilog") # internal now
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@ -42,7 +42,7 @@ from nubus_cpu_wb import Wishbone2NuBus
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# CRG ----------------------------------------------------------------------------------------------
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq,
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def __init__(self, platform, version, sys_clk_freq,
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goblin=False,
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goblin=False,
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hdmi=False,
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hdmi=False,
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pix_clk=0):
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pix_clk=0):
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@ -74,6 +74,17 @@ class _CRG(Module):
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self.specials += Instance("BUFG", i_I=clk48, o_O=self.clk48_bufg)
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self.specials += Instance("BUFG", i_I=clk48, o_O=self.clk48_bufg)
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self.comb += self.cd_native.clk.eq(self.clk48_bufg)
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self.comb += self.cd_native.clk.eq(self.clk48_bufg)
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#self.cd_native.clk = clk48
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#self.cd_native.clk = clk48
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##### V1.2 extra clock for B34
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if (version == "V1.2"):
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self.clock_domains.cd_bank34 = ClockDomain()
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clk54 = platform.request("clk54")
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self.clk54_bufg = Signal()
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self.specials += Instance("BUFG", i_I=clk54, o_O=self.clk54_bufg)
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self.comb += self.cd_native.clk.eq(self.clk54_bufg)
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else:
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clk54 = None
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clk_nubus = platform.request("clk_3v3_n")
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clk_nubus = platform.request("clk_3v3_n")
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if (clk_nubus is None):
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if (clk_nubus is None):
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@ -108,8 +119,8 @@ class _CRG(Module):
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platform.add_platform_command("create_generated_clock -name sys4x90clk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
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platform.add_platform_command("create_generated_clock -name sys4x90clk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
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num_clk = num_clk + 1
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num_clk = num_clk + 1
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self.comb += pll.reset.eq(~rst_nubus_n) # | ~por_done
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self.comb += pll.reset.eq(~rst_nubus_n) # | ~por_done
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platform.add_false_path_constraints(self.cd_native.clk, self.cd_nubus.clk) # FIXME?
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platform.add_false_path_constraints(clk48, self.cd_nubus.clk) # FIXME?
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platform.add_false_path_constraints(self.cd_nubus.clk, self.cd_native.clk) # FIXME?
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platform.add_false_path_constraints(self.cd_nubus.clk, clk48) # FIXME?
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#platform.add_false_path_constraints(self.cd_sys.clk, self.cd_nubus.clk)
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#platform.add_false_path_constraints(self.cd_sys.clk, self.cd_nubus.clk)
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#platform.add_false_path_constraints(self.cd_nubus.clk, self.cd_sys.clk)
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#platform.add_false_path_constraints(self.cd_nubus.clk, self.cd_sys.clk)
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##platform.add_false_path_constraints(self.cd_native.clk, self.cd_sys.clk)
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##platform.add_false_path_constraints(self.cd_native.clk, self.cd_sys.clk)
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@ -130,7 +141,15 @@ class _CRG(Module):
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if (goblin):
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if (goblin):
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self.submodules.video_pll = video_pll = S7MMCM(speedgrade=platform.speedgrade)
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self.submodules.video_pll = video_pll = S7MMCM(speedgrade=platform.speedgrade)
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video_pll.register_clkin(self.clk48_bufg, 48e6)
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if (clk54 is None):
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# no 54 MHz clock, drive hdmi from the main clock
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video_pll.register_clkin(self.clk48_bufg, 48e6)
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else:
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# drive hdmi from the 54 MHz clock, easier to generate e.g. 148.5 MHz
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video_pll.register_clkin(self.clk54_bufg, 54e6)
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platform.add_false_path_constraints(self.cd_bank34.clk, self.cd_nubus.clk) # FIXME?
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platform.add_false_path_constraints(self.cd_bank34.clk, clk48) # FIXME?
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if (not hdmi):
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if (not hdmi):
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video_pll.create_clkout(self.cd_vga, pix_clk, margin = 0.0005)
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video_pll.create_clkout(self.cd_vga, pix_clk, margin = 0.0005)
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platform.add_platform_command("create_generated_clock -name vga_clk [get_pins {{{{MMCME2_ADV_{}/CLKOUT{}}}}}]".format(num_adv, num_clk))
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platform.add_platform_command("create_generated_clock -name vga_clk [get_pins {{{{MMCME2_ADV_{}/CLKOUT{}}}}}]".format(num_adv, num_clk))
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@ -223,7 +242,7 @@ class NuBusFPGA(SoCCore):
|
|||||||
#"END OF SLOT SPACE": 0xF0FFFFFF,
|
#"END OF SLOT SPACE": 0xF0FFFFFF,
|
||||||
}
|
}
|
||||||
self.mem_map.update(wb_mem_map)
|
self.mem_map.update(wb_mem_map)
|
||||||
self.submodules.crg = _CRG(platform=platform, sys_clk_freq=sys_clk_freq, goblin=goblin, hdmi=hdmi, pix_clk=litex.soc.cores.video.video_timings[goblin_res]["pix_clk"])
|
self.submodules.crg = _CRG(platform=platform, version=version, sys_clk_freq=sys_clk_freq, goblin=goblin, hdmi=hdmi, pix_clk=litex.soc.cores.video.video_timings[goblin_res]["pix_clk"])
|
||||||
|
|
||||||
## add our custom timings after the clocks have been defined
|
## add our custom timings after the clocks have been defined
|
||||||
xdc_timings_filename = None;
|
xdc_timings_filename = None;
|
||||||
@ -404,6 +423,7 @@ class NuBusFPGA(SoCCore):
|
|||||||
self.comb += dma_irq.eq(self.exchange_with_mem.irq)
|
self.comb += dma_irq.eq(self.exchange_with_mem.irq)
|
||||||
|
|
||||||
self.submodules.nubus = nubus_full_unified.NuBus(soc=self,
|
self.submodules.nubus = nubus_full_unified.NuBus(soc=self,
|
||||||
|
version=version,
|
||||||
burst_size=burst_size,
|
burst_size=burst_size,
|
||||||
tosbus_fifo=self.tosbus_fifo,
|
tosbus_fifo=self.tosbus_fifo,
|
||||||
fromsbus_fifo=self.fromsbus_fifo,
|
fromsbus_fifo=self.fromsbus_fifo,
|
||||||
|
@ -101,6 +101,8 @@ _nubus_io_v1_0 = [
|
|||||||
]
|
]
|
||||||
|
|
||||||
_nubus_io_v1_2 = [
|
_nubus_io_v1_2 = [
|
||||||
|
## extra 54 MHz clock reference for bank 34
|
||||||
|
("clk54", 0, Pins("R3"), IOStandard("LVCMOS33")),
|
||||||
## leds on the NuBus board
|
## leds on the NuBus board
|
||||||
("user_led", 0, Pins("U9"), IOStandard("lvcmos33")), #LED0
|
("user_led", 0, Pins("U9"), IOStandard("lvcmos33")), #LED0
|
||||||
("user_led", 1, Pins("V9"), IOStandard("lvcmos33")), #LED1; both are overlapping with serial TX/RX
|
("user_led", 1, Pins("V9"), IOStandard("lvcmos33")), #LED1; both are overlapping with serial TX/RX
|
||||||
@ -179,7 +181,7 @@ _nubus_nubus_v1_2 = [
|
|||||||
("ack_o_n", 0, Pins("H14"), IOStandard("lvttl")),
|
("ack_o_n", 0, Pins("H14"), IOStandard("lvttl")),
|
||||||
("ack_oe_n", 0, Pins("J13"), IOStandard("lvttl")),
|
("ack_oe_n", 0, Pins("J13"), IOStandard("lvttl")),
|
||||||
("nmrq_3v3_n", 0, Pins("K16"), IOStandard("lvttl")), # 'irq' line, Output only direct to 74LVT125
|
("nmrq_3v3_n", 0, Pins("K16"), IOStandard("lvttl")), # 'irq' line, Output only direct to 74LVT125
|
||||||
("reset_3v3_n", 0, Pins("R3"), IOStandard("lvttl")), # Input only
|
("reset_3v3_n", 0, Pins("U8"), IOStandard("lvttl")), # Input only
|
||||||
("rqst_3v3_n" , 0, Pins("J18"), IOStandard("lvttl")), # Open Collector
|
("rqst_3v3_n" , 0, Pins("J18"), IOStandard("lvttl")), # Open Collector
|
||||||
("rqst_o_n" , 0, Pins("K13"), IOStandard("lvttl")),
|
("rqst_o_n" , 0, Pins("K13"), IOStandard("lvttl")),
|
||||||
("start_3v3_n", 0, Pins("K15"), IOStandard("lvttl")),
|
("start_3v3_n", 0, Pins("K15"), IOStandard("lvttl")),
|
||||||
@ -191,7 +193,7 @@ _nubus_nubus_v1_2 = [
|
|||||||
"D17 D18 E17 E18 F15 F18 F16 G18 "), IOStandard("lvttl")),
|
"D17 D18 E17 E18 F15 F18 F16 G18 "), IOStandard("lvttl")),
|
||||||
("arb_3v3_n", 0, Pins("T8 V4 V5 U6"), IOStandard("lvttl")), # Open Collector
|
("arb_3v3_n", 0, Pins("T8 V4 V5 U6"), IOStandard("lvttl")), # Open Collector
|
||||||
("arb_o_n", 0, Pins("J14 G16 G14 H17"), IOStandard("lvttl")),
|
("arb_o_n", 0, Pins("J14 G16 G14 H17"), IOStandard("lvttl")),
|
||||||
("id_3v3_n", 0, Pins("U7 V6 V7 U8"), IOStandard("lvttl")),
|
("id_3v3_n", 0, Pins("U7 V6 V7"), IOStandard("lvttl")),
|
||||||
("tm0_3v3_n", 0, Pins("U2"), IOStandard("lvttl")),
|
("tm0_3v3_n", 0, Pins("U2"), IOStandard("lvttl")),
|
||||||
("tm0_o_n", 0, Pins("T6"), IOStandard("lvttl")),
|
("tm0_o_n", 0, Pins("T6"), IOStandard("lvttl")),
|
||||||
("tm1_3v3_n", 0, Pins("V2"), IOStandard("lvttl")),
|
("tm1_3v3_n", 0, Pins("V2"), IOStandard("lvttl")),
|
||||||
|
Loading…
Reference in New Issue
Block a user