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https://github.com/rdolbeau/NuBusFPGA.git
synced 2025-01-03 11:29:46 +00:00
disable leds
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parent
7eb5f578c3
commit
45de956195
@ -15,8 +15,8 @@ class NuBus(Module):
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platform = soc.platform
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self.add_sources(platform)
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led0 = platform.request("user_led", 0)
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led1 = platform.request("user_led", 1)
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#led0 = platform.request("user_led", 0)
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#led1 = platform.request("user_led", 1)
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nub_clk = ClockSignal(cd_nubus)
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nub_resetn = ~ResetSignal(cd_nubus)
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@ -430,7 +430,6 @@ class NuBus(Module):
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If(sampled_ack,
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wb_dma.ack.eq(1),
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# fixme: check status ??? (tm0 and tm1 should be active for no-error)
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#NextValue(led0, (~sampled_tm0 | ~sampled_tm1)),
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NextState("FinishCycle"),
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)
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)
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@ -450,7 +449,6 @@ class NuBus(Module):
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If(sampled_ack,
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wb_dma.ack.eq(1),
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# fixme: check status ??? (tm0 and tm1 should be active for no-error)
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#NextValue(led0, (~sampled_tm0 | ~sampled_tm1)),
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NextState("FinishCycle"),
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)
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)
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@ -559,11 +557,11 @@ class NuBus(Module):
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)
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)
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self.comb += [
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led0.eq(~dma_fsm.ongoing("Idle")),
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#led1.eq(dma_fsm.ongoing("Burst4DatCycleAck") | dma_fsm.ongoing("Burst4DatCycleTM0") ),
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led1.eq(sampled_rqst | wb_dma.cyc),
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]
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#self.comb += [
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# led0.eq(~dma_fsm.ongoing("Idle")),
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# #led1.eq(dma_fsm.ongoing("Burst4DatCycleAck") | dma_fsm.ongoing("Burst4DatCycleTM0") ),
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# led1.eq(sampled_rqst | wb_dma.cyc),
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#]
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# stuff at this end so we don't use the signals inadvertantly
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