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arbiter source file needed
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@ -172,7 +172,7 @@ class NuBus(Module):
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platform.add_source("nubus.v", "verilog")
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# XiBus is from my github, branch 'more_fixes'
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platform.add_source("XiBus/nubus.svh", "verilog")
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#platform.add_source("XiBus/nubus_arbiter.v", "verilog") # in the CPLDinfpga
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platform.add_source("nubus_arbiter.v", "verilog") # for CPLDinfpga
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platform.add_source("XiBus/nubus_cpubus.v", "verilog")
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platform.add_source("XiBus/nubus_driver.v", "verilog")
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#platform.add_source("XiBus/nubus_errors.v", "verilog") # unused
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@ -247,7 +247,7 @@ class NuBusFPGA(SoCCore):
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#self.submodules.wa2d = WA2D(self.platform)
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#self.bus.add_slave("WA2D", self.wa2d.bus, SoCRegion(origin=0x00C00000, size=0x00400000, cached=False))
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notsimul = 0
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notsimul = 1
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if (notsimul):
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avail_sdram = 0
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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