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11
README.md
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11
README.md
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|
@ -0,0 +1,11 @@
|
|||
# A FPGA on a NuBus card...
|
||||
|
||||
## Goal
|
||||
|
||||
The goal of this repository is to be able to interface a modern (202 era) [FPGA](https://e
|
||||
n.wikipedia.org/wiki/Field-programmable_gate_array) with a [NuBus](https://en.wikipedia.org/
|
||||
wiki/NuBus) host, specifically Apple's [Macintosh II](https://en.wikipedia.org/wiki/Macintosh_II_family) and [Macintosh Quadra](https://en.wikipedia.org/wiki/Macintosh_Quadra).
|
||||
|
||||
## Current status
|
||||
|
||||
Early draft version, this has not been built or tested.
|
13
nubus-to-ztex-gateware/74fct245.v
Normal file
13
nubus-to-ztex-gateware/74fct245.v
Normal file
|
@ -0,0 +1,13 @@
|
|||
module sn74fct245
|
||||
(
|
||||
input nubus_oe,
|
||||
input nubus_ad_dir,
|
||||
inout [7:0] data_3v3, // on B
|
||||
inout [7:0] data_5v // on A
|
||||
);
|
||||
|
||||
assign data_3v3 = nubus_oe ? 'bZZZZZZZZ : ( nubus_ad_dir ? data_5v : 'bZZZZZZZZ);
|
||||
assign data_5v = nubus_oe ? 'bZZZZZZZZ : (~nubus_ad_dir ? data_3v3 : 'bZZZZZZZZ);
|
||||
|
||||
endmodule // sn74fct245
|
||||
|
36
nubus-to-ztex-gateware/DeclROM/DepVideo.inc
Normal file
36
nubus-to-ztex-gateware/DeclROM/DepVideo.inc
Normal file
|
@ -0,0 +1,36 @@
|
|||
NuBusFPGAID = 0xBEEF
|
||||
|
||||
defMinorBase = 0 /* beginning */
|
||||
defMinorLength = 0xC0000 /* 768 KiB */
|
||||
|
||||
Pages8s = 1 /* no idea */
|
||||
|
||||
defmBounds_Ts = 0
|
||||
defmBounds_Ls = 0
|
||||
defmBounds_Bs = 480
|
||||
defmBounds_Rs = 640
|
||||
|
||||
DrHwNuBusFPGA = 0xBEEF /* placeholder */
|
||||
|
||||
defmBaseOffset = 0 /* beginning, placeholder */
|
||||
|
||||
devVersion = 0 /* placeholder */
|
||||
|
||||
defmHRes = 0x480000 /* Horizontal Pixels/inch */
|
||||
defmVRes = 0x480000 /* Vertical pixels/inch */
|
||||
|
||||
defmDevType = 0 /* 0 = CLUTType */
|
||||
|
||||
defmPlaneBytes = 0 /* Offset from one plane to the next. */
|
||||
|
||||
SGammaResID = 0
|
||||
|
||||
RB8s = 640
|
||||
|
||||
|
||||
ChunkyIndexed = 0
|
||||
|
||||
defVersion = 0 /* Version = 0 */
|
||||
|
||||
ROMSize = 0x1000 /* 4K byte ROM */
|
||||
|
22
nubus-to-ztex-gateware/DeclROM/Makefile
Normal file
22
nubus-to-ztex-gateware/DeclROM/Makefile
Normal file
|
@ -0,0 +1,22 @@
|
|||
AS=/home/dolbeau/Retro68/build/toolchain/bin/m68k-apple-macos-as
|
||||
OBJCOPY=/home/dolbeau/Retro68/build/toolchain/bin/m68k-apple-macos-objcopy
|
||||
|
||||
NS816DECLROMDIR=/home/dolbeau/ns816-declrom
|
||||
NUBUS_CHECKSUM=${NS816DECLROMDIR}/nubus_checksum
|
||||
PROCESS_ROM=${NS816DECLROMDIR}/process_rom
|
||||
|
||||
APPLEINCS=${NS816DECLROMDIR}/atrap.inc ${NS816DECLROMDIR}/declrom.inc ${NS816DECLROMDIR}/globals.inc
|
||||
|
||||
all: vid_decl_rom.bin vid_decl_rom.srec
|
||||
|
||||
vid_decl_rom.o: vid_decl_rom.s ${APPLEINCS}
|
||||
${AS} -march=68020 -mcpu=68020 -I${NS816DECLROMDIR} $< -o $@ -a > vid_decl_rom.l
|
||||
|
||||
vid_decl_rom.srec: vid_decl_rom.o
|
||||
${OBJCOPY} $< $@ --input-target=elf32-m68k --output-target=srec
|
||||
|
||||
vid_decl_rom.raw: vid_decl_rom.o
|
||||
${OBJCOPY} $< $@ --input-target=elf32-m68k --output-target=binary
|
||||
|
||||
vid_decl_rom.bin: vid_decl_rom.raw
|
||||
${NUBUS_CHECKSUM} --input_file $< --output_file $@ --output_size 4096
|
197
nubus-to-ztex-gateware/DeclROM/ROMDefs.inc
Normal file
197
nubus-to-ztex-gateware/DeclROM/ROMDefs.inc
Normal file
|
@ -0,0 +1,197 @@
|
|||
appleFormat = 1
|
||||
romRevision = 1
|
||||
romRevRange = 9
|
||||
testPattern = 1519594439L
|
||||
sCodeRev = 2
|
||||
sExec2 = 2
|
||||
sCPU68000 = 1
|
||||
sCPU68020 = 2
|
||||
sCPU68030 = 3
|
||||
sCPU68040 = 4
|
||||
sMacOS68000 = 1
|
||||
sMacOS68020 = 2
|
||||
sMacOS68030 = 3
|
||||
sMacOS68040 = 4
|
||||
board = 0
|
||||
displayVideoAppleTFB = 16843009L
|
||||
displayVideoAppleGM = 16843010L
|
||||
networkEtherNetApple3Com = 33620225L
|
||||
testSimpleAppleAny = -2147417856L
|
||||
endOfList = 255
|
||||
defaultTO = 100
|
||||
fOpenAtStart = 1
|
||||
f32BitMode = 2
|
||||
sRsrcType = 1
|
||||
sRsrcName = 2
|
||||
sRsrcIcon = 3
|
||||
sRsrcDrvrDir = 4
|
||||
sRsrcLoadDir = 5
|
||||
sRsrcBootRec = 6
|
||||
sRsrcFlags = 7
|
||||
sRsrcHWDevId = 8
|
||||
minorBaseOS = 10
|
||||
majorBaseOS = 12
|
||||
majorLength = 13
|
||||
sRsrcTest = 14
|
||||
sRsrccicn = 15
|
||||
sRsrcicl8 = 16
|
||||
sRsrcicl4 = 17
|
||||
sDRVRDir = 16
|
||||
sGammaDir = 64
|
||||
sRsrcVidNames = 65
|
||||
sRsrcDock = 80
|
||||
sDiagRec = 85
|
||||
sVidAuxParams = 123
|
||||
sDebugger = 124
|
||||
sVidAttributes = 125
|
||||
fLCDScreen = 0
|
||||
fBuiltInDisplay = 1
|
||||
fDefaultColor = 2
|
||||
fActiveBlack = 3
|
||||
fDimMinAt1 = 4
|
||||
fBuiltInDetach = 4
|
||||
sVidParmDir = 126
|
||||
sBkltParmDir = 140
|
||||
sSuperDir = 254
|
||||
/* = */
|
||||
/* = */
|
||||
catBoard = 0x0001
|
||||
catTest = 0x0002
|
||||
catDisplay = 0x0003
|
||||
catNetwork = 0x0004
|
||||
catScanner = 0x0008
|
||||
catCPU = 0x000A
|
||||
catIntBus = 0x000C
|
||||
catProto = 0x0011
|
||||
catDock = 0x0020
|
||||
typeBoard = 0x0000
|
||||
typeApple = 0x0001
|
||||
typeVideo = 0x0001
|
||||
typeEtherNet = 0x0001
|
||||
typeStation = 0x0001
|
||||
typeDesk = 0x0002
|
||||
typeTravel = 0x0003
|
||||
typeDSP = 0x0004
|
||||
typeXPT = 0x000B
|
||||
typeSIM = 0x000C
|
||||
typeDebugger = 0x0100
|
||||
type68000 = 0x0002
|
||||
type68020 = 0x0003
|
||||
type68030 = 0x0004
|
||||
type68040 = 0x0005
|
||||
type601 = 0x0025
|
||||
type603 = 0x002E
|
||||
typeAppleII = 0x0015
|
||||
drSwMacCPU = 0
|
||||
drSwAppleIIe = 0x0001
|
||||
drSwApple = 1
|
||||
drSwMacsBug = 0x0104
|
||||
drSwDepewEngineering = 0x0101
|
||||
drHwTFB = 1
|
||||
drHw3Com = 1
|
||||
drHwBSC = 3
|
||||
drHwGemini = 1
|
||||
drHwDeskBar = 1
|
||||
drHwATT3210 = 0x0001
|
||||
drHwBootBug = 0x0100
|
||||
drHwMicroDock = 0x0100
|
||||
drHwSTB3 = 0x0002
|
||||
drHwSTB = drHwSTB3
|
||||
drHwRBV = 0x0018
|
||||
drHwElsie = 0x001A
|
||||
drHwTim = 0x001B
|
||||
drHwDAFB = 0x001C
|
||||
drHwGSC = 0x001E
|
||||
drHwDAFBPDS = 0x001F
|
||||
drHWVSC = 0x0020
|
||||
drHwApollo = 0x0021
|
||||
drHwSonora = 0x0022
|
||||
drHwReserved2 = 0x0023
|
||||
drHwColumbia = 0x0024
|
||||
drHwCivic = 0x0025
|
||||
drHwBrazil = 0x0026
|
||||
drHWPBLCD = 0x0027
|
||||
drHWCSC = 0x0028
|
||||
drHwJET = 0x0029
|
||||
drHWMEMCjr = 0x002A
|
||||
drHwHPV = 0x002C
|
||||
drHwPlanaria = 0x002D
|
||||
drHwValkyrie = 0x002E
|
||||
drHwKeystone = 0x002F
|
||||
drHWATI = 0x0055
|
||||
drHwGammaFormula = 0x0056
|
||||
drHwSonic = 0x0110
|
||||
drHwMace = 0x0114
|
||||
drHwDblExp = 0x0001
|
||||
MIIBoardId = 0x0010
|
||||
ciVidBoardID = 0x001F
|
||||
CX16VidBoardID = 0x0020
|
||||
MIIxBoardId = 0x0021
|
||||
SE30BoardID = 0x0022
|
||||
MIIcxBoardId = 0x0023
|
||||
MIIfxBoardId = 0x0024
|
||||
EricksonBoardID = 0x0028
|
||||
ElsieBoardID = 0x0029
|
||||
TIMBoardID = 0x002A
|
||||
EclipseBoardID = 0x002B
|
||||
SpikeBoardID = 0x0033
|
||||
DBLiteBoardID = 0x0035
|
||||
ZydecoBrdID = 0x0036
|
||||
ApolloBoardID = 0x0038
|
||||
PDMBrdID = 0x0039
|
||||
VailBoardID = 0x003A
|
||||
WombatBrdID = 0x003B
|
||||
ColumbiaBrdID = 0x003C
|
||||
CycloneBrdID = 0x003D
|
||||
CompanionBrdID = 0x003E
|
||||
DartanianBoardID = 0x0040
|
||||
DartExtVidBoardID = 0x0046
|
||||
HookBoardID = 0x0047
|
||||
EscherBoardID = 0x004A
|
||||
POBoardID = 0x004D
|
||||
TempestBrdID = 0x0050
|
||||
BlackBirdBdID = 0x0058
|
||||
BBExtVidBdID = 0x0059
|
||||
YeagerBoardID = 0x005A
|
||||
BBEtherNetBdID = 0x005E
|
||||
TELLBoardID = 0x0065
|
||||
MalcolmBoardID = 0x065E
|
||||
AJBoardID = 0x065F
|
||||
M2BoardID = 0x0660
|
||||
OmegaBoardID = 0x0661
|
||||
TNTBoardID = 0x0670
|
||||
HooperBoardID = 0x06CD
|
||||
BoardIDDblExp = 0x002F
|
||||
DAFBPDSBoardID = 0x0037
|
||||
MonetBoardID = 0x0048
|
||||
SacSONIC16BoardID = 0x004E
|
||||
SacSONIC32BoardID = 0x004F
|
||||
drHWMacII = 0x0001
|
||||
drHwMacIIx = 0x0002
|
||||
drHWSE30 = 0x0003
|
||||
drHwMacIIcx = 0x0004
|
||||
drHWMacIIfx = 0x0005
|
||||
drHWF19 = 0x0005
|
||||
sBlockTransferInfo = 20
|
||||
sMaxLockedTransferCount = 21
|
||||
boardId = 32
|
||||
pRAMInitData = 33
|
||||
primaryInit = 34
|
||||
timeOutConst = 35
|
||||
vendorInfo = 36
|
||||
boardFlags = 37
|
||||
secondaryInit = 38
|
||||
MajRAMSp = 129
|
||||
MinROMSp = 130
|
||||
vendorId = 1
|
||||
serialNum = 2
|
||||
revLevel = 3
|
||||
partNum = 4
|
||||
date = 5
|
||||
testByte = 32
|
||||
testWord = 33
|
||||
testLong = 34
|
||||
testString = 35
|
||||
mBlockTransferInfo = 5
|
||||
mMaxLockedTransferCount = 6
|
||||
|
358
nubus-to-ztex-gateware/DeclROM/Video.inc
Normal file
358
nubus-to-ztex-gateware/DeclROM/Video.inc
Normal file
|
@ -0,0 +1,358 @@
|
|||
mBaseOffset = 1 /*IdofmBaseOffset.*/
|
||||
mRowBytes = 2 /*VideosResourceparameterId's*/
|
||||
mBounds = 3 /*VideosResourceparameterId's*/
|
||||
mVersion = 4 /*VideosResourceparameterId's*/
|
||||
mHRes = 5 /*VideosResourceparameterId's*/
|
||||
mVRes = 6 /*VideosResourceparameterId's*/
|
||||
mPixelType = 7 /*VideosResourceparameterId's*/
|
||||
mPixelSize = 8 /*VideosResourceparameterId's*/
|
||||
mCmpCount = 9 /*VideosResourceparameterId's*/
|
||||
mCmpSize = 10 /*VideosResourceparameterId's*/
|
||||
mPlaneBytes = 11 /*VideosResourceparameterId's*/
|
||||
mVertRefRate = 14 /*VideosResourceparameterId's*/
|
||||
mVidParams = 1 /*Videoparameterblockid.*/
|
||||
mTable = 2 /*Offsettothetable.*/
|
||||
mPageCnt = 3 /*Numberofpages*/
|
||||
mDevType = 4 /*DeviceType*/
|
||||
oneBitMode = 128 /*IdofOneBitModeParameterlist.*/
|
||||
twoBitMode = 129 /*IdofTwoBitModeParameterlist.*/
|
||||
fourBitMode = 130 /*IdofFourBitModeParameterlist.*/
|
||||
eightBitMode = 131/*IdofEightBitModeParameterlist.*/
|
||||
sixteenBitMode = 132 /*IdofSixteenBitModeParameterlist.*/
|
||||
thirtyTwoBitMode = 133 /*IdofThirtyTwoBitModeParameterlist.*/
|
||||
firstVidMode = 128 /*Thenew,betterwaytodotheabove.*/
|
||||
secondVidMode = 129 /*QuickDrawonlysupportssixvideo*/
|
||||
thirdVidMode = 130 /*atthistime.*/
|
||||
fourthVidMode = 131
|
||||
fifthVidMode = 132
|
||||
sixthVidMode = 133
|
||||
spGammaDir = 64
|
||||
spVidNamesDir = 65
|
||||
/* kDeclROMtables = FOUR_CHAR_CODE('decl') */
|
||||
/* kDetailedTimingFormat = FOUR_CHAR_CODE('arba') */ /*Timingisadetailedtiming*/
|
||||
kDDCBlockSize = 128
|
||||
kDDCBlockTypeEDID = 0/*EDIDblocktype.*/
|
||||
kDDCForceReadBit = 0 /*ForceanewreadoftheEDID.*/
|
||||
kDDCForceReadMask = (1<<kDDCForceReadBit)/*MaskforkddcForceReadBit.*/
|
||||
timingInvalid_SM_T24 = 8 /*WorkaroundbuginSMThunder24card.*/
|
||||
timingApple_FixedRateLCD = 42 /*Lumpallfixed-rateLCDsintoonecategory.*/
|
||||
timingApple_512x384_60hz = 130 /*512x384(60Hz)Rubiktiming.*/
|
||||
timingApple_560x384_60hz = 135 /*560x384(60Hz)Rubik-560timing.*/
|
||||
timingApple_640x480_67hz = 140 /*640x480(67Hz)HRtiming.*/
|
||||
timingApple_640x400_67hz = 145 /*640x400(67Hz)HR-400timing.*/
|
||||
timingVESA_640x480_60hz = 150 /*640x480(60Hz)VGAtiming.*/
|
||||
timingVESA_640x480_72hz = 152 /*640x480(72Hz)VGAtiming.*/
|
||||
timingVESA_640x480_75hz = 154 /*640x480(75Hz)VGAtiming.*/
|
||||
timingVESA_640x480_85hz = 158 /*640x480(85Hz)VGAtiming.*/
|
||||
timingGTF_640x480_120hz = 159 /*640x480(120Hz)VESAGeneralizedTimingFormula*/
|
||||
timingApple_640x870_75hz = 160 /*640x870(75Hz)FPDtiming.*/
|
||||
timingApple_640x818_75hz = 165 /*640x818(75Hz)FPD-818timing.*/
|
||||
timingApple_832x624_75hz = 170 /*832x624(75Hz)GoldFishtiming.*/
|
||||
timingVESA_800x600_56hz = 180 /*800x600(56Hz)SVGAtiming.*/
|
||||
timingVESA_800x600_60hz = 182 /*800x600(60Hz)SVGAtiming.*/
|
||||
timingVESA_800x600_72hz = 184 /*800x600(72Hz)SVGAtiming.*/
|
||||
timingVESA_800x600_75hz = 186 /*800x600(75Hz)SVGAtiming.*/
|
||||
timingVESA_800x600_85hz = 188 /*800x600(85Hz)SVGAtiming.*/
|
||||
timingVESA_1024x768_60hz = 190 /*1024x768(60Hz)VESA1K-60Hztiming.*/
|
||||
timingVESA_1024x768_70hz = 200 /*1024x768(70Hz)VESA1K-70Hztiming.*/
|
||||
timingVESA_1024x768_75hz = 204 /*1024x768(75Hz)VESA1K-75Hztiming(verysimilarto
|
||||
timingVESA_1024x768_85hz = 208 /*1024x768(85Hz)VESAtiming.*/
|
||||
timingApple_1024x768_75hz = 210 /*1024x768(75Hz)Apple19"RGB.*/
|
||||
timingApple_1152x870_75hz = 220 /*1152x870(75Hz)Apple21"RGB.*/
|
||||
timingAppleNTSC_ST = 230 /*512x384(60Hz,interlaced,non-convolved).*/
|
||||
timingAppleNTSC_FF = 232 /*640x480(60Hz,interlaced,non-convolved).*/
|
||||
timingAppleNTSC_STconv = 234 /*512x384(60Hz,interlaced,convolved).*/
|
||||
timingAppleNTSC_FFconv = 236 /*640x480(60Hz,interlaced,convolved).*/
|
||||
timingApplePAL_ST = 238 /*640x480(50Hz,interlaced,non-convolved).*/
|
||||
timingApplePAL_FF = 240 /*768x576(50Hz,interlaced,non-convolved).*/
|
||||
timingApplePAL_STconv = 242 /*640x480(50Hz,interlaced,convolved).*/
|
||||
timingApplePAL_FFconv = 244 /*768x576(50Hz,interlaced,convolved).*/
|
||||
timingVESA_1280x960_75hz = 250 /*1280x960(75Hz)*/
|
||||
timingVESA_1280x960_60hz = 252 /*1280x960(60Hz)*/
|
||||
timingVESA_1280x960_85hz = 254 /*1280x960(85Hz)*/
|
||||
timingVESA_1280x1024_60hz = 260 /*1280x1024(60Hz)*/
|
||||
timingVESA_1280x1024_75hz = 262 /*1280x1024(75Hz)*/
|
||||
timingVESA_1280x1024_85hz = 268 /*1280x1024(85Hz)*/
|
||||
timingVESA_1600x1200_60hz = 280 /*1600x1200(60Hz)VESAtiming.*/
|
||||
timingVESA_1600x1200_65hz = 282 /*1600x1200(65Hz)VESAtiming.*/
|
||||
timingVESA_1600x1200_70hz = 284 /*1600x1200(70Hz)VESAtiming.*/
|
||||
timingVESA_1600x1200_75hz = 286 /*1600x1200(75Hz)VESAtiming(pixelclockis189.2
|
||||
timingVESA_1600x1200_80hz = 288 /*1600x1200(80Hz)VESAtiming(pixelclockis216>?
|
||||
timingVESA_1600x1200_85hz = 289 /*1600x1200(85Hz)VESAtiming(pixelclockis229.5
|
||||
timingVESA_1792x1344_60hz = 296 /*1792x1344(60Hz)VESAtiming(204.75Mhzdotclock).
|
||||
timingVESA_1792x1344_75hz = 298 /*1792x1344(75Hz)VESAtiming(261.75Mhzdotclock).
|
||||
timingVESA_1856x1392_60hz = 300 /*1856x1392(60Hz)VESAtiming(218.25Mhzdotclock).
|
||||
timingVESA_1856x1392_75hz = 302 /*1856x1392(75Hz)VESAtiming(288Mhzdotclock).
|
||||
timingVESA_1920x1440_60hz = 304 /*1920x1440(60Hz)VESAtiming(234Mhzdotclock).
|
||||
timingVESA_1920x1440_75hz = 306 /*1920x1440(75Hz)VESAtiming(297Mhzdotclock).
|
||||
timingSMPTE240M_60hz = 400 /*60HzV,33.75KHzH,interlacedtiming,16:9aspect,typical
|
||||
timingFilmRate_48hz = 410 /*48HzV,25.20KHzH,non-interlacedtiming,typicalresolutionof
|
||||
timingSony_1600x1024_76hz = 500 /*1600x1024(76Hz)Sonytiming(pixelclockis170.447
|
||||
timingSony_1920x1080_60hz = 510 /*1920x1080(60Hz)Sonytiming(pixelclockis159.84
|
||||
timingSony_1920x1080_72hz = 520 /*1920x1080(72Hz)Sonytiming(pixelclockis216.023
|
||||
timingSony_1920x1200_76hz = 540 /*1900x1200(76Hz)Sonytiming(pixelclockis243.20
|
||||
timingApple_0x0_0hz_Offline = 550/*Indicatesthatthistimingwilltakethedisplayoff-line
|
||||
timingApple12 = timingApple_512x384_60hz
|
||||
timingApple12x = timingApple_560x384_60hz
|
||||
timingApple13 = timingApple_640x480_67hz
|
||||
timingApple13x = timingApple_640x400_67hz
|
||||
timingAppleVGA = timingVESA_640x480_60hz
|
||||
timingApple15 = timingApple_640x870_75hz
|
||||
timingApple15x = timingApple_640x818_75hz
|
||||
timingApple16 = timingApple_832x624_75hz
|
||||
timingAppleSVGA = timingVESA_800x600_56hz
|
||||
timingApple1Ka = timingVESA_1024x768_60hz
|
||||
timingApple1Kb = timingVESA_1024x768_70hz
|
||||
timingApple19 = timingApple_1024x768_75hz
|
||||
timingApple21 = timingApple_1152x870_75hz
|
||||
timingSony_1900x1200_74hz = 530 /*1900x1200(74Hz)Sonytiming(pixelclockis236.25
|
||||
timingSony_1900x1200_76hz = timingSony_1920x1200_76hz/*1900x1200(76Hz)Sonytiming(pixelclockis245.48
|
||||
kAllModesValid = 0 /*Allmodesnottrimmedbyprimaryinitaregood
|
||||
kAllModesSafe = 1 /*Allmodesnottrimmedbyprimaryinitareknow
|
||||
kReportsTagging = 2 /*Candetecttaggeddisplays(toidentifysmartmonitors)*/
|
||||
kHasDirectConnection = 3 /*Trueimpliesthatdrivercantalkdirectlytodevice
|
||||
kUncertainConnection = 5 /*Theremaynotbeadisplay(nosenselines?).
|
||||
kTaggingInfoNonStandard = 6 /*SetwhencsConnectTaggedType/csConnectTaggedDataarenon-standard(i.e.,nottheApple
|
||||
kReportsDDCConnection = 7 /*Cardcandoddc(setkHasDirectConnect&&kHasDDCConnectif
|
||||
kHasDDCConnection = 8 /*Cardhasddcconnectnow.*/
|
||||
kConnectionInactive = 9 /*SetwhentheconnectionisNOTcurrentlyactive(generally
|
||||
kDependentConnection = 10 /*SetwhensomeascpectofTHISconnectiondependson
|
||||
kBuiltInConnection = 11 /*SetwhenconnectionisKNOWNtobebuilt-in(this
|
||||
kOverrideConnection = 12 /*Setwhenthereportedconnectionisnotthetrue
|
||||
kFastCheckForDDC = 13 /*Setwhenall3aretrue:1)sensecodes
|
||||
kReportsHotPlugging = 14/*Detectsandreportshotplugggingonconnector(viaVSL
|
||||
kPanelConnect = 2 /*Forusewithfixed-in-placeLCDpanels.*/
|
||||
kPanelTFTConnect = 2 /*AliasforkPanelConnect*/
|
||||
kFixedModeCRTConnect = 3 /*Forusewithfixed-mode(i.e.,verylimitedrange)displays.
|
||||
kMultiModeCRT1Connect = 4 /*320x200maybe,12"maybe,13"(default),16"certain,19"
|
||||
kMultiModeCRT2Connect = 5 /*320x200maybe,12"maybe,13"certain,16"(default),19"
|
||||
kMultiModeCRT3Connect = 6 /*320x200maybe,12"maybe,13"certain,16"certain,19"
|
||||
kMultiModeCRT4Connect = 7 /*Expansiontolargemultimode(notyetused)*/
|
||||
kModelessConnect = 8 /*Expansiontomodelessmodel(notyetused)*/
|
||||
kFullPageConnect = 9 /*640x818(toget8bppin512Kcase)and640x870
|
||||
kVGAConnect = 10 /*640x480VGAdefault--questioneverythingelse*/
|
||||
kNTSCConnect = 11 /*NTSCST(default),FF,STconv,FFconv*/
|
||||
kPALConnect = 12 /*PALST(default),FF,STconv,FFconv*/
|
||||
kHRConnect = 13 /*Straight-6connect--640x480and640x400(toget8bpp
|
||||
kMonoTwoPageConnect = 15 /*1152x870Applecolortwo-pagedisplay*/
|
||||
kColorTwoPageConnect = 16 /*1152x870AppleB&Wtwo-pagedisplay*/
|
||||
kColor16Connect = 17 /*832x624AppleB&Wtwo-pagedisplay*/
|
||||
kColor19Connect = 18 /*1024x768AppleB&Wtwo-pagedisplay*/
|
||||
kGenericCRT = 19 /*IndicatesnothingexceptthatconnectionisCRTinnature.
|
||||
kGenericLCD = 20 /*IndicatesnothingexceptthatconnectionisLCDinnature.
|
||||
kDDCConnect = 21 /*DDCconnection,alwayssetkHasDDCConnection*/
|
||||
kNoConnect = 22/*Nodisplayisconnected-loadsensingorsimilar
|
||||
kModeValid = 0 /*SaysthatthismodeshouldNOTbetrimmed.*/
|
||||
kModeSafe = 1 /*Thismodedoesnotneedconfirmation*/
|
||||
kModeDefault = 2 /*Thisisthedefaultmodeforthistypeof
|
||||
kModeShowNow = 3 /*Thismodeshouldalwaysbeshown(eventhoughit
|
||||
kModeNotResize = 4 /*Thismodeshouldnotbeusedtoresizethe
|
||||
kModeRequiresPan = 5 /*Thismodehasmorepixelsthanareactuallydisplayed
|
||||
kModeInterlaced = 6 /*Thismodeisinterlaced(singlepixellineslookbad).
|
||||
kModeShowNever = 7 /*Thismodeshouldnotbeshownintheuser
|
||||
kModeSimulscan = 8 /*Indicatesthatmorethanonedisplayconnectioncanbe
|
||||
kModeNotPreset = 9 /*Indicatesthatthetimingisnotafactorypreset
|
||||
kModeBuiltIn = 10 /*Indicatesthatthedisplaymodeisforthebuilt-in
|
||||
kModeStretched = 11/*Indicatesthatthedisplaymodewillbestretched/distortedto
|
||||
kDepthDependent = 0/*Saysthatthisdepthmodemaycausedependentchanges
|
||||
kResolutionHasMultipleDepthSizes = 0/*SaysthatthismodehasdifferentcsHorizontalPixels csVerticalLinesat
|
||||
kAVPowerOff = 0 /*Powerfullyoff*/
|
||||
kAVPowerStandby = 1
|
||||
kAVPowerSuspend = 2
|
||||
kAVPowerOn = 3
|
||||
kHardwareSleep = 128
|
||||
kHardwareWake = 129
|
||||
kHardwareWakeFromSuspend = 130
|
||||
kHardwareWakeToDoze = 131
|
||||
kHardwareWakeToDozeFromSuspend = 132
|
||||
cscReset = 0
|
||||
cscKillIO = 1
|
||||
cscSetMode = 2
|
||||
cscSetEntries = 3
|
||||
cscSetGamma = 4
|
||||
cscGrayPage = 5
|
||||
cscGrayScreen = 5
|
||||
cscSetGray = 6
|
||||
cscSetInterrupt = 7
|
||||
cscDirectSetEntries = 8
|
||||
cscSetDefaultMode = 9
|
||||
cscSwitchMode = 10 /*TakesaVDSwitchInfoPtr*/
|
||||
cscSetSync = 11 /*TakesaVDSyncInfoPtr*/
|
||||
cscSavePreferredConfiguration = 16 /*TakesaVDSwitchInfoPtr*/
|
||||
cscSetHardwareCursor = 22 /*TakesaVDSetHardwareCursorPtr*/
|
||||
cscDrawHardwareCursor = 23 /*TakesaVDDrawHardwareCursorPtr*/
|
||||
cscSetConvolution = 24 /*TakesaVDConvolutionInfoPtr*/
|
||||
cscSetPowerState = 25 /*TakesaVDPowerStatePtr*/
|
||||
cscPrivateControlCall = 26 /*TakesaVDPrivateSelectorDataPtr*/
|
||||
cscSetMultiConnect = 28 /*TakesaVDMultiConnectInfoPtr*/
|
||||
cscSetClutBehavior = 29 /*TakesaVDClutBehavior*/
|
||||
cscSetDetailedTiming = 31 /*TakesaVDDetailedTimingPtr*/
|
||||
cscDoCommunication = 33 /*TakesaVDCommunicationPtr*/
|
||||
cscProbeConnection = 34 /*Takesnilpointer(maygenerateakFBConnectInterruptServiceTypeserviceinterrupt)*/
|
||||
cscUnusedCall = 127/*Thiscallusedtoexpendthescrnresource.Its
|
||||
cscGetMode = 2
|
||||
cscGetEntries = 3
|
||||
cscGetPageCnt = 4
|
||||
cscGetPages = 4 /*ThisiswhatC&D2callsit.*/
|
||||
cscGetPageBase = 5
|
||||
cscGetBaseAddr = 5 /*ThisiswhatC&D2callsit.*/
|
||||
cscGetGray = 6
|
||||
cscGetInterrupt = 7
|
||||
cscGetGamma = 8
|
||||
cscGetDefaultMode = 9
|
||||
cscGetCurMode = 10 /*TakesaVDSwitchInfoPtr*/
|
||||
cscGetSync = 11 /*TakesaVDSyncInfoPtr*/
|
||||
cscGetConnection = 12 /*Returninformationabouttheconnectiontothedisplay*/
|
||||
cscGetModeTiming = 13 /*Returntiminginfoforamode*/
|
||||
cscGetModeBaseAddress = 14 /*Returnbaseaddressinformationaboutaparticularmode*/
|
||||
cscGetScanProc = 15 /*QuickTimescanchasingroutine*/
|
||||
cscGetPreferredConfiguration = 16 /*TakesaVDSwitchInfoPtr*/
|
||||
cscGetNextResolution = 17 /*TakesaVDResolutionInfoPtr*/
|
||||
cscGetVideoParameters = 18 /*TakesaVDVideoParametersInfoPtr*/
|
||||
cscGetGammaInfoList = 20 /*TakesaVDGetGammaListPtr*/
|
||||
cscRetrieveGammaTable = 21 /*TakesaVDRetrieveGammaPtr*/
|
||||
cscSupportsHardwareCursor = 22 /*TakesaVDSupportsHardwareCursorPtr*/
|
||||
cscGetHardwareCursorDrawState = 23 /*TakesaVDHardwareCursorDrawStatePtr*/
|
||||
cscGetConvolution = 24 /*TakesaVDConvolutionInfoPtr*/
|
||||
cscGetPowerState = 25 /*TakesaVDPowerStatePtr*/
|
||||
cscPrivateStatusCall = 26 /*TakesaVDPrivateSelectorDataPtr*/
|
||||
cscGetDDCBlock = 27 /*TakesaVDDDCBlockPtr*/
|
||||
cscGetMultiConnect = 28 /*TakesaVDMultiConnectInfoPtr*/
|
||||
cscGetClutBehavior = 29 /*TakesaVDClutBehaviorPtr*/
|
||||
cscGetTimingRanges = 30 /*TakesaVDDisplayTimingRangePtr*/
|
||||
cscGetDetailedTiming = 31 /*TakesaVDDetailedTimingPtr*/
|
||||
cscGetCommunicationInfo = 32/*TakesaVDCommunicationInfoPtr*/
|
||||
kDisableHorizontalSyncBit = 0
|
||||
kDisableVerticalSyncBit = 1
|
||||
kDisableCompositeSyncBit = 2
|
||||
kEnableSyncOnBlue = 3
|
||||
kEnableSyncOnGreen = 4
|
||||
kEnableSyncOnRed = 5
|
||||
kNoSeparateSyncControlBit = 6
|
||||
kTriStateSyncBit = 7
|
||||
kHorizontalSyncMask = 0x01
|
||||
kVerticalSyncMask = 0x02
|
||||
kCompositeSyncMask = 0x04
|
||||
kDPMSSyncMask = 0x07
|
||||
kTriStateSyncMask = 0x80
|
||||
kSyncOnBlueMask = 0x08
|
||||
kSyncOnGreenMask = 0x10
|
||||
kSyncOnRedMask = 0x20
|
||||
kSyncOnMask = 0x38
|
||||
kDPMSSyncOn = 0
|
||||
kDPMSSyncStandby = 1
|
||||
kDPMSSyncSuspend = 2
|
||||
kDPMSSyncOff = 7
|
||||
kConvolved = 0
|
||||
kLiveVideoPassThru = 1
|
||||
kConvolvedMask = 0x01
|
||||
kLiveVideoPassThruMask = 0x02
|
||||
kRSCZero = 0
|
||||
kRSCOne = 1
|
||||
kRSCTwo = 2
|
||||
kRSCThree = 3
|
||||
kRSCFour = 4
|
||||
kRSCFive = 5
|
||||
kRSCSix = 6
|
||||
kRSCSeven = 7
|
||||
kESCZero21Inch = 0x00 /*21"RGB*/
|
||||
kESCOnePortraitMono = 0x14 /*PortraitMonochrome*/
|
||||
kESCTwo12Inch = 0x21 /*12"RGB*/
|
||||
kESCThree21InchRadius = 0x31 /*21"RGB(Radius)*/
|
||||
kESCThree21InchMonoRadius = 0x34 /*21"Monochrome(Radius)*/
|
||||
kESCThree21InchMono = 0x35 /*21"Monochrome*/
|
||||
kESCFourNTSC = 0x0A /*NTSC*/
|
||||
kESCFivePortrait = 0x1E /*PortraitRGB*/
|
||||
kESCSixMSB1 = 0x03 /*MultiScanBand-1(12"thru1Six")*/
|
||||
kESCSixMSB2 = 0x0B /*MultiScanBand-2(13"thru19")*/
|
||||
kESCSixMSB3 = 0x23 /*MultiScanBand-3(13"thru21")*/
|
||||
kESCSixStandard = 0x2B /*13"/14"RGBor12"Monochrome*/
|
||||
kESCSevenPAL = 0x00 /*PAL*/
|
||||
kESCSevenNTSC = 0x14 /*NTSC*/
|
||||
kESCSevenVGA = 0x17 /*VGA*/
|
||||
kESCSeven16Inch = 0x2D /*16"RGB(GoldFish)*/
|
||||
kESCSevenPALAlternate = 0x30 /*PAL(Alternate)*/
|
||||
kESCSevenDDC = 0x3E /*DDCdisplay*/
|
||||
kESCSevenNoDisplay = 0x3F/*Nodisplayconnected*/
|
||||
kDepthMode1 = 128
|
||||
kDepthMode2 = 129
|
||||
kDepthMode3 = 130
|
||||
kDepthMode4 = 131
|
||||
kDepthMode5 = 132
|
||||
kDepthMode6 = 133
|
||||
kFirstDepthMode = 128 /*Theseconstantsareobsolete,andjustincluded*/
|
||||
kSecondDepthMode = 129 /*forclientsthathaveconvertedtotheabove*/
|
||||
kThirdDepthMode = 130 /*kDepthModeXXXconstants.*/
|
||||
kFourthDepthMode = 131
|
||||
kFifthDepthMode = 132
|
||||
kSixthDepthMode = 133
|
||||
kDisplayModeIDCurrent = 0x00 /*ReferencetheCurrentDisplayModeID*/
|
||||
kDisplayModeIDInvalid = 0xFFFFFFFF /*AbogusDisplayModeIDinallcases*/
|
||||
kDisplayModeIDFindFirstResolution = 0xFFFFFFFE /*UsedincscGetNextResolutiontoresetiterator*/
|
||||
kDisplayModeIDNoMoreResolutions = 0xFFFFFFFD /*UsedincscGetNextResolutiontoindicateEndOfList*/
|
||||
kDisplayModeIDFindFirstProgrammable = 0xFFFFFFFC /*UsedincscGetNextResolutiontofindunusedprogrammabletiming*/
|
||||
kDisplayModeIDBootProgrammable = 0xFFFFFFFB /*ThisistheIDgivenatboottimeby
|
||||
kDisplayModeIDReservedBase = 0x80000000/*Lowest(unsigned)DisplayModeIDreservedbyApple*/
|
||||
kGammaTableIDFindFirst = 0xFFFFFFFE /*GetthefirstgammatableID*/
|
||||
kGammaTableIDNoMoreTables = 0xFFFFFFFD /*Usedtoindicateendoflist*/
|
||||
kGammaTableIDSpecific = 0x00/*Returntheinfoforthegiventableid*/
|
||||
kActivateConnection = (0<<kConnectionInactive) /*Usedforactivatingaconnection(csConnectFlagsvalue).*/
|
||||
kDeactivateConnection = (1<<kConnectionInactive)/*Usedfordeactivatingaconnection(csConnectFlagsvalue.)*/
|
||||
kVideoDefaultBus = 0
|
||||
kVideoBusTypeInvalid = 0
|
||||
kVideoBusTypeI2C = 1
|
||||
kVideoNoTransactionType = 0 /*Notransaction*/
|
||||
kVideoSimpleI2CType = 1 /*SimpleI2Cmessage*/
|
||||
kVideoDDCciReplyType = 2/*DDC/cimessage(withimbeddedlength)*/
|
||||
kVideoReplyMicroSecDelayMask = (1<<0)/*Ifset thedrivershoulddelaycsMinReplyDelay
|
||||
kSyncInterlaceMask = (1<<7)
|
||||
kSyncAnalogCompositeMask = 0
|
||||
kSyncAnalogCompositeSerrateMask = (1<<2)
|
||||
kSyncAnalogCompositeRGBSyncMask = (1<<1)
|
||||
kSyncAnalogBipolarMask = (1<<3)
|
||||
kSyncAnalogBipolarSerrateMask = (1<<2)
|
||||
kSyncAnalogBipolarSRGBSyncMask = (1<<1)
|
||||
kSyncDigitalCompositeMask = (1<<4)
|
||||
kSyncDigitalCompositeSerrateMask = (1<<2)
|
||||
kSyncDigitalCompositeMatchHSyncMask = (1<<2)
|
||||
kSyncDigitalSeperateMask = (1<<4)+(1<<3)
|
||||
kSyncDigitalVSyncPositiveMask = (1<<2)
|
||||
kSyncDigitalHSyncPositiveMask = (1<<1)
|
||||
kDMSModeReady = 0 /*DisplayModeIDisconfiguredandready*/
|
||||
kDMSModeNotReady = 1 /*DisplayModeIDisisbeingprogrammed*/
|
||||
kDMSModeFree = 2/*DisplayModeIDisnotassociatedwithatiming*/
|
||||
kTimingChangeRestrictedErr = -10930
|
||||
kVideoI2CReplyPendingErr = -10931
|
||||
kVideoI2CTransactionErr = -10932
|
||||
kVideoI2CBusyErr = -10933
|
||||
kVideoI2CTransactionTypeErr = -10934
|
||||
kVideoBufferSizeErr = -10935
|
||||
kRangeSupportsSignal_0700_0300_Bit = 0
|
||||
kRangeSupportsSignal_0714_0286_Bit = 1
|
||||
kRangeSupportsSignal_1000_0400_Bit = 2
|
||||
kRangeSupportsSignal_0700_0000_Bit = 3
|
||||
kRangeSupportsSignal_0700_0300_Mask = (1<<kRangeSupportsSignal_0700_0300_Bit)
|
||||
kRangeSupportsSignal_0714_0286_Mask = (1<<kRangeSupportsSignal_0714_0286_Bit)
|
||||
kRangeSupportsSignal_1000_0400_Mask = (1<<kRangeSupportsSignal_1000_0400_Bit)
|
||||
kRangeSupportsSignal_0700_0000_Mask = (1<<kRangeSupportsSignal_0700_0000_Bit)
|
||||
kDigitalSignalBit = 0 /*Donotset.MacOSdoesnotcurrentlysupport
|
||||
kAnalogSetupExpectedBit = 1 /*Analogdisplays-displayexpectsablank-to-blacksetupor
|
||||
kDigitalSignalMask = (1<<kDigitalSignalBit)
|
||||
kAnalogSetupExpectedMask = (1<<kAnalogSetupExpectedBit)
|
||||
kAnalogSignalLevel_0700_0300 = 0
|
||||
kAnalogSignalLevel_0714_0286 = 1
|
||||
kAnalogSignalLevel_1000_0400 = 2
|
||||
kAnalogSignalLevel_0700_0000 = 3
|
||||
kRangeSupportsSeperateSyncsBit = 0
|
||||
kRangeSupportsSyncOnGreenBit = 1
|
||||
kRangeSupportsCompositeSyncBit = 2
|
||||
kRangeSupportsVSyncSerrationBit = 3
|
||||
kRangeSupportsSeperateSyncsMask = (1<<kRangeSupportsSeperateSyncsBit)
|
||||
kRangeSupportsSyncOnGreenMask = (1<<kRangeSupportsSyncOnGreenBit)
|
||||
kRangeSupportsCompositeSyncMask = (1<<kRangeSupportsCompositeSyncBit)
|
||||
kRangeSupportsVSyncSerrationMask = (1<<kRangeSupportsVSyncSerrationBit)
|
||||
kSyncPositivePolarityBit = 0 /*Digitalseparatesyncpolarityforanaloginterfaces(0=>
|
||||
kSyncPositivePolarityMask = (1<<kSyncPositivePolarityBit)
|
||||
kSetClutAtSetEntries = 0 /*SetEntriesbehavioristoupdateclutduringSetEntriescall*/
|
||||
kSetClutAtVBL = 1/*SetEntriesbehavioristoupateclutatnextvbl*/
|
||||
|
168
nubus-to-ztex-gateware/DeclROM/vid_decl_rom.s
Normal file
168
nubus-to-ztex-gateware/DeclROM/vid_decl_rom.s
Normal file
|
@ -0,0 +1,168 @@
|
|||
.include "atrap.inc"
|
||||
.include "globals.inc"
|
||||
.include "declrom.inc"
|
||||
|
||||
.include "ROMDefs.inc"
|
||||
.include "Video.inc"
|
||||
.include "DepVideo.inc"
|
||||
|
||||
sRsrc_Board = 1 /* board sResource (>0 & <128) */
|
||||
sRsrc_VidS8 = 0x80 /* functional sResources */
|
||||
|
||||
_sRsrcDir:
|
||||
OSLstEntry sRsrc_Board,_sRsrc_Board /* board sRsrc List */
|
||||
OSLstEntry sRsrc_VidS8,_sRsrc_VidS8 /* video sRsrc List */
|
||||
.long EndOfList
|
||||
|
||||
_sRsrc_Board:
|
||||
OSLstEntry sRsrcType,_BoardType /* offset to board descriptor */
|
||||
OSLstEntry sRsrcName,_BoardName /* offset to name of board */
|
||||
DatLstEntry boardId,NuBusFPGAID /* board ID # (assigned by DTS) */
|
||||
/* OSLstEntry PrimaryInit,_sPInitRec */ /* offset to PrimaryInit exec blk */
|
||||
OSLstEntry vendorInfo,_VendorInfo /* offset to vendor info record */
|
||||
/* OSLstEntry SecondaryInit,_sSInitRec */ /* offset to SecondaryInit block */
|
||||
.long EndOfList
|
||||
|
||||
_BoardType:
|
||||
.short catBoard /* board sResource */
|
||||
.short typBoard
|
||||
.short 0
|
||||
.short 0
|
||||
|
||||
_BoardName:
|
||||
.String "SBusFPGA Video" /* name of board */
|
||||
|
||||
/* _VidICON ; optional icon, not needed */
|
||||
/* _sVidNameDir ; optional name(s), not needed */
|
||||
|
||||
_sPInitRec:
|
||||
.long _EndsPInitRec-_sPInitRec /* physical block size */
|
||||
/* INCLUDE "NuBusFPGAPrimaryInit.a" /* the header/code */ */
|
||||
ALIGN 2
|
||||
_EndsPInitRec:
|
||||
|
||||
/* _sSInitRec */
|
||||
/* .long _EndsSInitRec-_sSInitRec ; physical block size */
|
||||
/* INCLUDE "NuBusFPGASecondaryInit.a" ; the header/code */
|
||||
/* ALIGN 2 */
|
||||
/* _EndsSInitRec */
|
||||
|
||||
_VendorInfo:
|
||||
OSLstEntry vendorId,_VendorId /* offset to vendor ID */
|
||||
OSLstEntry revLevel,_RevLevel /* offset to revision */
|
||||
OSLstEntry partNum,_PartNum /* offset to part number record */
|
||||
OSLstEntry date,_Date /* offset to ROM build date */
|
||||
.long EndOfList
|
||||
|
||||
_VendorId:
|
||||
.string "Romain Dolbeau" /* vendor ID */
|
||||
_RevLevel:
|
||||
.string "NuBusFPGA V1.0" /* revision level */
|
||||
_PartNum:
|
||||
.string "Part Number" /* part number */
|
||||
_Date:
|
||||
.string "&SysDate" /* date */
|
||||
|
||||
_sRsrc_VidS8:
|
||||
OSLstEntry sRsrcType,_VideoType /* video type descriptor */
|
||||
OSLstEntry sRsrcName,_VideoName /* offset to driver name string */
|
||||
/* OSLstEntry sRsrcDrvrDir,_VidDrvrDir ; offset to driver directory */
|
||||
DatLstEntry sRsrcHWDevId,1 /* hardware device ID */
|
||||
OSLstEntry MinorBaseOS,_MinorBase /* offset to frame buffer array */
|
||||
OSLstEntry MinorLength,_MinorLength /* offset to frame buffer length */
|
||||
OSLstEntry sGammaDir,_GammaDirS /* directory for 640x480 monitor */
|
||||
/* Parameters */
|
||||
OSLstEntry firstVidMode,_EBMs /* offset to EightBitMode parms */
|
||||
.long EndOfList /* end of list */
|
||||
|
||||
_VideoType:
|
||||
.short catDisplay /* <Category> */
|
||||
.short typeVideo /* <Type> */
|
||||
.short drSwApple /* <DrvrSw> */
|
||||
.short DrHwNuBusFPGA /* <DrvrHw> */
|
||||
|
||||
_VideoName:
|
||||
.string "Video_NuBusFPGA" /* video driver name */
|
||||
_MinorBase:
|
||||
.long defMinorBase /* frame buffer offset */
|
||||
_MinorLength:
|
||||
.long defMinorLength /* frame buffer length */
|
||||
|
||||
/* _VidDrvrDir */
|
||||
/* OSLstEntry sMacOS68020,_sMacOS68020 driver directory for Mac OS */
|
||||
/* .long EndOfList */
|
||||
/* */
|
||||
/* _sMacOS68020 */
|
||||
/* .long _End020Drvr- sMacOS68020 ; physical block size */
|
||||
/* INCLUDE 'NuBusFPGADrvr.a' ; driver code */
|
||||
/* _End020Drvr */
|
||||
|
||||
|
||||
_GammaDirS: /* for the 640x480 monitor */
|
||||
OSLstEntry 128,_SmallGamma
|
||||
.long EndOfList
|
||||
|
||||
_SmallGamma:
|
||||
.long _EndSmallGamma-_SmallGamma
|
||||
.short SGammaResID
|
||||
.string "Small Gamma" /* Monitors name */
|
||||
ALIGN 2
|
||||
.short $0000 /* gVersion */
|
||||
.short DrHwNuBusFPGA /* gType */
|
||||
.short $0000 /* gFormulaSize */
|
||||
.short $0001 /* gChanCnt */
|
||||
.short $0100 /* gDataCnt */
|
||||
.short $0008 /* gChanWidth */
|
||||
.long $0005090B,$0E101315,$17191B1D,$1E202224
|
||||
.long $2527282A,$2C2D2F30,$31333436,$37383A3B
|
||||
.long $3C3E3F40,$42434445,$4748494A,$4B4D4E4F
|
||||
.long $50515254,$55565758,$595A5B5C,$5E5F6061
|
||||
.long $62636465,$66676869,$6A6B6C6D,$6E6F7071
|
||||
.long $72737475,$76777879,$7A7B7C7D,$7E7F8081
|
||||
.long $81828384,$85868788,$898A8B8C,$8C8D8E8F
|
||||
.long $90919293,$94959596,$9798999A,$9B9B9C9D
|
||||
.long $9E9FA0A1,$A1A2A3A4,$A5A6A6A7,$A8A9AAAB
|
||||
.long $ABACADAE,$AFB0B0B1,$B2B3B4B4,$B5B6B7B8
|
||||
.long $B8B9BABB,$BCBCBDBE,$BFC0C0C1,$C2C3C3C4
|
||||
.long $C5C6C7C7,$C8C9CACA,$CBCCCDCD,$CECFD0D0
|
||||
.long $D1D2D3D3,$D4D5D6D6,$D7D8D9D9,$DADBDCDC
|
||||
.long $DDDEDFDF,$E0E1E1E2,$E3E4E4E5,$E6E7E7E8
|
||||
.long $E9B9EAEB,$ECECEDEE,$EEEFF0F1,$F1F2F3F3
|
||||
.long $F4F5F5F6,$F7F8F8F9,$FAFAFBFC,$FCFDFEFF
|
||||
_EndSmallGamma:
|
||||
|
||||
_EBMs:
|
||||
OSLstEntry mVidParams,_EBVParms /* offset to vid parameters */
|
||||
DatLstEntry mPageCnt,Pages8s /* number of video pages */
|
||||
DatLstEntry mDevType,defmDevType /* device type */
|
||||
.long EndOfList /* end of list */
|
||||
_EBVParms:
|
||||
.long _EndEBVParms-_EBVParms /* physical block size */
|
||||
.long defmBaseOffset /* QuickDraw base offset ; vpBaseOffset */
|
||||
.short RB8s /* physRowBytes ; vpRowBytes */
|
||||
.short defmBounds_Ts,defmBounds_Ls,defmBounds_Bs,defmBounds_Rs /* vpBounds */
|
||||
.short defVersion /* bmVersion ; vpVersion */
|
||||
.short 0 /* packType not used ; vpPackType */
|
||||
.long 0 /* packSize not used ; vpPackSize */
|
||||
.long defmHRes /* bmHRes */
|
||||
.long defmVRes /* bmVRes */
|
||||
.short ChunkyIndexed /* bmPixelType */
|
||||
.short 8 /* bmPixelSize */
|
||||
.short 1 /* bmCmpCount */
|
||||
.short 8 /* bmCmpSize */
|
||||
.long defmPlaneBytes /* bmPlaneBytes */
|
||||
_EndEBVParms:
|
||||
|
||||
/* Declaration ROM directory at end */
|
||||
DeclROMDir:
|
||||
OSLstEntry 0, _sRsrcDir
|
||||
.long DeclRomEnd-_sRsrcDir /* Length should be 0x824 */
|
||||
DeclROMCRC: .long 0x0 /* TODO: calculate this */
|
||||
.byte 1 /* Revision Level */
|
||||
.byte appleFormat /* Apple Format */
|
||||
.long testPattern /* magic TestPattern */
|
||||
.byte 0 /* reserved */
|
||||
.byte 0x0F /* byte lane marker */
|
||||
DeclRomEnd:
|
||||
.end
|
||||
|
1
nubus-to-ztex-gateware/MakeFile
Executable file
1
nubus-to-ztex-gateware/MakeFile
Executable file
|
@ -0,0 +1 @@
|
|||
# MakeFile - Make instructions for assembly language examples.
#
# Copyright Apple Computer, Inc. 1986-1987,1992, 1998
# All rights reserved.
#
# This makefile builds:
# The sample MPW Tool: Count
# The sample desk accessory: Memory
#
all ÄÄ rom
rom.raw ÄÄ rom.a.o
Link rom.a.o -o rom.raw
rom ÄÄ rom.ck
Data rom.ck rom
rom.ck ÄÄ rom.raw
CRCPatch rom.raw rom.ck
rom.a.o Ä rom.a
Asm rom.a
# 'quadra650hd:MPW-GM:Interfaces&Libraries:Interfaces:AIncludes:'
# 'quadra650hd:Metrowerks:CodeWarrior MPW:Interfaces&Libraries:Interfaces:AIncludes:'
|
13
nubus-to-ztex-gateware/do
Normal file
13
nubus-to-ztex-gateware/do
Normal file
|
@ -0,0 +1,13 @@
|
|||
(
|
||||
source /opt/Xilinx/Vivado/2020.1/settings64.sh
|
||||
export LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2020.1/lib/lnx64.o/SuSE
|
||||
|
||||
python3 nubus_to_fpga_soc.py --build --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.0 --sys-clk-freq 100e6
|
||||
) 2>&1 | tee build_V1_0.log
|
||||
# --trng
|
||||
# --sdram
|
||||
# --sdcard
|
||||
# --usb
|
||||
# --cg3 --cg3-res 1280x1024@60Hz
|
||||
|
||||
grep -A10 'Design Timing Summary' build/ztex213_nubus_V1_0/gateware/ztex213_nubus_V1_0_timing.rpt
|
100
nubus-to-ztex-gateware/nubus-to-ztex-io-signal.xdc
Normal file
100
nubus-to-ztex-gateware/nubus-to-ztex-io-signal.xdc
Normal file
|
@ -0,0 +1,100 @@
|
|||
set_property IOSTANDARD LVTTL [get_ports {nmrq_n}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {start_n}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {arb_n[2]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {arb_n[0]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[31]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[29]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[27]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[25]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[23]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[21]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[18]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[16]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {nubus_oe}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[17]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[12]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[10]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[8]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[6]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[4]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[5]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[3]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[0]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {tm_n[1]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {tm_n[0]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {reset_n}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {rqst_n}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ack_n}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {arb_n[3]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {arb_n[1]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[30]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[28]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[26]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {clk_n}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[24]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[22]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[20]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[19]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[14]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[15]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[13]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[11]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {clk2x_n}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[9]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[7]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {tm_n[2]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[2]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {ad_n[1]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {usbh0_p}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {usbh0_n}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {led[8]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {RX}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {id_n[1]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {id_n[3]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {id_n[2]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {id_n[0]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {i2c0_scl}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {i2c0_sda}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {led[6]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {led[4]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {led[2]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {led[0]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {unused0}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_clk}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_b[7]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_b[6]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_b[5]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_b[4]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_b[3]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_b[2]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_b[1]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_b[0]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_g[7]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_g[6]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_g[4]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_g[5]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {TX}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {sd_d2}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {sd_d3}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {sd_cmd}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {sd_clk}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {sd_d0}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {sd_d1}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {led[7]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {led[5]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {led[3]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {led[1]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_hs}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_vs}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_r[0]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_r[1]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_r[2]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_r[3]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_r[4]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_r[5]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_r[6]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_r[7]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_g[0]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_g[1]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_g[2]}]
|
||||
set_property IOSTANDARD LVTTL [get_ports {vga_g[3]}]
|
144
nubus-to-ztex-gateware/nubus-to-ztex-pin-signal.xdc
Normal file
144
nubus-to-ztex-gateware/nubus-to-ztex-pin-signal.xdc
Normal file
|
@ -0,0 +1,144 @@
|
|||
# !!! Constraint files are application specific !!!
|
||||
# !!! This is a template only !!!
|
||||
|
||||
# on-board signals
|
||||
|
||||
# CLKOUT/FXCLK
|
||||
create_clock -name fxclk_in -period 20.833 [get_ports fxclk_in]
|
||||
set_property PACKAGE_PIN P15 [get_ports fxclk_in]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports fxclk_in]
|
||||
|
||||
# IFCLK
|
||||
#create_clock -name ifclk_in -period 20.833 [get_ports ifclk_in]
|
||||
#set_property PACKAGE_PIN P17 [get_ports ifclk_in]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports ifclk_in]
|
||||
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
||||
|
||||
|
||||
# set_property PACKAGE_PIN [get_ports {}]
|
||||
# set_property IOSTANDARD LVTTL [get_ports {}]
|
||||
|
||||
#### AB
|
||||
# AB TOP LEFT (12)
|
||||
set_property PACKAGE_PIN K16 [get_ports {rqst_n}]
|
||||
set_property PACKAGE_PIN K15 [get_ports {tm0_n}]
|
||||
set_property PACKAGE_PIN J15 [get_ports {start_n}]
|
||||
set_property PACKAGE_PIN H15 [get_ports {grant}] # from CPLD
|
||||
set_property PACKAGE_PIN J14 [get_ports {fpga_to_cpld_signal}] # to CPLD
|
||||
set_property PACKAGE_PIN H17 [get_ports {nubus_master_dir}]
|
||||
set_property PACKAGE_PIN G17 [get_ports {reset_n}]
|
||||
set_property PACKAGE_PIN G18 [get_ports {ad_n[31]}]
|
||||
set_property PACKAGE_PIN F18 [get_ports {ad_n[29]}]
|
||||
set_property PACKAGE_PIN E18 [get_ports {ad_n[27]}]
|
||||
set_property PACKAGE_PIN D18 [get_ports {ad_n[25]}]
|
||||
set_property PACKAGE_PIN G13 [get_ports {nubus_oe}]
|
||||
|
||||
# AB BOTTOM LEFT (13)
|
||||
set_property PACKAGE_PIN F13 [get_ports {ad_n[23]}]
|
||||
set_property PACKAGE_PIN E16 [get_ports {ad_n[21]}]
|
||||
set_property PACKAGE_PIN C17 [get_ports {ad_n[19]}]
|
||||
set_property PACKAGE_PIN A18 [get_ports {ad_n[17]}]
|
||||
set_property PACKAGE_PIN C15 [get_ports {ad_n[15]}]
|
||||
set_property PACKAGE_PIN B17 [get_ports {ad_n[13]}]
|
||||
set_property PACKAGE_PIN C14 [get_ports {ad_n[11]}]
|
||||
set_property PACKAGE_PIN D13 [get_ports {ad_n[9]}]
|
||||
set_property PACKAGE_PIN A16 [get_ports {ad_n[7]}]
|
||||
set_property PACKAGE_PIN B14 [get_ports {ad_n[5]}]
|
||||
set_property PACKAGE_PIN B12 [get_ports {ad_n[3]}]
|
||||
set_property PACKAGE_PIN A14 [get_ports {ad_n[1]}]
|
||||
set_property PACKAGE_PIN B11 [get_ports {usbh0_p}]
|
||||
|
||||
# AB TOP RIGHT (12)
|
||||
set_property PACKAGE_PIN J18 [get_ports {nmrq_n}]
|
||||
set_property PACKAGE_PIN J17 [get_ports {tm1_n}]
|
||||
set_property PACKAGE_PIN K13 [get_ports {ack_n}]
|
||||
set_property PACKAGE_PIN J13 [get_ports {arb}] # from CPLD
|
||||
set_property PACKAGE_PIN H14 [get_ports {fpga_to_cpld_clk}] # to CPLD
|
||||
set_property PACKAGE_PIN G14 [get_ports {fpga_to_cpld_signal_2}] # to CPLD
|
||||
set_property PACKAGE_PIN G16 [get_ports {nubus_ad_dir}]
|
||||
set_property PACKAGE_PIN H16 [get_ports {clk_n}]
|
||||
set_property PACKAGE_PIN F16 [get_ports {ad_n[30]}]
|
||||
set_property PACKAGE_PIN F15 [get_ports {ad_n[28]}]
|
||||
set_property PACKAGE_PIN E17 [get_ports {ad_n[26]}]
|
||||
set_property PACKAGE_PIN D17 [get_ports {ad_n[24]}]
|
||||
|
||||
# AB BOTTOM RIGHT (13)
|
||||
set_property PACKAGE_PIN F14 [get_ports {ad_n[22]}]
|
||||
set_property PACKAGE_PIN E15 [get_ports {ad_n[20]}]
|
||||
set_property PACKAGE_PIN C16 [get_ports {ad_n[18]}]
|
||||
set_property PACKAGE_PIN B18 [get_ports {ad_n[16]}]
|
||||
set_property PACKAGE_PIN D15 [get_ports {ad_n[14]}]
|
||||
set_property PACKAGE_PIN B16 [get_ports {ad_n[12]}]
|
||||
set_property PACKAGE_PIN D14 [get_ports {ad_n[10]}]
|
||||
set_property PACKAGE_PIN D12 [get_ports {ad_n[8]}]
|
||||
set_property PACKAGE_PIN A15 [get_ports {ad_n[6]}]
|
||||
set_property PACKAGE_PIN B13 [get_ports {ad_n[4]}]
|
||||
set_property PACKAGE_PIN C12 [get_ports {ad_n[2]}]
|
||||
set_property PACKAGE_PIN A13 [get_ports {ad_n[0]}]
|
||||
set_property PACKAGE_PIN A11 [get_ports {usbh0_n}]
|
||||
|
||||
#### CD
|
||||
# CD TOP LEFT (13)
|
||||
set_property PACKAGE_PIN U9 [get_ports {RX}]
|
||||
set_property PACKAGE_PIN U8 [get_ports {id_n[3]}]
|
||||
set_property PACKAGE_PIN U7 [get_ports {id_n[0]}]
|
||||
set_property PACKAGE_PIN U6 [get_ports {tmoen}] # to CPLD
|
||||
set_property PACKAGE_PIN T8 [get_ports {hdmi_hpd_a}]
|
||||
set_property PACKAGE_PIN R8 [get_ports {hdmi_sda_a}]
|
||||
set_property PACKAGE_PIN R7 [get_ports {hdmi_scl_a}]
|
||||
set_property PACKAGE_PIN T6 [get_ports {hdmi_cec_a}]
|
||||
set_property PACKAGE_PIN R6 [get_ports {hdmi_clk_p}]
|
||||
set_property PACKAGE_PIN R5 [get_ports {hdmi_clk_n}]
|
||||
set_property PACKAGE_PIN V2 [get_ports {hdmi_d1_n}]
|
||||
set_property PACKAGE_PIN U2 [get_ports {hdmi_d1_p}]
|
||||
set_property PACKAGE_PIN K6 [get_ports {vga_clk}]
|
||||
|
||||
# CD BOTTOM LEFT (12)
|
||||
set_property PACKAGE_PIN N6 [get_ports {vga_b[7]}]
|
||||
set_property PACKAGE_PIN M6 [get_ports {vga_b[6]}]
|
||||
set_property PACKAGE_PIN L6 [get_ports {vga_b[5]}]
|
||||
set_property PACKAGE_PIN L5 [get_ports {vga_b[4]}]
|
||||
set_property PACKAGE_PIN N4 [get_ports {vga_b[3]}]
|
||||
set_property PACKAGE_PIN M4 [get_ports {vga_b[2]}]
|
||||
set_property PACKAGE_PIN M3 [get_ports {vga_b[1]}]
|
||||
set_property PACKAGE_PIN M2 [get_ports {vga_b[0]}]
|
||||
set_property PACKAGE_PIN K5 [get_ports {vga_g[7]}]
|
||||
set_property PACKAGE_PIN L4 [get_ports {vga_g[6]}]
|
||||
set_property PACKAGE_PIN L3 [get_ports {vga_g[5]}]
|
||||
set_property PACKAGE_PIN K3 [get_ports {vga_g[4]}]
|
||||
|
||||
# CD TOP RIGHT (13)
|
||||
set_property PACKAGE_PIN V9 [get_ports {TX}]
|
||||
set_property PACKAGE_PIN V7 [get_ports {id_n[2]}]
|
||||
set_property PACKAGE_PIN V6 [get_ports {id_n[1]}]
|
||||
set_property PACKAGE_PIN V5 [get_ports {led[0]}]
|
||||
set_property PACKAGE_PIN V4 [get_ports {led[1]}]
|
||||
set_property PACKAGE_PIN T5 [get_ports {led[2]}]
|
||||
set_property PACKAGE_PIN T4 [get_ports {led[3]}]
|
||||
set_property PACKAGE_PIN U4 [get_ports {vga_hs}]
|
||||
set_property PACKAGE_PIN U3 [get_ports {vga_vs}]
|
||||
set_property PACKAGE_PIN V1 [get_ports {hdmi_d0_n}]
|
||||
set_property PACKAGE_PIN U1 [get_ports {hdmi_d0_p}]
|
||||
set_property PACKAGE_PIN T3 [get_ports {hdmi_d2_n}]
|
||||
set_property PACKAGE_PIN R3 [get_ports {hdmi_d2_p}]
|
||||
|
||||
# CD BOTTOM RIGHT (12)
|
||||
set_property PACKAGE_PIN P5 [get_ports {vga_r[0]}]
|
||||
set_property PACKAGE_PIN N5 [get_ports {vga_r[1]}]
|
||||
set_property PACKAGE_PIN P4 [get_ports {vga_r[2]}]
|
||||
set_property PACKAGE_PIN P3 [get_ports {vga_r[3]}]
|
||||
set_property PACKAGE_PIN T1 [get_ports {vga_r[4]}]
|
||||
set_property PACKAGE_PIN R1 [get_ports {vga_r[5]}]
|
||||
set_property PACKAGE_PIN R2 [get_ports {vga_r[6]}]
|
||||
set_property PACKAGE_PIN P2 [get_ports {vga_r[7]}]
|
||||
set_property PACKAGE_PIN N2 [get_ports {vga_g[0]}]
|
||||
set_property PACKAGE_PIN N1 [get_ports {vga_g[1]}]
|
||||
set_property PACKAGE_PIN M1 [get_ports {vga_g[2]}]
|
||||
set_property PACKAGE_PIN L1 [get_ports {vga_g[3]}]
|
||||
|
103
nubus-to-ztex-gateware/nubus.py
Normal file
103
nubus-to-ztex-gateware/nubus.py
Normal file
|
@ -0,0 +1,103 @@
|
|||
from migen import *
|
||||
from migen.genlib.fifo import *
|
||||
|
||||
import litex
|
||||
|
||||
class NuBus(Module):
|
||||
def __init__(self, platform, cd_nubus="nubus"):
|
||||
# unused & unconnected
|
||||
# self.nubus_pwf_n = Signal(reset = 1)
|
||||
# self.nubus_sp_n = Signal(reset = 1)
|
||||
# self.nubus_spv_n = Signal(reset = 1)
|
||||
# self.nubus_tm2_n = platform.request("nubus_tm2_n"),
|
||||
|
||||
# memory
|
||||
self.mem_valid = Signal()
|
||||
self.mem_addr = Signal(32)
|
||||
self.mem_wdata = Signal(32)
|
||||
self.mem_write = Signal(4)
|
||||
self.mem_ready = Signal()
|
||||
self.mem_rdata = Signal(32)
|
||||
self.mem_error = Signal()
|
||||
self.mem_tryagain = Signal()
|
||||
|
||||
# cpu
|
||||
#self.cpu_valid = Signal(reset = 0)
|
||||
#self.cpu_addr = Signal(32)
|
||||
#self.cpu_wdata = Signal(32)
|
||||
#self.cpu_ready = Signal()
|
||||
#self.cpu_write = Signal(4)
|
||||
#self.cpu_rdata = Signal(32)
|
||||
#self.cpu_lock = Signal()
|
||||
#self.cpu_eclr = Signal()
|
||||
#self.cpu_errors = Signal(4)
|
||||
|
||||
# utilities
|
||||
self.tmoen = Signal()
|
||||
self.mem_stdslot = Signal()
|
||||
self.mem_super = Signal()
|
||||
self.mem_local = Signal()
|
||||
|
||||
self.add_sources(platform)
|
||||
|
||||
#fixme: parameters
|
||||
self.specials += Instance(self.get_netlist_name(),
|
||||
# master side
|
||||
#p_SIMPLE_MAP = 0x0,
|
||||
p_SLOTS_ADDRESS = 0xf,
|
||||
p_SUPERSLOTS_ADDRESS = 0x9,
|
||||
p_WDT_W = 0x8,
|
||||
p_LOCAL_SPACE_EXPOSED_TO_NUBUS = 0,
|
||||
p_NON_ECC_PARITY = 0,
|
||||
i_nub_clkn = ClockSignal(cd_nubus),
|
||||
i_nub_resetn = ~ResetSignal(cd_nubus),
|
||||
i_nub_idn = platform.request("id_3v3_n"),
|
||||
# io_nub_pfwn = self.nubus_pwf_n,
|
||||
io_nub_adn = platform.request("ad_3v3_n"),
|
||||
io_nub_tm0n = platform.request("tm0_3v3_n"),
|
||||
io_nub_tm1n = platform.request("tm1_3v3_n"),
|
||||
io_nub_startn = platform.request("start_3v3_n"),
|
||||
io_nub_rqstn = platform.request("rqst_3v3_n"),
|
||||
io_nub_ackn = platform.request("ack_3v3_n"),
|
||||
# io_nub_arbn = platform.request("nubus_arb_n"),
|
||||
o_arb = platform.request("arb"),
|
||||
i_grant = platform.request("grant"),
|
||||
o_tmoen = platform.request("tmoen"),
|
||||
o_NUBUS_AD_DIR = platform.request("nubus_ad_dir"),
|
||||
io_nub_nmrqn = platform.request("nmrq_3v3_n"),
|
||||
# io_nub_spn = self.nubus_sp_n,
|
||||
# io_nub_spvn = self.nubus_spv_n,
|
||||
o_mem_valid = self.mem_valid,
|
||||
o_mem_addr = self.mem_addr,
|
||||
o_mem_wdata = self.mem_wdata,
|
||||
o_mem_write = self.mem_write,
|
||||
i_mem_ready = self.mem_ready,
|
||||
i_mem_rdata = self.mem_rdata,
|
||||
i_mem_error = self.mem_error,
|
||||
i_mem_tryagain = self.mem_tryagain,
|
||||
#i_cpu_valid = self.cpu_valid,
|
||||
#i_cpu_addr = self.cpu_addr,
|
||||
#i_cpu_wdata = self.cpu_wdata,
|
||||
#o_cpu_ready = self.cpu_ready,
|
||||
#i_cpu_write = self.cpu_write,
|
||||
#o_cpu_rdata = self.cpu_rdata,
|
||||
#i_cpu_lock = self.cpu_lock,
|
||||
#i_cpu_eclr = self.cpu_eclr,
|
||||
#o_cpu_errors = self.cpu_errors,
|
||||
o_mem_stdslot = self.mem_stdslot,
|
||||
o_mem_super = self.mem_super,
|
||||
o_mem_local = self.mem_local)
|
||||
|
||||
def get_netlist_name(self):
|
||||
return "nubus"
|
||||
|
||||
def add_sources(self, platform):
|
||||
platform.add_source("nubus.v", "verilog")
|
||||
platform.add_source("/home/dolbeau/XiBus/nubus.svh", "verilog")
|
||||
#platform.add_source("/home/dolbeau/XiBus/nubus_arbiter.v", "verilog")
|
||||
#platform.add_source("/home/dolbeau/XiBus/nubus_cpubus.v", "verilog")
|
||||
platform.add_source("/home/dolbeau/XiBus/nubus_driver.v", "verilog")
|
||||
#platform.add_source("/home/dolbeau/XiBus/nubus_errors.v", "verilog")
|
||||
platform.add_source("/home/dolbeau/XiBus/nubus_membus.v", "verilog")
|
||||
#platform.add_source("/home/dolbeau/XiBus/nubus_master.v", "verilog")
|
||||
platform.add_source("/home/dolbeau/XiBus/nubus_slave.v", "verilog")
|
203
nubus-to-ztex-gateware/nubus.v
Normal file
203
nubus-to-ztex-gateware/nubus.v
Normal file
|
@ -0,0 +1,203 @@
|
|||
/*
|
||||
* NuBus controller
|
||||
*
|
||||
* Autor: Valeriya Pudova (hww.github.io)
|
||||
*/
|
||||
|
||||
module nubus
|
||||
#(
|
||||
// All slots area starts with addrss $FXXX XXXX
|
||||
parameter SLOTS_ADDRESS = 'hF,
|
||||
// All superslots starts at $9000 0000
|
||||
parameter SUPERSLOTS_ADDRESS = 'h9,
|
||||
// Watch dog timer bits. Master controller will terminate transfer
|
||||
// after (2 ^ WDT_W) clocks
|
||||
parameter WDT_W = 8,
|
||||
// Local space of card start and end addres. For example 0-5
|
||||
// makes local space address $00000000-$50000000
|
||||
parameter LOCAL_SPACE_EXPOSED_TO_NUBUS = 0,
|
||||
parameter LOCAL_SPACE_START = 0,
|
||||
parameter LOCAL_SPACE_END = 5,
|
||||
// Generate parity without ECC memory
|
||||
parameter NON_ECC_PARITY = 0
|
||||
)
|
||||
|
||||
(
|
||||
/* NuBus signals */
|
||||
|
||||
input nub_clkn, // Clock (rising is driving edge, faling is sampling)
|
||||
input nub_resetn, // Reset
|
||||
input [ 3:0] nub_idn, // Slot Identificatjon
|
||||
|
||||
// inout nub_pfwn, // Power Fail Warning
|
||||
inout [31:0] nub_adn, // Address/Data
|
||||
inout nub_tm0n, // Transfer Mode
|
||||
inout nub_tm1n, // Transfer Mode
|
||||
inout nub_startn, // Start
|
||||
inout nub_rqstn, // Request
|
||||
inout nub_ackn, // Acknowledge
|
||||
// inout [ 3:0] nub_arbn, // Arbitration
|
||||
output arb,
|
||||
input grant,
|
||||
output tmoen,
|
||||
output NUBUS_AD_DIR,
|
||||
|
||||
inout nub_nmrqn, // Non-Master Request
|
||||
// inout nub_spn, // System Parity
|
||||
// inout nub_spvn, // System Parity Valid
|
||||
|
||||
/* Memory bus signals connected to a memory, accesible by nubus or processor */
|
||||
|
||||
output mem_valid,
|
||||
output [31:0] mem_addr,
|
||||
output [31:0] mem_wdata,
|
||||
output [ 3:0] mem_write,
|
||||
input mem_ready,
|
||||
input [31:0] mem_rdata,
|
||||
input mem_error,
|
||||
input mem_tryagain,
|
||||
|
||||
// Access to slot area
|
||||
output mem_stdslot,
|
||||
// Access to superslot area ($sXXXXXXX where <s> is card id)
|
||||
output mem_super,
|
||||
// Access to local memory on the card
|
||||
output mem_local
|
||||
);
|
||||
|
||||
`include "nubus.svh"
|
||||
|
||||
// ==========================================================================
|
||||
// Colock and reset
|
||||
// ==========================================================================
|
||||
|
||||
wire nub_clk = ~nub_clkn;
|
||||
wire nub_reset = ~nub_resetn;
|
||||
|
||||
// ==========================================================================
|
||||
// Global signals
|
||||
// ==========================================================================
|
||||
|
||||
wire slv_master, slv_slave, slv_tm1n, slv_tm0n, slv_ackcyn, slv_myslotcy;
|
||||
wire unsigned [31:0] slv_addr;
|
||||
wire drv_tmoen, drv_mstdn;
|
||||
|
||||
wire mst_timeout;
|
||||
|
||||
// ==========================================================================
|
||||
// Drive NuBus address-data line
|
||||
// ==========================================================================
|
||||
|
||||
// Select nubus data signals
|
||||
wire [31:0] nub_ad = mem_rdata;
|
||||
|
||||
// When 1 - drive the NuBus AD lines
|
||||
wire nub_adoe = slv_slave & slv_tm1n
|
||||
/*SLAVE read of card*/
|
||||
;
|
||||
// Output to nubus the
|
||||
assign nub_adn = nub_adoe ? ~nub_ad : 'bZ;
|
||||
|
||||
assign mem_valid = slv_myslotcy;
|
||||
|
||||
assign NUBUS_AD_DIR = ~nub_adoe;
|
||||
|
||||
// ==========================================================================
|
||||
// Parity checking
|
||||
// ==========================================================================
|
||||
|
||||
//wire parity = ~^nub_adn;
|
||||
//wire nub_noparity = NON_ECC_PARITY & ~nub_adoe & ~nub_spvn & nub_spn == parity;
|
||||
|
||||
//assign nub_spn = NON_ECC_PARITY & nub_adoe ? parity : 'bZ;
|
||||
//assign nub_spvn = NON_ECC_PARITY & nub_adoe ? 0 : 'bZ;
|
||||
|
||||
// ==========================================================================
|
||||
// Slave FSM
|
||||
// ==========================================================================
|
||||
|
||||
nubus_slave
|
||||
#(
|
||||
.SLOTS_ADDRESS (SLOTS_ADDRESS),
|
||||
.SUPERSLOTS_ADDRESS(SUPERSLOTS_ADDRESS),
|
||||
.SIMPLE_MAP(0),
|
||||
.LOCAL_SPACE_EXPOSED_TO_NUBUS(LOCAL_SPACE_EXPOSED_TO_NUBUS),
|
||||
.LOCAL_SPACE_START(LOCAL_SPACE_START),
|
||||
.LOCAL_SPACE_END(LOCAL_SPACE_END)
|
||||
|
||||
)
|
||||
USlave
|
||||
(
|
||||
.nub_clkn(nub_clkn), // Clock
|
||||
.nub_resetn(nub_resetn), // Reset
|
||||
.nub_idn(nub_idn), // Card ID
|
||||
.nub_adn(nub_adn), // Address Data
|
||||
.nub_startn(nub_startn), // Transfer start
|
||||
.nub_ackn(nub_ackn), // Transfer end
|
||||
.nub_tm1n(nub_tm1n), // Transition mode 1 (Read/Write)
|
||||
.nub_tm0n(nub_tm0n),
|
||||
.mem_ready(mem_ready),
|
||||
.mst_timeout(0),
|
||||
|
||||
.slv_slave_o(slv_slave), // Slave mode
|
||||
.slv_tm1n_o(slv_tm1n), // Latched transition mode 1 (Read/Write)
|
||||
.slv_tm0n_o(slv_tm0n),
|
||||
.slv_ackcyn_o(slv_ackcyn), // Acknowlege
|
||||
.slv_addr_o(slv_addr), // Slave address
|
||||
.slv_stdslot_o(mem_stdslot), // Starndard slot
|
||||
.slv_super_o(mem_super), // Superslot
|
||||
.slv_local_o(mem_local), // Local area
|
||||
.slv_myslotcy_o(slv_myslotcy) // Any slot
|
||||
);
|
||||
|
||||
// ==========================================================================
|
||||
// Driver Nubus
|
||||
// ==========================================================================
|
||||
|
||||
assign tmoen = drv_tmoen;
|
||||
|
||||
nubus_driver UNDriver
|
||||
(
|
||||
.slv_ackcyn(slv_ackcyn), // Achnowlege
|
||||
.mst_arbcyn(1), // Arbiter enabled
|
||||
.mst_adrcyn(1), // Address strobe
|
||||
.mst_dtacyn(1), // Data strobe
|
||||
.mst_ownern(1), // Master is owner of the bus
|
||||
.mst_lockedn(1), // Locked or not transfer
|
||||
.mst_tm1n(1), // Address ines
|
||||
.mst_tm0n(1), // Address ines
|
||||
.mst_timeout(0),
|
||||
.mis_errorn(TMN_COMPLETE),
|
||||
.nub_tm0n_o(nub_tm0n), // Transfer mode
|
||||
.nub_tm1n_o(nub_tm1n), // Transfer mode
|
||||
.nub_ackn_o(nub_ackn), // Achnowlege
|
||||
.nub_startn_o(nub_startn), // Transfer start
|
||||
.nub_rqstn_o(nub_rqstn), // Bus request
|
||||
.nub_rqstoen_o(nub_qstoen), // Bus request enable
|
||||
.drv_tmoen_o(drv_tmoen), // Transfer mode enable
|
||||
.drv_mstdn_o(drv_mstdn) // Guess: Slave sends /ACK. Master responds with /MSTDN, which allows slave to clear /ACK and listen for next transaction.
|
||||
);
|
||||
|
||||
// ==========================================================================
|
||||
// Memory Interface
|
||||
// ==========================================================================
|
||||
|
||||
nubus_membus UMemBus
|
||||
(
|
||||
.nub_clkn(nub_clkn), // Clock
|
||||
.nub_resetn(nub_resetn), // Reset
|
||||
.nub_adn(nub_adn),
|
||||
|
||||
.slv_tm1n(slv_tm1n),
|
||||
.slv_tm0n(slv_tm0n),
|
||||
.slv_myslotcy(slv_myslotcy),
|
||||
.slv_addr(slv_addr),
|
||||
|
||||
.mem_addr_o(mem_addr),
|
||||
.mem_write_o(mem_write),
|
||||
.mem_wdata_o(mem_wdata)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
42
nubus-to-ztex-gateware/nubus_cpld.ucf
Normal file
42
nubus-to-ztex-gateware/nubus_cpld.ucf
Normal file
|
@ -0,0 +1,42 @@
|
|||
|
||||
NET "fpga_to_cpld_clk" LOC = "S:PIN1";
|
||||
NET "tmoen" LOC = "S:PIN23";
|
||||
NET "fpga_to_cpld_signal" LOC = "S:PIN39";
|
||||
NET "fpga_to_cpld_signal_2" LOC = "S:PIN40";
|
||||
|
||||
NET "rqst_n_5v" LOC = "S:PIN43";
|
||||
NET "rqst_n_3v3" LOC = "S:PIN36";
|
||||
|
||||
#PINLOCK_BEGIN
|
||||
|
||||
#Fri Dec 17 09:49:34 2021
|
||||
|
||||
NET "arb" LOC = "S:PIN28";
|
||||
NET "clk_n_5v" LOC = "S:PIN44";
|
||||
NET "id_n_5v<0>" LOC = "S:PIN5";
|
||||
NET "id_n_5v<1>" LOC = "S:PIN6";
|
||||
NET "id_n_5v<2>" LOC = "S:PIN7";
|
||||
NET "id_n_5v<3>" LOC = "S:PIN8";
|
||||
NET "nubus_master_dir" LOC = "S:PIN22";
|
||||
NET "nubus_oe" LOC = "S:PIN19";
|
||||
NET "reset_n_5v" LOC = "S:PIN18";
|
||||
NET "arb_n_5v<3>" LOC = "S:PIN16";
|
||||
NET "arb_n_5v<2>" LOC = "S:PIN14";
|
||||
NET "arb_n_5v<1>" LOC = "S:PIN13";
|
||||
NET "arb_n_5v<0>" LOC = "S:PIN12";
|
||||
NET "ack_n_3v3" LOC = "S:PIN42";
|
||||
NET "ack_n_5v" LOC = "S:PIN3";
|
||||
NET "clk_n_3v3" LOC = "S:PIN20";
|
||||
NET "grant" LOC = "S:PIN27";
|
||||
NET "id_n_3v3<0>" LOC = "S:PIN29";
|
||||
NET "id_n_3v3<1>" LOC = "S:PIN30";
|
||||
NET "id_n_3v3<2>" LOC = "S:PIN31";
|
||||
NET "id_n_3v3<3>" LOC = "S:PIN32";
|
||||
NET "reset_n_3v3" LOC = "S:PIN21";
|
||||
NET "start_n_3v3" LOC = "S:PIN41";
|
||||
NET "start_n_5v" LOC = "S:PIN2";
|
||||
NET "tm0_n_3v3" LOC = "S:PIN33";
|
||||
NET "tm0_n_5v" LOC = "S:PIN37";
|
||||
NET "tm1_n_3v3" LOC = "S:PIN34";
|
||||
NET "tm1_n_5v" LOC = "S:PIN38";
|
||||
#PINLOCK_END
|
57
nubus-to-ztex-gateware/nubus_cpld.v
Normal file
57
nubus-to-ztex-gateware/nubus_cpld.v
Normal file
|
@ -0,0 +1,57 @@
|
|||
module nubus_cpld
|
||||
(
|
||||
input fpga_to_cpld_clk, // unused (extra line from FPGA to CPLD, pin is a clk input)
|
||||
input fpga_to_cpld_signal, // unused (extra line from FPGA to CPLD)
|
||||
input fpga_to_cpld_signal_2, // unused (extra line from FPGA to CPLD)
|
||||
input tmoen,
|
||||
input [3:0] id_n_5v, // ID of this card
|
||||
inout [3:0] arb_n_5v, // NuBus arbiter's lines
|
||||
input arb, // enable arbitter
|
||||
output grant, // Grant access
|
||||
input reset_n_5v, // reset from NuBus, forwarded
|
||||
input nubus_oe, // disable all 5v drivers
|
||||
output reset_n_3v3, // nubus reset to FPGA
|
||||
input nubus_master_dir, // direction of signals, i.e. are we in master mode
|
||||
output clk_n_3v3, // nubus clk to FPGA
|
||||
output [3:0] id_n_3v3, // nubus ID of this card to FPGA
|
||||
inout tm0_n_3v3, // nubus tm0 to/from FPGA
|
||||
inout tm1_n_3v3, // nubus tm1 to/from FPGA
|
||||
inout tm0_n_5v, // tm0 from/to NuBus
|
||||
inout tm1_n_5v, // tm1 from/to NuBus
|
||||
input clk_n_5v, // clk from NuBus
|
||||
inout start_n_3v3, // start to/from FPGA
|
||||
inout ack_n_3v3, // ack from/to FPGA
|
||||
inout start_n_5v, // start from/to NuBus
|
||||
inout ack_n_5v, // ack to/from NuBus
|
||||
inout rqst_n_5v,
|
||||
inout rqst_n_3v3
|
||||
);
|
||||
|
||||
// clock and pure in -> out pass_through are always on
|
||||
assign clk_n_3v3 = clk_n_5v;
|
||||
assign id_n_3v3 = id_n_5v;
|
||||
assign reset_n_3v3 = reset_n_5v;
|
||||
|
||||
// nubus_master_dir-controlled signals, Z when nubus_oe is off
|
||||
assign start_n_5v = nubus_oe ? 'bZ : ( nubus_master_dir ? start_n_3v3 : 'bZ); // master out
|
||||
assign start_n_3v3 = nubus_oe ? 'bZ : (~nubus_master_dir ? start_n_5v : 'bZ); // master in
|
||||
|
||||
assign rqst_n_5v = nubus_oe ? 'bZ : ( nubus_master_dir ? rqst_n_3v3 : 'bZ); // master out
|
||||
assign rqst_n_3v3 = nubus_oe ? 'bZ : (~nubus_master_dir ? rqst_n_5v : 'bZ); // master in
|
||||
|
||||
assign ack_n_5v = nubus_oe ? 'bZ : ((nubus_master_dir ^ ~tmoen) ? ack_n_3v3 : 'bZ); // slave out/in
|
||||
assign tm0_n_5v = nubus_oe ? 'bZ : ((nubus_master_dir ^ ~tmoen) ? tm0_n_3v3 : 'bZ); // slave out/in
|
||||
assign tm1_n_5v = nubus_oe ? 'bZ : ((nubus_master_dir ^ ~tmoen) ? tm1_n_3v3 : 'bZ); // slave out/in
|
||||
assign ack_n_3v3 = nubus_oe ? 'bZ : ((nubus_master_dir ^ tmoen) ? ack_n_5v : 'bZ); // slave out/in
|
||||
assign tm0_n_3v3 = nubus_oe ? 'bZ : ((nubus_master_dir ^ tmoen) ? tm0_n_5v : 'bZ); // slave in/out
|
||||
assign tm1_n_3v3 = nubus_oe ? 'bZ : ((nubus_master_dir ^ tmoen) ? tm1_n_5v : 'bZ); // slave in/out
|
||||
|
||||
nubus_arbiter UArbiter
|
||||
(
|
||||
.idn(id_n_5v),
|
||||
.arbn(arb_n_5v),
|
||||
.arbcyn(arb),
|
||||
.grant(grant)
|
||||
);
|
||||
|
||||
endmodule // nubus_cpld
|
34
nubus-to-ztex-gateware/nubus_mem_wb.py
Normal file
34
nubus-to-ztex-gateware/nubus_mem_wb.py
Normal file
|
@ -0,0 +1,34 @@
|
|||
from migen import *
|
||||
from migen.genlib.fifo import *
|
||||
|
||||
import litex
|
||||
from litex.soc.interconnect import wishbone
|
||||
|
||||
from migen.genlib.cdc import BusSynchronizer
|
||||
|
||||
class NuBus2Wishbone(Module):
|
||||
"""Wishbone Clock Domain Crossing [Master]"""
|
||||
def __init__(self, nubus, wb):
|
||||
|
||||
# memory
|
||||
# nubus.mem_valid
|
||||
# nubus.mem_addr
|
||||
# nubus.mem_wdata
|
||||
# nubus.mem_write
|
||||
# nubus.mem_ready
|
||||
# nubus.mem_rdata
|
||||
#nubus.mem_error
|
||||
#nubus.mem_tryagain
|
||||
|
||||
self.comb += wb.cyc.eq(nubus.mem_valid)
|
||||
self.comb += wb.stb.eq(nubus.mem_valid)
|
||||
self.comb += If(nubus.mem_write == 0,
|
||||
wb.sel.eq(0xF)).Else(
|
||||
wb.sel.eq(nubus.mem_write))
|
||||
self.comb += wb.we.eq(nubus.mem_write != 0)
|
||||
self.comb += wb.adr.eq(Cat(nubus.mem_addr[2:24], Signal(8, reset = 0))) # 24 bits, a.k.a 22 bits of words
|
||||
self.comb += wb.dat_w.eq(nubus.mem_wdata)
|
||||
self.comb += nubus.mem_rdata.eq(wb.dat_r)
|
||||
self.comb += nubus.mem_ready.eq(wb.ack)
|
||||
self.comb += nubus.mem_error.eq(0)
|
||||
self.comb += nubus.mem_tryagain.eq(0)
|
330
nubus-to-ztex-gateware/nubus_to_fpga_soc.py
Normal file
330
nubus-to-ztex-gateware/nubus_to_fpga_soc.py
Normal file
|
@ -0,0 +1,330 @@
|
|||
import os
|
||||
import argparse
|
||||
from migen import *
|
||||
from migen.genlib.fifo import *
|
||||
from migen.fhdl.specials import Tristate
|
||||
|
||||
import litex
|
||||
from litex.build.generic_platform import *
|
||||
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
|
||||
from litex.soc.integration.soc import *
|
||||
from litex.soc.integration.soc_core import *
|
||||
from litex.soc.integration.builder import *
|
||||
from litex.soc.interconnect import wishbone
|
||||
from litex.soc.cores.clock import *
|
||||
from litex.soc.cores.led import LedChaser
|
||||
import ztex213_nubus
|
||||
|
||||
import nubus
|
||||
|
||||
from litedram.modules import MT41J128M16
|
||||
from litedram.phy import s7ddrphy
|
||||
|
||||
from litedram.frontend.dma import *
|
||||
|
||||
from migen.genlib.cdc import BusSynchronizer
|
||||
from migen.genlib.resetsync import AsyncResetSynchronizer
|
||||
|
||||
from litex.soc.cores.video import VideoVGAPHY
|
||||
import cg3_fb
|
||||
|
||||
# Wishbone stuff
|
||||
from sbus_wb import WishboneDomainCrossingMaster
|
||||
from nubus_mem_wb import NuBus2Wishbone
|
||||
|
||||
# CRG ----------------------------------------------------------------------------------------------
|
||||
|
||||
class _CRG(Module):
|
||||
def __init__(self, platform, sys_clk_freq,
|
||||
cg3=False,
|
||||
hdmi=False,
|
||||
pix_clk=0):
|
||||
self.clock_domains.cd_sys = ClockDomain() # 100 MHz PLL, reset'ed by NuBus (via pll), SoC/Wishbone main clock
|
||||
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
|
||||
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
|
||||
self.clock_domains.cd_idelay = ClockDomain()
|
||||
self.clock_domains.cd_native = ClockDomain(reset_less=True) # 48MHz native, non-reset'ed (for power-on long delay, never reset, we don't want the delay after a warm reset)
|
||||
self.clock_domains.cd_nubus = ClockDomain() # 10 MHz NuBus, reset'ed by NuBus, native NuBus clock domain (25% duty cycle)
|
||||
self.clock_domains.cd_nubus90 = ClockDomain() # 20 MHz NuBus90, reset'ed by NuBus, native NuBus90 clock domain (25% duty cycle)
|
||||
if (cg3):
|
||||
if (not hdmi):
|
||||
self.clock_domains.cd_vga = ClockDomain(reset_less=True)
|
||||
else:
|
||||
self.clock_domains.cd_hdmi = ClockDomain()
|
||||
self.clock_domains.cd_hdmi5x = ClockDomain()
|
||||
|
||||
|
||||
# # #
|
||||
clk48 = platform.request("clk48")
|
||||
###### explanations from betrusted-io/betrusted-soc/betrusted_soc.py
|
||||
# Note: below feature cannot be used because Litex appends this *after* platform commands! This causes the generated
|
||||
# clock derived constraints immediately below to fail, because .xdc file is parsed in-order, and the main clock needs
|
||||
# to be created before the derived clocks. Instead, we use the line afterwards.
|
||||
platform.add_platform_command("create_clock -name clk48 -period 20.8333 [get_nets clk48]")
|
||||
# The above constraint must strictly proceed the below create_generated_clock constraints in the .XDC file
|
||||
# This allows PLLs/MMCMEs to be placed anywhere and reference the input clock
|
||||
self.clk48_bufg = Signal()
|
||||
self.specials += Instance("BUFG", i_I=clk48, o_O=self.clk48_bufg)
|
||||
self.comb += self.cd_native.clk.eq(self.clk48_bufg)
|
||||
#self.cd_native.clk = clk48
|
||||
|
||||
clk_nubus = platform.request("clk_3v3_n")
|
||||
if (clk_nubus is None):
|
||||
print(" ***** ERROR ***** Can't find the NuBus Clock !!!!\n");
|
||||
assert(false)
|
||||
self.cd_nubus.clk = clk_nubus
|
||||
rst_nubus_n = platform.request("reset_3v3_n")
|
||||
self.comb += self.cd_nubus.rst.eq(~rst_nubus_n)
|
||||
platform.add_platform_command("create_clock -name nubus_clk -period 100.0 -waveform {{0.0 75.0}} [get_ports clk_3v3_n]")
|
||||
|
||||
#clk2x_nubus = platform.request("nubus_clk2x_n")
|
||||
#if (clk2x_nubus is None):
|
||||
# print(" ***** ERROR ***** Can't find the NuBus90 Clock !!!!\n");
|
||||
# assert(false)
|
||||
#self.cd_nubus90.clk = clk2x_nubus
|
||||
#self.comb += self.cd_nubus90.rst.eq(~rst_nubus_n)
|
||||
#platform.add_platform_command("create_clock -name nubus90_clk -period 50.0 -waveform {{0.0 37.5}} [get_ports nubus_clk2x_n]")
|
||||
|
||||
num_adv = 0
|
||||
num_clk = 0
|
||||
|
||||
self.submodules.pll = pll = S7MMCM(speedgrade=platform.speedgrade)
|
||||
#pll.register_clkin(clk48, 48e6)
|
||||
pll.register_clkin(self.clk48_bufg, 48e6)
|
||||
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
||||
platform.add_platform_command("create_generated_clock -name sysclk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
|
||||
num_clk = num_clk + 1
|
||||
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
|
||||
platform.add_platform_command("create_generated_clock -name sys4xclk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
|
||||
num_clk = num_clk + 1
|
||||
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
|
||||
platform.add_platform_command("create_generated_clock -name sys4x90clk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
|
||||
num_clk = num_clk + 1
|
||||
self.comb += pll.reset.eq(~rst_nubus_n) # | ~por_done
|
||||
platform.add_false_path_constraints(self.cd_native.clk, self.cd_nubus.clk) # FIXME?
|
||||
platform.add_false_path_constraints(self.cd_nubus.clk, self.cd_native.clk) # FIXME?
|
||||
#platform.add_false_path_constraints(self.cd_sys.clk, self.cd_nubus.clk)
|
||||
#platform.add_false_path_constraints(self.cd_nubus.clk, self.cd_sys.clk)
|
||||
##platform.add_false_path_constraints(self.cd_native.clk, self.cd_sys.clk)
|
||||
|
||||
num_adv = num_adv + 1
|
||||
num_clk = 0
|
||||
|
||||
self.submodules.pll_idelay = pll_idelay = S7MMCM(speedgrade=platform.speedgrade)
|
||||
#pll_idelay.register_clkin(clk48, 48e6)
|
||||
pll_idelay.register_clkin(self.clk48_bufg, 48e6)
|
||||
pll_idelay.create_clkout(self.cd_idelay, 200e6, margin = 0)
|
||||
platform.add_platform_command("create_generated_clock -name idelayclk [get_pins {{{{MMCME2_ADV_{}/CLKOUT{}}}}}]".format(num_adv, num_clk))
|
||||
num_clk = num_clk + 1
|
||||
self.comb += pll_idelay.reset.eq(~rst_nubus_n) # | ~por_done
|
||||
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
|
||||
num_adv = num_adv + 1
|
||||
num_clk = 0
|
||||
|
||||
if (cg3):
|
||||
self.submodules.video_pll = video_pll = S7MMCM(speedgrade=platform.speedgrade)
|
||||
video_pll.register_clkin(self.clk48_bufg, 48e6)
|
||||
if (not hdmi):
|
||||
video_pll.create_clkout(self.cd_vga, pix_clk, margin = 0.0005)
|
||||
platform.add_platform_command("create_generated_clock -name vga_clk [get_pins {{{{MMCME2_ADV_{}/CLKOUT{}}}}}]".format(num_adv, num_clk))
|
||||
num_clk = num_clk + 1
|
||||
else:
|
||||
video_pll.create_clkout(self.cd_hdmi, pix_clk, margin = 0.0005)
|
||||
video_pll.create_clkout(self.cd_hdmi5x, 5*pix_clk, margin = 0.0005)
|
||||
platform.add_platform_command("create_generated_clock -name hdmi_clk [get_pins {{{{MMCME2_ADV_{}/CLKOUT{}}}}}]".format(num_adv, num_clk))
|
||||
num_clk = num_clk + 1
|
||||
platform.add_platform_command("create_generated_clock -name hdmi5x_clk [get_pins {{{{MMCME2_ADV_{}/CLKOUT{}}}}}]".format(num_adv, num_clk))
|
||||
num_clk = num_clk + 1
|
||||
self.comb += video_pll.reset.eq(~rst_nubus_n)
|
||||
#platform.add_false_path_constraints(self.cd_sys.clk, self.cd_vga.clk)
|
||||
platform.add_false_path_constraints(self.cd_sys.clk, video_pll.clkin)
|
||||
num_adv = num_adv + 1
|
||||
num_clk = 0
|
||||
|
||||
|
||||
|
||||
class NuBusFPGA(SoCCore):
|
||||
def __init__(self, variant, version, sys_clk_freq, cg3, hdmi, cg3_res, **kwargs):
|
||||
print(f"Building NuBusFPGA for board version {version}")
|
||||
|
||||
kwargs["cpu_type"] = "None"
|
||||
kwargs["integrated_sram_size"] = 0
|
||||
kwargs["with_uart"] = False
|
||||
kwargs["with_timer"] = False
|
||||
|
||||
self.sys_clk_freq = sys_clk_freq
|
||||
|
||||
self.platform = platform = ztex213_nubus.Platform(variant = variant, version = version)
|
||||
|
||||
if (cg3):
|
||||
hres = int(cg3_res.split("@")[0].split("x")[0])
|
||||
vres = int(cg3_res.split("@")[0].split("x")[1])
|
||||
cg3_fb_size = cg3_fb.cg3_rounded_size(hres, vres)
|
||||
print(f"Reserving {cg3_fb_size} bytes ({cg3_fb_size//1048576} MiB) for the CG3/CG6")
|
||||
else:
|
||||
hres = 0
|
||||
vres = 0
|
||||
cg3_fb_size = 0
|
||||
litex.soc.cores.video.video_timings.update(cg3_fb.cg3_timings)
|
||||
|
||||
SoCCore.__init__(self,
|
||||
platform=platform,
|
||||
sys_clk_freq=sys_clk_freq,
|
||||
clk_freq=sys_clk_freq,
|
||||
csr_paging=0x800, # default is 0x800
|
||||
**kwargs)
|
||||
|
||||
# Quoting the doc:
|
||||
# * Separate address spaces are reserved for processor access to cards in NuBus slots. For a
|
||||
# * device in NuBus slot number s, the address space in 32-bit mode begins at address
|
||||
# * $Fs00 0000 and continues through the highest address, $FsFF FFFF (where s is a constant in
|
||||
# * the range $9 through $E for the Macintosh II, the Macintosh IIx, and the Macintosh IIfx;
|
||||
# * $A through $E for the Macintosh Quadra 900; $9 through $B for the Macintosh IIcx;
|
||||
# * $C through $E for the Macintosh IIci; $D and $E for the Macintosh Quadra 700; and
|
||||
# * $9 for the Macintosh IIsi).
|
||||
# So at best we get 16 MiB in 32-bits moden unless using "super slot space"
|
||||
# in 24 bits it's only one megabyte, $s0 0000 through $sF FFFF
|
||||
# they are translated: '$s0 0000-$sF FFFF' to '$Fs00 0000-$Fs0F FFFF' (for s in range $9 through $E)
|
||||
self.wb_mem_map = wb_mem_map = {
|
||||
"cg3_mem_short": 0x00000000, # up to 832 KiB of FB memory
|
||||
"csr" : 0x000D0000, # CSR in the middle of the first MB
|
||||
"cg3_bt" : 0x000E0000, # BT for CG3 just before the ROM
|
||||
"rom": 0x000FF000, # ROM at the end of the first MB (4 KiB of it ATM)
|
||||
"END OF FIRST MB" : 0x000FFFFF,
|
||||
"cg3_mem": 0x00100000, # full FB mem, up to 15 MiB
|
||||
"END OF SLOT SPACE": 0x00FFFFFF,
|
||||
"main_ram": 0x80000000, # not directly reachable from NuBus
|
||||
"video_framebuffer": 0x80000000 + 0x10000000 - cg3_fb_size, # Updated later
|
||||
}
|
||||
self.mem_map.update(wb_mem_map)
|
||||
self.submodules.crg = _CRG(platform=platform, sys_clk_freq=sys_clk_freq, cg3=cg3, pix_clk=litex.soc.cores.video.video_timings[cg3_res]["pix_clk"])
|
||||
|
||||
## add our custom timings after the clocks have been defined
|
||||
xdc_timings_filename = None;
|
||||
#if (version == "V1.0"):
|
||||
# xdc_timings_filename = "/home/dolbeau/nubus-to-ztex-gateware/nubus-to-ztex-timings.xdc"
|
||||
|
||||
if (xdc_timings_filename != None):
|
||||
xdc_timings_file = open(xdc_timings_filename)
|
||||
xdc_timings_lines = xdc_timings_file.readlines()
|
||||
for line in xdc_timings_lines:
|
||||
if (line[0:3] == "set"):
|
||||
fix_line = line.strip().replace("{", "{{").replace("}", "}}")
|
||||
#print(fix_line)
|
||||
platform.add_platform_command(fix_line)
|
||||
|
||||
rom_file = "rom_{}.bin".format(version.replace(".", "_"))
|
||||
rom_data = soc_core.get_mem_data(rom_file, "big")
|
||||
# rom = Array(rom_data)
|
||||
#print("\n****************************************\n")
|
||||
#for i in range(len(rom)):
|
||||
# print(hex(rom[i]))
|
||||
#print("\n****************************************\n")
|
||||
self.add_ram("rom", origin=self.mem_map["rom"], size=2**12, contents=rom_data, mode="r") ### FIXME: round up the prom_data size & check for <= 2**12!
|
||||
#getattr(self,"rom").mem.init = rom_data
|
||||
#getattr(self,"rom").mem.depth = 2**16
|
||||
|
||||
avail_sdram = 0
|
||||
#self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
|
||||
# memtype = "DDR3",
|
||||
# nphases = 4,
|
||||
# sys_clk_freq = sys_clk_freq)
|
||||
#self.add_sdram("sdram",
|
||||
# phy = self.ddrphy,
|
||||
# module = MT41J128M16(sys_clk_freq, "1:4"),
|
||||
# l2_cache_size = 0,
|
||||
#)
|
||||
#avail_sdram = self.bus.regions["main_ram"].size
|
||||
|
||||
self.submodules.leds = LedChaser(
|
||||
pads = platform.request_all("user_led"),
|
||||
sys_clk_freq = sys_clk_freq)
|
||||
self.add_csr("leds")
|
||||
|
||||
base_fb = self.wb_mem_map["main_ram"] + avail_sdram - 1048576 # placeholder
|
||||
if (cg3):
|
||||
if (avail_sdram >= cg3_fb_size):
|
||||
avail_sdram = avail_sdram - cg3_fb_size
|
||||
base_fb = self.wb_mem_map["main_ram"] + avail_sdram
|
||||
self.wb_mem_map["video_framebuffer"] = base_fb
|
||||
else:
|
||||
print("***** ERROR ***** Can't have a FrameBuffer without main ram\n")
|
||||
assert(False)
|
||||
|
||||
# don't enable anything on the NuBus side for XX seconds after power up
|
||||
# this avoids FPGA initialization messing with the cold boot process
|
||||
# requires us to reset the Macintosh afterward so the FPGA board
|
||||
# is properly identified
|
||||
# This is in the 'native' ClockDomain that is never reset
|
||||
#hold_reset_ctr = Signal(30, reset=960000000)
|
||||
hold_reset_ctr = Signal(5, reset=31)
|
||||
self.sync.native += If(hold_reset_ctr>0, hold_reset_ctr.eq(hold_reset_ctr - 1))
|
||||
hold_reset = Signal(reset=1)
|
||||
self.comb += hold_reset.eq(~(hold_reset_ctr == 0))
|
||||
pad_nubus_oe = platform.request("nubus_oe")
|
||||
self.comb += pad_nubus_oe.eq(hold_reset)
|
||||
|
||||
# Interface NuBus to wishbone
|
||||
# we need to cross clock domains
|
||||
|
||||
wishbone_master_sys = wishbone.Interface(data_width=self.bus.data_width)
|
||||
self.submodules.wishbone_master_nubus = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_master_sys, cd_master="nubus", cd_slave="sys")
|
||||
self.bus.add_master(name="NuBusBridgeToWishbone", master=wishbone_master_sys)
|
||||
|
||||
self.submodules.nubus = nubus.NuBus(platform=platform, cd_nubus="nubus")
|
||||
self.submodules.nubus2wishbone = ClockDomainsRenamer("nubus")(NuBus2Wishbone(nubus=self.nubus,wb=self.wishbone_master_nubus))
|
||||
|
||||
self.add_ram("ram", origin=self.mem_map["cg3_mem_short"], size=2**16, mode="rw")
|
||||
|
||||
if (cg3):
|
||||
if (not hdmi):
|
||||
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
|
||||
self.submodules.cg3 = cg3_fb.cg3(soc=self, phy=self.videophy, timings=cg3_res, clock_domain="vga") # clock_domain for the VGA side, cg3 is running in cd_sys
|
||||
else:
|
||||
self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi"), clock_domain="hdmi")
|
||||
self.submodules.cg3 = cg3_fb.cg3(soc=self, phy=self.videophy, timings=cg3_res, clock_domain="hdmi") # clock_domain for the VGA side, cg3 is running in cd_sys
|
||||
self.bus.add_slave("cg3_bt", self.cg3.bus, SoCRegion(origin=self.mem_map.get("cg3_bt", None), size=0x1000, cached=False))
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description="SbusFPGA")
|
||||
parser.add_argument("--build", action="store_true", help="Build bitstream")
|
||||
parser.add_argument("--variant", default="ztex2.13a", help="ZTex board variant (default ztex2.13a)")
|
||||
parser.add_argument("--version", default="V1.0", help="NuBusFPGA board version (default V1.0)")
|
||||
parser.add_argument("--sys-clk-freq", default=100e6, help="NuBusFPGA system clock (default 100e6 = 100 MHz)")
|
||||
parser.add_argument("--cg3", action="store_true", help="add a CG3 framebuffer")
|
||||
parser.add_argument("--hdmi", action="store_true", help="The framebuffer uses HDMI (default to VGA)")
|
||||
parser.add_argument("--cg3-res", default="1152x900@76Hz", help="Specify the CG3resolution")
|
||||
builder_args(parser)
|
||||
vivado_build_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = NuBusFPGA(**soc_core_argdict(args),
|
||||
variant=args.variant,
|
||||
version=args.version,
|
||||
sys_clk_freq=int(float(args.sys_clk_freq)),
|
||||
cg3=args.cg3,
|
||||
hdmi=args.hdmi,
|
||||
cg3_res=args.cg3_res)
|
||||
|
||||
version_for_filename = args.version.replace(".", "_")
|
||||
|
||||
soc.platform.name += "_" + version_for_filename
|
||||
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
builder.build(**vivado_build_argdict(args), run=args.build)
|
||||
|
||||
# Generate modified CSR registers definitions/access functions to netbsd_csr.h.
|
||||
# should be split per-device (and without base) to still work if we have identical devices in different configurations on multiple boards
|
||||
# now it is split
|
||||
|
||||
#csr_contents_dict = nubus_to_fpga_export.get_csr_header_split(
|
||||
# regions = soc.csr_regions,
|
||||
# constants = soc.constants,
|
||||
# csr_base = soc.mem_regions['csr'].origin)
|
||||
#for name in csr_contents_dict.keys():
|
||||
# write_to_file(os.path.join("nubusfpga_csr_{}.h".format(name)), csr_contents_dict[name])
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
379
nubus-to-ztex-gateware/slave_tb.sv
Normal file
379
nubus-to-ztex-gateware/slave_tb.sv
Normal file
|
@ -0,0 +1,379 @@
|
|||
`timescale 1 ns / 1 ps
|
||||
|
||||
module nubus_slave_tb ();
|
||||
|
||||
`include "nubus_tb.svh"
|
||||
|
||||
parameter TEST_CARD_ID = 'h0;
|
||||
parameter TEST_ADDR = 'hF0000000;
|
||||
parameter TEST_DATA = 'h87654321;
|
||||
parameter [1:0] MEMORY_WAIT_CLOCKS = 1;
|
||||
parameter DEBUG_NUBUS_START = 0;
|
||||
parameter ROM_ADDR = 'hF00FF000;
|
||||
|
||||
// Clock (rising is driving edge, faling is sampling)
|
||||
tri1 bd_clk48;
|
||||
|
||||
// Slot Identification
|
||||
tri1 [3:0] nub_idn;
|
||||
// Clock (rising is driving edge, faling is sampling)
|
||||
tri1 nub_clkn;
|
||||
// Clock 90 (rising is driving edge, faling is sampling)
|
||||
//tri1 nub_clk2xn;
|
||||
// Reset [Open Collector]
|
||||
tri1 nub_resetn;
|
||||
// Power Fail Warning [Control]
|
||||
//tri1 nub_pfwn;
|
||||
// Address/Data [Address/Data]
|
||||
tri1 [31:0] nub_adn;
|
||||
// Transfer Mode [Control]
|
||||
tri1 nub_tm0n;
|
||||
tri1 nub_tm1n;
|
||||
//tri1 nub_tm2n;
|
||||
// Start [Control]
|
||||
tri1 nub_startn;
|
||||
// Request [Open Collector]
|
||||
tri1 nub_rqstn;
|
||||
// Acknowledge [Control]
|
||||
tri1 nub_ackn;
|
||||
// Arbitration [Open Collector]
|
||||
tri1 [3:0] nub_arbn;
|
||||
// Non-Master Request [Open Collector]
|
||||
tri1 nub_nmrqn;
|
||||
// System Parity [Address/Data]
|
||||
//tri1 nub_spn;
|
||||
// System Parity Valid [Address/Data]
|
||||
//tri1 nub_spvn;
|
||||
|
||||
tri1 [4:0] leds;
|
||||
|
||||
tri unused0, tmoen, unused1, unused2;
|
||||
tri arb, grant;
|
||||
tri nubus_oe, nubus_master_dir, nubus_ad_dir;
|
||||
tri reset_n_3v3, clk_n_3v3, tm0_n_3v3, tm1_n_3v3, start_n_3v3, ack_n_3v3;
|
||||
tri1 [3:0] id_n_3v3;
|
||||
tri [31:0] ad_n_3v3;
|
||||
|
||||
assign nub_idn = ~ TEST_CARD_ID;
|
||||
|
||||
assign nubus_master_dir = 0;
|
||||
assign nub_arbn = 'b1111;
|
||||
|
||||
nubus_cpld UCPLD (
|
||||
.fpga_to_cpld_clk(unused0),
|
||||
.tmoen(tmoen),
|
||||
.fpga_to_cpld_signal(unused1),
|
||||
.fpga_to_cpld_signal_2(unused2),
|
||||
.id_n_5v(nub_idn),
|
||||
.arb_n_5v(nub_arbn),
|
||||
.arb(arb),
|
||||
.grant(grant),
|
||||
.reset_n_5v(nub_resetn),
|
||||
.nubus_oe(nubus_oe),
|
||||
.reset_n_3v3(reset_n_3v3),
|
||||
.nubus_master_dir(nubus_master_dir),
|
||||
.clk_n_3v3(clk_n_3v3),
|
||||
.id_n_3v3(id_n_3v3),
|
||||
.tm0_n_3v3(tm0_n_3v3),
|
||||
.tm1_n_3v3(tm1_n_3v3),
|
||||
.tm0_n_5v(nub_tm0n),
|
||||
.tm1_n_5v(nub_tm1n),
|
||||
.clk_n_5v(nub_clkn),
|
||||
.start_n_3v3(start_n_3v3),
|
||||
.ack_n_3v3(ack_n_3v3),
|
||||
.start_n_5v(nub_startn),
|
||||
.ack_n_5v(nub_ackn)
|
||||
);
|
||||
|
||||
sn74fct245 shifters_b0(.data_5v(nub_adn[ 7: 0]),
|
||||
.data_3v3(ad_n_3v3[ 7: 0]),
|
||||
.nubus_oe(nubus_oe),
|
||||
.nubus_ad_dir(nubus_ad_dir));
|
||||
sn74fct245 shifters_b1(.data_5v(nub_adn[15: 8]),
|
||||
.data_3v3(ad_n_3v3[15: 8]),
|
||||
.nubus_oe(nubus_oe),
|
||||
.nubus_ad_dir(nubus_ad_dir));
|
||||
sn74fct245 shifters_b2(.data_5v(nub_adn[23:16]),
|
||||
.data_3v3(ad_n_3v3[23:16]),
|
||||
.nubus_oe(nubus_oe),
|
||||
.nubus_ad_dir(nubus_ad_dir));
|
||||
sn74fct245 shifters_b3(.data_5v(nub_adn[31:24]),
|
||||
.data_3v3(ad_n_3v3[31:24]),
|
||||
.nubus_oe(nubus_oe),
|
||||
.nubus_ad_dir(nubus_ad_dir));
|
||||
|
||||
ztex213_nubus_V1_0 UNuBus (
|
||||
// NuBus lines only
|
||||
.clk48(bd_clk48),
|
||||
.clk_3v3_n(clk_n_3v3),
|
||||
.reset_3v3_n(reset_n_3v3),
|
||||
// .nubus_clk2x_n(nub_clk2xn),
|
||||
.user_led0(leds[0]),
|
||||
.user_led1(leds[1]),
|
||||
.user_led2(leds[2]),
|
||||
.user_led3(leds[3]),
|
||||
//.nubus_tm2_n(nub_tm2n),
|
||||
.id_3v3_n(id_n_3v3),
|
||||
.ad_3v3_n(ad_n_3v3),
|
||||
.tm0_3v3_n(tm0_n_3v3),
|
||||
.tm1_3v3_n(tm1_n_3v3),
|
||||
.start_3v3_n(start_n_3v3),
|
||||
.rqst_3v3_n(nub_rqstn),
|
||||
.ack_3v3_n(ack_n_3v3),
|
||||
// .nubus_arb_n(nub_arbn),
|
||||
.arb(arb),
|
||||
.grant(grant),
|
||||
.tmoen(tmoen),
|
||||
.nubus_ad_dir(nubus_ad_dir),
|
||||
.nmrq_3v3_n(nub_nmrqn),
|
||||
.nubus_oe(nubus_oe)
|
||||
);
|
||||
|
||||
|
||||
// State machine of test bench
|
||||
reg tst_clkn;
|
||||
reg tst_clk48;
|
||||
reg tst_resetn;
|
||||
reg tst_startn;
|
||||
reg tst_ackn; // half clkn delayed ackn
|
||||
reg [1:0] tst_tmn;
|
||||
reg [1:0] tst_statusn;
|
||||
reg [31:0] tst_addrn;
|
||||
reg [31:0] tst_wdatan;
|
||||
reg [31:0] tst_rdatan;
|
||||
|
||||
// Drive NuBus signals
|
||||
assign nub_clkn = tst_clkn;
|
||||
assign bd_clk48 = tst_clk48;
|
||||
assign nub_resetn = tst_resetn;
|
||||
assign nub_startn = tst_startn;
|
||||
assign nub_tm0n = tst_startn ? 'bZ : tst_tmn[0];
|
||||
assign nub_tm1n = tst_startn ? 'bZ : tst_tmn[1];
|
||||
assign nub_ackn = tst_startn ? 'bZ : tst_ackn;
|
||||
|
||||
// Drive NuBus address/data lines
|
||||
wire [31:0] tst_adn = tst_startn ? tst_wdatan : tst_addrn;
|
||||
wire tst_nuboen = tst_startn & tst_tmn[1];
|
||||
assign nub_adn = tst_nuboen ? 'bZ : tst_adn;
|
||||
|
||||
// Inverted verions of registers
|
||||
wire [31:0] tst_rdata = ~tst_rdatan;
|
||||
wire [31:0] tst_addr = ~tst_addrn;
|
||||
|
||||
initial begin
|
||||
$display ("Start virtual master (vm) writes and reads to/from NuBus slave memory module");
|
||||
$dumpfile("nubus_slave_tb.vcd");
|
||||
$dumpvars;
|
||||
|
||||
tst_clkn <= 1;
|
||||
tst_resetn <= 0;
|
||||
tst_addrn <= 'hFFFFFFFF;
|
||||
tst_wdatan <= 'hFFFFFFFF;
|
||||
tst_rdatan <= 'hFFFFFFFF;
|
||||
tst_startn <= 1;
|
||||
tst_statusn<= TMN_TRY_AGAIN_LATER;
|
||||
tst_tmn <= TMN_NOP;
|
||||
|
||||
@ (posedge nub_clkn);
|
||||
@ (posedge nub_clkn);
|
||||
tst_resetn <= 1;
|
||||
|
||||
#2000;
|
||||
|
||||
@ (posedge nub_clkn);
|
||||
$display ("%g: %b", $time, nub_startn);
|
||||
|
||||
$display ("WORD ---------------------------");
|
||||
write_word(TMADN_WR_WORD, TEST_ADDR+0, TEST_DATA);
|
||||
read_word (TMADN_RD_WORD, TEST_ADDR+0);
|
||||
check_word(TMADN_RD_WORD, TEST_DATA);
|
||||
$display ("HALF 0 -------------------------");
|
||||
write_word(TMADN_WR_HALF_0, TEST_ADDR+4, TEST_DATA);
|
||||
read_word (TMADN_RD_HALF_0, TEST_ADDR+4);
|
||||
check_word(TMADN_RD_HALF_0, TEST_DATA);
|
||||
$display ("HALF 1 -------------------------");
|
||||
write_word(TMADN_WR_HALF_1, TEST_ADDR+8, TEST_DATA);
|
||||
read_word (TMADN_RD_HALF_1, TEST_ADDR+8);
|
||||
check_word(TMADN_RD_HALF_1, TEST_DATA);
|
||||
|
||||
$display ("BYTE 0 -------------------------");
|
||||
write_word(TMADN_WR_BYTE_0, TEST_ADDR+12, TEST_DATA);
|
||||
read_word (TMADN_RD_BYTE_0, TEST_ADDR+12);
|
||||
check_word(TMADN_RD_BYTE_0, TEST_DATA);
|
||||
$display ("BYTE 1 -------------------------");
|
||||
write_word(TMADN_WR_BYTE_1, TEST_ADDR+16, TEST_DATA);
|
||||
read_word (TMADN_RD_BYTE_1, TEST_ADDR+16);
|
||||
check_word(TMADN_RD_BYTE_1, TEST_DATA);
|
||||
$display ("BYTE 2 -------------------------");
|
||||
write_word(TMADN_WR_BYTE_2, TEST_ADDR+20, TEST_DATA);
|
||||
read_word (TMADN_RD_BYTE_2, TEST_ADDR+20);
|
||||
check_word(TMADN_RD_BYTE_2, TEST_DATA);
|
||||
$display ("BYTE 3 -------------------------");
|
||||
write_word(TMADN_WR_BYTE_3, TEST_ADDR+24, TEST_DATA);
|
||||
read_word (TMADN_RD_BYTE_3, TEST_ADDR+24);
|
||||
check_word(TMADN_RD_BYTE_3, TEST_DATA);
|
||||
|
||||
// $display ("BLOCK2 -------------------------");
|
||||
// read_block2 (TMADN_RD_BLOCK, TEST_ADDR);
|
||||
|
||||
#500
|
||||
|
||||
// Check Rom
|
||||
$display ("ROM ---------------------------");
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+4092);
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+4088);
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+4084);
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+4080);
|
||||
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+0);
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+4);
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+8);
|
||||
read_word (TMADN_RD_WORD, ROM_ADDR+12);
|
||||
|
||||
#1000;
|
||||
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
// ======================================================
|
||||
// Write task
|
||||
// ======================================================
|
||||
|
||||
task write_word;
|
||||
input [3:0] tmadn;
|
||||
input [31:0] addr;
|
||||
input [31:0] data;
|
||||
begin
|
||||
@ (posedge nub_clkn);
|
||||
tst_wdatan <= ~data;
|
||||
tst_addrn[31:2] <= ~addr[31:2];
|
||||
tst_addrn[ 1:0] <= tmadn[1:0];
|
||||
tst_tmn <= tmadn[3:2];
|
||||
tst_startn <= 0;
|
||||
tst_ackn <= 1;
|
||||
//tst_statusn <= TMN_TRY_AGAIN_LATER;
|
||||
@ (posedge nub_clkn);
|
||||
tst_startn <= 1;
|
||||
tst_ackn <= nub_ackn;
|
||||
do begin
|
||||
@ (negedge nub_clkn);
|
||||
tst_ackn <= nub_ackn;
|
||||
tst_statusn <= { nub_tm1n, nub_tm0n };
|
||||
//@ (posedge nub_clkn);
|
||||
end while (tst_ackn) ;
|
||||
$display ("%g (write) address: $%h tm: $%h data: $%h stat: %s", $time, addr, tmadn, data, get_status_str(tst_statusn));
|
||||
end
|
||||
endtask
|
||||
|
||||
// ======================================================
|
||||
// Read task
|
||||
// ======================================================
|
||||
|
||||
task read_word;
|
||||
input [3:0] tmadn;
|
||||
input [31:0] addr;
|
||||
begin
|
||||
@ (posedge nub_clkn);
|
||||
tst_tmn <= tmadn[3:2];
|
||||
tst_addrn[ 1:0] <= tmadn[1:0];
|
||||
tst_addrn[31:2] <= ~addr[31:2];
|
||||
tst_startn <= 0;
|
||||
tst_ackn <= 1;
|
||||
//tst_statusn <= TMN_TRY_AGAIN_LATER;
|
||||
@ (posedge nub_clkn);
|
||||
tst_startn <= 1;
|
||||
tst_ackn <= nub_ackn;
|
||||
do begin
|
||||
@ (negedge nub_clkn);
|
||||
tst_rdatan <= nub_adn;
|
||||
tst_ackn <= nub_ackn;
|
||||
tst_statusn <= { nub_tm1n, nub_tm0n };
|
||||
//@ (posedge nub_clkn);
|
||||
end while (tst_ackn) ;
|
||||
$display ("%g (read ) address: $%h tm: $%h data: $%h stat: %s", $time, addr, tmadn, tst_rdata, get_status_str(tst_statusn));
|
||||
end
|
||||
endtask
|
||||
|
||||
// ======================================================
|
||||
// Verify data writen to memory with read from
|
||||
// asume memory befor write was $00000000
|
||||
// ======================================================
|
||||
|
||||
task check_word
|
||||
(
|
||||
input [3:0] tm,
|
||||
input [31:0] data_wr
|
||||
);
|
||||
reg [31:0] expected;
|
||||
begin
|
||||
expected = (data_wr & get_mask(tm));
|
||||
if (tst_rdata == expected)
|
||||
$display (":) PASSED");
|
||||
else
|
||||
$display (":( FAILED expected: $%h found: $%h", expected, tst_rdata);
|
||||
$display(" ");
|
||||
end
|
||||
endtask // verify
|
||||
|
||||
// ======================================================
|
||||
// Read block2 task
|
||||
// Currently unsupported (introduced with Q700/Q900, not in the NTC)
|
||||
// ======================================================
|
||||
|
||||
task read_block2;
|
||||
input [3:0] tmadn;
|
||||
input [31:0] addr;
|
||||
begin
|
||||
@ (posedge nub_clkn);
|
||||
tst_tmn <= tmadn[3:2];
|
||||
tst_addrn[ 1:0] <= tmadn[1:0];
|
||||
tst_addrn[ 2:2] <= 1; // this indicates size 2
|
||||
tst_addrn[31:3] <= ~addr[31:3];
|
||||
tst_startn <= 0;
|
||||
//tst_statusn <= TMN_TRY_AGAIN_LATER;
|
||||
@ (posedge nub_clkn);
|
||||
tst_startn <= 1;
|
||||
tst_ackn <= nub_ackn;
|
||||
do begin
|
||||
@ (negedge nub_clkn);
|
||||
tst_rdatan <= nub_adn;
|
||||
tst_ackn <= nub_ackn;
|
||||
tst_statusn <= { nub_tm1n, nub_tm0n };
|
||||
//@ (posedge nub_clkn);
|
||||
end while (tst_statusn[0]) ;
|
||||
$display ("%g (block0/2) address: $%h tm: $%h data: $%h stat: %s", $time, addr, tmadn, tst_rdata, get_status_str(tst_statusn));
|
||||
do begin
|
||||
@ (negedge nub_clkn);
|
||||
tst_rdatan <= nub_adn;
|
||||
tst_ackn <= nub_ackn;
|
||||
tst_statusn <= { nub_tm1n, nub_tm0n };
|
||||
//@ (posedge nub_clkn);
|
||||
end while (tst_ackn) ;
|
||||
$display ("%g (block1/2) address: $%h tm: $%h data: $%h stat: %s", $time, addr, tmadn, tst_rdata, get_status_str(tst_statusn));
|
||||
end
|
||||
endtask // read block2
|
||||
|
||||
// ======================================================
|
||||
// Clock generators
|
||||
// ======================================================
|
||||
|
||||
always begin
|
||||
tst_clkn <= 1;
|
||||
#75;
|
||||
tst_clkn <= 0;
|
||||
if (DEBUG_NUBUS_START) begin
|
||||
if (~nub_startn)
|
||||
$display ("%g (NuBus Start) /ad: $%h {/tmadn}: %b%b%b%b", $time, nub_adn, nub_tm1n, nub_tm0n, nub_adn[1], nub_adn[0]);
|
||||
end
|
||||
#25;
|
||||
end
|
||||
|
||||
always begin
|
||||
tst_clk48 <= 0;
|
||||
#10.41666666;
|
||||
tst_clk48 <= 1;
|
||||
#10.41666666;
|
||||
end
|
||||
|
||||
endmodule
|
184
nubus-to-ztex-gateware/ztex213_nubus.py
Normal file
184
nubus-to-ztex-gateware/ztex213_nubus.py
Normal file
|
@ -0,0 +1,184 @@
|
|||
#
|
||||
# This file is part of LiteX-Boards.
|
||||
#
|
||||
# Support for the ZTEX USB-FGPA Module 2.13:
|
||||
# <https://www.ztex.de/usb-fpga-2/usb-fpga-2.13.e.html>
|
||||
# With (no-so-optional) expansion, either the ZTEX Debug board:
|
||||
# <https://www.ztex.de/usb-fpga-2/debug.e.html>
|
||||
# Or the NuBusFPGA adapter board:
|
||||
# <https://github.com/rdolbeau/NuBusFPGA>
|
||||
#
|
||||
# Copyright (c) 2015 Yann Sionneau <yann.sionneau@gmail.com>
|
||||
# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# Copyright (c) 2020-2021 Romain Dolbeau <romain@dolbeau.org>
|
||||
# SPDX-License-Identifier: BSD-2-Clause
|
||||
|
||||
from litex.build.generic_platform import *
|
||||
from litex.build.xilinx import XilinxPlatform
|
||||
from litex.build.openocd import OpenOCD
|
||||
|
||||
# IOs ----------------------------------------------------------------------------------------------
|
||||
|
||||
# FPGA daughterboard I/O
|
||||
|
||||
_io = [
|
||||
## 48 MHz clock reference
|
||||
("clk48", 0, Pins("P15"), IOStandard("LVCMOS33")),
|
||||
## embedded 256 MiB DDR3 DRAM
|
||||
("ddram", 0,
|
||||
Subsignal("a", Pins("C5 B6 C7 D5 A3 E7 A4 C6", "A6 D8 B2 A5 B3 B7"),
|
||||
IOStandard("SSTL135")),
|
||||
Subsignal("ba", Pins("E5 A1 E6"), IOStandard("SSTL135")),
|
||||
Subsignal("ras_n", Pins("E3"), IOStandard("SSTL135")),
|
||||
Subsignal("cas_n", Pins("D3"), IOStandard("SSTL135")),
|
||||
Subsignal("we_n", Pins("D4"), IOStandard("SSTL135")),
|
||||
# Subsignal("cs_n", Pins(""), IOStandard("SSTL135")),
|
||||
Subsignal("dm", Pins("G1 G6"), IOStandard("SSTL135")),
|
||||
Subsignal("dq", Pins(
|
||||
"H1 F1 E2 E1 F4 C1 F3 D2",
|
||||
"G4 H5 G3 H6 J2 J3 K1 K2"),
|
||||
IOStandard("SSTL135"),
|
||||
Misc("IN_TERM=UNTUNED_SPLIT_40")),
|
||||
Subsignal("dqs_p", Pins("H2 J4"),
|
||||
IOStandard("DIFF_SSTL135"),
|
||||
Misc("IN_TERM=UNTUNED_SPLIT_40")),
|
||||
Subsignal("dqs_n", Pins("G2 H4"),
|
||||
IOStandard("DIFF_SSTL135"),
|
||||
Misc("IN_TERM=UNTUNED_SPLIT_40")),
|
||||
Subsignal("clk_p", Pins("C4"), IOStandard("DIFF_SSTL135")),
|
||||
Subsignal("clk_n", Pins("B4"), IOStandard("DIFF_SSTL135")),
|
||||
Subsignal("cke", Pins("B1"), IOStandard("SSTL135")),
|
||||
Subsignal("odt", Pins("F5"), IOStandard("SSTL135")),
|
||||
Subsignal("reset_n", Pins("J5"), IOStandard("SSTL135")),
|
||||
Misc("SLEW=FAST"),
|
||||
),
|
||||
]
|
||||
|
||||
# NuBusFPGA I/O
|
||||
|
||||
_nubus_io_v1_0 = [
|
||||
## leds on the NuBus board
|
||||
("user_led", 0, Pins("V5"), IOStandard("lvcmos33")), #LED0
|
||||
("user_led", 1, Pins("V4"), IOStandard("lvcmos33")), #LED1
|
||||
("user_led", 2, Pins("T5"), IOStandard("lvcmos33")), #LED2
|
||||
("user_led", 3, Pins("T4"), IOStandard("lvcmos33")), #LED3
|
||||
## serial header for console
|
||||
("serial", 0,
|
||||
Subsignal("tx", Pins("V9")), # FIXME: might be the other way round
|
||||
Subsignal("rx", Pins("U9")),
|
||||
IOStandard("LVCMOS33")
|
||||
),
|
||||
## USB
|
||||
("usb", 0,
|
||||
Subsignal("dp", Pins("B11")),
|
||||
Subsignal("dm", Pins("A11")),
|
||||
IOStandard("LVCMOS33")
|
||||
),
|
||||
## VGA
|
||||
("vga", 0,
|
||||
Subsignal("clk", Pins("K6")),
|
||||
Subsignal("hsync", Pins("U4")),
|
||||
Subsignal("vsync", Pins("U3")),
|
||||
Subsignal("b", Pins("M2 M3 M4 N4 L5 L6 M6 N6")),
|
||||
Subsignal("g", Pins("N2 N1 M1 L1 K3 L3 L4 K5")),
|
||||
Subsignal("r", Pins("P5 N5 P4 P3 T1 R1 R2 P2")),
|
||||
IOStandard("LVCMOS33"),
|
||||
),
|
||||
# HDMI
|
||||
("hdmi", 0,
|
||||
Subsignal("clk_p", Pins("R6"), IOStandard("TMDS_33")),
|
||||
Subsignal("clk_n", Pins("R5"), IOStandard("TMDS_33")),
|
||||
Subsignal("data0_p", Pins("U1"), IOStandard("TMDS_33")),
|
||||
Subsignal("data0_n", Pins("V1"), IOStandard("TMDS_33")),
|
||||
Subsignal("data1_p", Pins("U2"), IOStandard("TMDS_33")),
|
||||
Subsignal("data1_n", Pins("V2"), IOStandard("TMDS_33")),
|
||||
Subsignal("data2_p", Pins("R3"), IOStandard("TMDS_33")),
|
||||
Subsignal("data2_n", Pins("T3"), IOStandard("TMDS_33")),
|
||||
Subsignal("hdp", Pins("T8"), IOStandard("LVCMOS33")),
|
||||
Subsignal("sda", Pins("R8"), IOStandard("LVCMOS33")),
|
||||
Subsignal("scl", Pins("R7"), IOStandard("LVCMOS33")),
|
||||
Subsignal("cec", Pins("T6"), IOStandard("LVCMOS33")),
|
||||
),
|
||||
]
|
||||
|
||||
_nubus_nubus_v1_0 = [
|
||||
("clk_3v3_n", 0, Pins("H16"), IOStandard("lvttl")),
|
||||
# ("nubus_clk2x_n", 0, Pins(""), IOStandard("lvttl")),
|
||||
("ack_3v3_n", 0, Pins("K13"), IOStandard("lvttl")),
|
||||
("nmrq_3v3_n", 0, Pins("J18"), IOStandard("lvttl")),
|
||||
("reset_3v3_n", 0, Pins("G17"), IOStandard("lvttl")),
|
||||
("rqst_3v3_n" , 0, Pins("K16"), IOStandard("lvttl")),
|
||||
("start_3v3_n", 0, Pins("J15"), IOStandard("lvttl")),
|
||||
("ad_3v3_n", 0, Pins("A13 A14 C12 B12 B13 B14 A15 A16 "
|
||||
"D12 D13 D14 C14 B16 B17 D15 C15 "
|
||||
"B18 A18 C16 C17 E15 E16 F14 F13 "
|
||||
"D17 D18 E17 E18 F15 F18 F16 G18 "), IOStandard("lvttl")),
|
||||
# ("nubus_arb_n", 0, Pins(""), IOStandard("lvttl")),
|
||||
("id_3v3_n", 0, Pins("U7 V6 V7 U8"), IOStandard("lvttl")),
|
||||
("tm0_3v3_n", 0, Pins("K15"), IOStandard("lvttl")),
|
||||
("tm1_3v3_n", 0, Pins("J17"), IOStandard("lvttl")),
|
||||
# ("nubus_tm2_n", 0, Pins(""), IOStandard("lvttl")),
|
||||
|
||||
("nubus_oe", 0, Pins("G13"), IOStandard("lvttl")),
|
||||
("nubus_ad_dir", 0, Pins("G16"), IOStandard("lvttl")),
|
||||
("nubus_master_dir", 0, Pins("H17"), IOStandard("lvttl")),
|
||||
("grant", 0, Pins("H15"), IOStandard("lvttl")),
|
||||
("arb", 0, Pins("J13"), IOStandard("lvttl")),
|
||||
("fpga_to_cpld_clk", 0, Pins("H14"), IOStandard("lvttl")),
|
||||
("tmoen", 0, Pins("U6"), IOStandard("lvttl")),
|
||||
("fpga_to_cpld_signal",0, Pins("J14"), IOStandard("lvttl")),
|
||||
("fpga_to_cpld_signal_2",0, Pins("G14"), IOStandard("lvttl")),
|
||||
]
|
||||
|
||||
# Connectors ---------------------------------------------------------------------------------------
|
||||
connectors = [
|
||||
]
|
||||
|
||||
# Platform -----------------------------------------------------------------------------------------
|
||||
|
||||
class Platform(XilinxPlatform):
|
||||
default_clk_name = "clk48"
|
||||
default_clk_period = 1e9/48e6
|
||||
|
||||
def __init__(self, variant="ztex2.13a", version="V1.0"):
|
||||
device = {
|
||||
"ztex2.13a": "xc7a35tcsg324-1",
|
||||
"ztex2.13b": "xc7a50tcsg324-1", #untested
|
||||
"ztex2.13b2": "xc7a50tcsg324-1", #untested
|
||||
"ztex2.13c": "xc7a75tcsg324-2", #untested
|
||||
"ztex2.13d": "xc7a100tcsg324-2" #untested
|
||||
}[variant]
|
||||
nubus_io = {
|
||||
"V1.0" : _nubus_io_v1_0,
|
||||
}[version]
|
||||
nubus_nubus = {
|
||||
"V1.0" : _nubus_nubus_v1_0,
|
||||
}[version]
|
||||
self.speedgrade = -1
|
||||
if (device[-1] == '2'):
|
||||
self.speedgrade = -2
|
||||
|
||||
XilinxPlatform.__init__(self, device, _io, connectors, toolchain="vivado")
|
||||
self.add_extension(nubus_io)
|
||||
print(nubus_nubus)
|
||||
self.add_extension(nubus_nubus)
|
||||
|
||||
self.toolchain.bitstream_commands = \
|
||||
["set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]",
|
||||
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]",
|
||||
"set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]",
|
||||
"set_property BITSTREAM.GENERAL.COMPRESS true [current_design]",
|
||||
"set_property BITSTREAM.GENERAL.CRC DISABLE [current_design]",
|
||||
"set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]",
|
||||
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
|
||||
"set_property CFGBVS VCCO [current_design]"
|
||||
# , "set_property STEPS.SYNTH_DESIGN.ARGS.DIRECTIVE AreaOptimized_high [get_runs synth_1]"
|
||||
]
|
||||
|
||||
def create_programmer(self):
|
||||
bscan_spi = "bscan_spi_xc7a35t.bit"
|
||||
return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi) #FIXME
|
||||
|
||||
def do_finalize(self, fragment):
|
||||
XilinxPlatform.do_finalize(self, fragment)
|
||||
#self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)
|
56982
nubus-to-ztex/10029449-111RLF.stp
Normal file
56982
nubus-to-ztex/10029449-111RLF.stp
Normal file
File diff suppressed because it is too large
Load Diff
15328
nubus-to-ztex/1050170001.stp
Normal file
15328
nubus-to-ztex/1050170001.stp
Normal file
File diff suppressed because it is too large
Load Diff
18404
nubus-to-ztex/676432911.stp
Normal file
18404
nubus-to-ztex/676432911.stp
Normal file
File diff suppressed because it is too large
Load Diff
89
nubus-to-ztex/74CB3T16211.pretty/74CB3T16211.kicad_mod
Normal file
89
nubus-to-ztex/74CB3T16211.pretty/74CB3T16211.kicad_mod
Normal file
|
@ -0,0 +1,89 @@
|
|||
(module TSSOP-56_6.1x14mm_P0.5mm (layer F.Cu) (tedit 5A02F25C)
|
||||
(descr "TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot364-1_po.pdf)")
|
||||
(tags "SSOP 0.5")
|
||||
(attr smd)
|
||||
(fp_text reference REF** (at 0 -8.05) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value TSSOP-56_6.1x14mm_P0.5mm (at 0 8.05) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -2.05 -7.0) (end 3.05 -7.0) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start 3.05 -7.0) (end 3.05 7.0) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start 3.05 7.0) (end -3.05 7.0) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start -3.05 7.0) (end -3.05 -6.0) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start -3.05 -6.0) (end -2.05 -7.0) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start -4.5 -7.3) (end -4.5 7.3) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 4.5 -7.3) (end 4.5 7.3) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -4.5 -7.3) (end 4.5 -7.3) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -4.5 7.3) (end 4.5 7.3) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 3.175 -7.125) (end 3.175 -7.1175) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 3.175 7.125) (end 3.175 7.1175) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -3.175 7.125) (end -3.175 7.1175) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -4.25 -7.2) (end 3.175 -7.2) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -3.175 7.125) (end 3.175 7.125) (layer F.SilkS) (width 0.15))
|
||||
(fp_text user %R (at 0 0) (layer F.Fab)
|
||||
(effects (font (size 0.8 0.8) (thickness 0.15)))
|
||||
)
|
||||
(pad 1 smd rect (at -3.75 -6.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 2 smd rect (at -3.75 -6.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 3 smd rect (at -3.75 -5.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 4 smd rect (at -3.75 -5.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 5 smd rect (at -3.75 -4.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 6 smd rect (at -3.75 -4.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 7 smd rect (at -3.75 -3.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 8 smd rect (at -3.75 -3.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 9 smd rect (at -3.75 -2.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 10 smd rect (at -3.75 -2.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 11 smd rect (at -3.75 -1.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 12 smd rect (at -3.75 -1.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 13 smd rect (at -3.75 -0.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 14 smd rect (at -3.75 -0.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 15 smd rect (at -3.75 0.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 16 smd rect (at -3.75 0.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 17 smd rect (at -3.75 1.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 18 smd rect (at -3.75 1.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 19 smd rect (at -3.75 2.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 20 smd rect (at -3.75 2.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 21 smd rect (at -3.75 3.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 22 smd rect (at -3.75 3.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 23 smd rect (at -3.75 4.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 24 smd rect (at -3.75 4.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 25 smd rect (at -3.75 5.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 26 smd rect (at -3.75 5.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 27 smd rect (at -3.75 6.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 28 smd rect (at -3.75 6.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 29 smd rect (at 3.75 6.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 30 smd rect (at 3.75 6.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 31 smd rect (at 3.75 5.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 32 smd rect (at 3.75 5.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 33 smd rect (at 3.75 4.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 34 smd rect (at 3.75 4.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 35 smd rect (at 3.75 3.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 36 smd rect (at 3.75 3.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 37 smd rect (at 3.75 2.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 38 smd rect (at 3.75 2.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 39 smd rect (at 3.75 1.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 40 smd rect (at 3.75 1.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 41 smd rect (at 3.75 0.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 42 smd rect (at 3.75 0.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 43 smd rect (at 3.75 -0.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 44 smd rect (at 3.75 -0.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 45 smd rect (at 3.75 -1.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 46 smd rect (at 3.75 -1.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 47 smd rect (at 3.75 -2.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 48 smd rect (at 3.75 -2.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 49 smd rect (at 3.75 -3.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 50 smd rect (at 3.75 -3.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 51 smd rect (at 3.75 -4.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 52 smd rect (at 3.75 -4.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 53 smd rect (at 3.75 -5.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 54 smd rect (at 3.75 -5.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 55 smd rect (at 3.75 -6.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 56 smd rect (at 3.75 -6.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-56_6.1x14mm_P0.5mm.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
39516
nubus-to-ztex/850030567.stp
Normal file
39516
nubus-to-ztex/850030567.stp
Normal file
File diff suppressed because it is too large
Load Diff
64
nubus-to-ztex/ADV7125-lqfp48.lib
Normal file
64
nubus-to-ztex/ADV7125-lqfp48.lib
Normal file
|
@ -0,0 +1,64 @@
|
|||
EESchema-LIBRARY Version 2.3
|
||||
#encoding utf-8
|
||||
#
|
||||
# ADV7125-lqfp48
|
||||
#
|
||||
DEF ADV7125-lqfp48 U 0 40 Y Y 1 F N
|
||||
F0 "U" 0 -100 50 H V C CNN
|
||||
F1 "ADV7125-lqfp48" 0 100 50 H V C CNN
|
||||
F2 "MODULE" 0 0 50 H I C CNN
|
||||
F3 "DOCUMENTATION" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -950 -1550 950 2250 1 0 0 N
|
||||
X GND 1 -450 -1850 300 U 50 50 1 1 W
|
||||
X GND 2 -350 -1850 300 U 50 50 1 1 W
|
||||
X G0 3 -1250 1000 300 R 50 50 1 1 I
|
||||
X G1 4 -1250 900 300 R 50 50 1 1 I
|
||||
X G2 5 -1250 800 300 R 50 50 1 1 I
|
||||
X G3 6 -1250 700 300 R 50 50 1 1 I
|
||||
X G4 7 -1250 600 300 R 50 50 1 1 I
|
||||
X G5 8 -1250 500 300 R 50 50 1 1 I
|
||||
X G6 9 -1250 400 300 R 50 50 1 1 I
|
||||
X G7 10 -1250 300 300 R 50 50 1 1 I
|
||||
X B4 20 -1250 -350 300 R 50 50 1 1 I
|
||||
X VAA 30 -100 2550 300 D 50 50 1 1 I
|
||||
X GND 40 250 -1850 300 U 50 50 1 1 W
|
||||
X BLANKB 11 -1250 -1150 300 R 50 50 1 1 I
|
||||
X B5 21 -1250 -450 300 R 50 50 1 1 I
|
||||
X #IOG 31 1250 400 300 L 50 50 1 1 I
|
||||
X R0 41 -1250 1950 300 R 50 50 1 1 I
|
||||
X SYNCB 12 -1250 -1250 300 R 50 50 1 1 I
|
||||
X B6 22 -1250 -550 300 R 50 50 1 1 I
|
||||
X IOG 32 1250 500 300 L 50 50 1 1 I
|
||||
X R1 42 -1250 1850 300 R 50 50 1 1 I
|
||||
X VAA 13 100 2550 300 D 50 50 1 1 I
|
||||
X B7 23 -1250 -650 300 R 50 50 1 1 I
|
||||
X #IOR 33 1250 700 300 L 50 50 1 1 I
|
||||
X R2 43 -1250 1750 300 R 50 50 1 1 I
|
||||
X GND 14 -250 -1850 300 U 50 50 1 1 W
|
||||
X CLOCK 24 -1250 -1350 300 R 50 50 1 1 I
|
||||
X IOR 34 1250 800 300 L 50 50 1 1 I
|
||||
X R3 44 -1250 1650 300 R 50 50 1 1 I
|
||||
X GND 15 -150 -1850 300 U 50 50 1 1 W
|
||||
X GND 25 -50 -1850 300 U 50 50 1 1 W
|
||||
X COMP 35 550 -1850 300 U 50 50 1 1 I
|
||||
X R4 45 -1250 1550 300 R 50 50 1 1 I
|
||||
X B0 16 -1250 50 300 R 50 50 1 1 I
|
||||
X GND 26 50 -1850 300 U 50 50 1 1 W
|
||||
X VREF 36 1250 1350 300 L 50 50 1 1 I
|
||||
X R5 46 -1250 1450 300 R 50 50 1 1 I
|
||||
X B1 17 -1250 -50 300 R 50 50 1 1 I
|
||||
X #IOB 27 1250 100 300 L 50 50 1 1 I
|
||||
X RSET 37 450 -1850 300 U 50 50 1 1 I
|
||||
X R6 47 -1250 1350 300 R 50 50 1 1 I
|
||||
X B2 18 -1250 -150 300 R 50 50 1 1 I
|
||||
X IOB 28 1250 200 300 L 50 50 1 1 I
|
||||
X PSAVEB 38 -1250 -1450 300 R 50 50 1 1 I
|
||||
X R7 48 -1250 1250 300 R 50 50 1 1 I
|
||||
X B3 19 -1250 -250 300 R 50 50 1 1 I
|
||||
X VAA 29 0 2550 300 D 50 50 1 1 I
|
||||
X GND 39 150 -1850 300 U 50 50 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
3
nubus-to-ztex/AT30TS74.bck
Normal file
3
nubus-to-ztex/AT30TS74.bck
Normal file
|
@ -0,0 +1,3 @@
|
|||
EESchema-DOCLIB Version 2.0
|
||||
#
|
||||
#End Doc Library
|
3
nubus-to-ztex/AT30TS74.dcm
Normal file
3
nubus-to-ztex/AT30TS74.dcm
Normal file
|
@ -0,0 +1,3 @@
|
|||
EESchema-DOCLIB Version 2.0
|
||||
#
|
||||
#End Doc Library
|
24
nubus-to-ztex/AT30TS74.lib
Normal file
24
nubus-to-ztex/AT30TS74.lib
Normal file
|
@ -0,0 +1,24 @@
|
|||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# AT30TS74
|
||||
#
|
||||
DEF AT30TS74 U 0 40 Y Y 1 F N
|
||||
F0 "U" 0 0 50 H V C CNN
|
||||
F1 "AT30TS74" 0 0 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -100 -100 350 -500 0 1 0 N
|
||||
X SDA 1 -200 -150 100 R 50 50 1 1 B
|
||||
X SCL 2 -200 -250 100 R 50 50 1 1 I
|
||||
X ALERT 3 -200 -350 100 R 50 50 1 1 O
|
||||
X GND 4 -200 -450 100 R 50 50 1 1 P
|
||||
X A2 5 450 -450 100 L 50 50 1 1 I
|
||||
X A1 6 450 -350 100 L 50 50 1 1 I
|
||||
X A0 7 450 -250 100 L 50 50 1 1 I
|
||||
X VCC 8 450 -150 100 L 50 50 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
871
nubus-to-ztex/B2B.sch
Normal file
871
nubus-to-ztex/B2B.sch
Normal file
|
@ -0,0 +1,871 @@
|
|||
EESchema Schematic File Version 4
|
||||
LIBS:nubus-to-ztex-cache
|
||||
EELAYER 26 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 2 7
|
||||
Title "sbus-to-ztex B2B connector"
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L ztex_AB:ZTEX_AB JAB1
|
||||
U 1 1 5F676E85
|
||||
P 1800 2650
|
||||
AR Path="/5F676E85" Ref="JAB1" Part="1"
|
||||
AR Path="/5F67E4B9/5F676E85" Ref="JAB1" Part="1"
|
||||
AR Path="/618E8C75/5F676E85" Ref="JAB1" Part="1"
|
||||
F 0 "JAB1" H 1825 4375 50 0000 C CNN
|
||||
F 1 "ZTEX_AB-ztex_AB" H 1825 4284 50 0000 C CNN
|
||||
F 2 "For_SeeedStudio:PinHeader_2x32_P2.54mm_Vertical_For_SeeedStudio" H 1800 2650 50 0001 C CNN
|
||||
F 3 "" H 1800 2650 50 0001 C CNN
|
||||
F 4 "10-89-7642" H 1800 2650 50 0001 C CNN "MPN"
|
||||
F 5 "https://www2.mouser.com/ProductDetail/Molex/10-89-7642?qs=%2Fha2pyFadugCxzQFZUdvioDcljDVidgd4vXrOFuSRYM%3D" H 1800 2650 50 0001 C CNN "URL"
|
||||
1 1800 2650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+5V #PWR0101
|
||||
U 1 1 5F677F4B
|
||||
P 2400 1000
|
||||
F 0 "#PWR0101" H 2400 850 50 0001 C CNN
|
||||
F 1 "+5V" H 2415 1173 50 0000 C CNN
|
||||
F 2 "" H 2400 1000 50 0001 C CNN
|
||||
F 3 "" H 2400 1000 50 0001 C CNN
|
||||
1 2400 1000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Notes 9950 6500 0 50 ~ 0
|
||||
Clock capable inputs (MRCC and SRCC, MRCC are multi-domain)\nFor 2.13:\nB9 G16~IO_L13N_T2_MRCC_15 G16\nB10 H16~IO_L13P_T2_MRCC_15 H16\nB11 F16~IO_L14N_T2_SRCC_15 F16\nB12 F15~IO_L14P_T2_SRCC_15 F15\nA19 E16~IO_L11N_T1_SRCC_15 E16\nB19 E15~IO_L11P_T1_SRCC_15 E15\nA22 C15~IO_L12N_T1_MRCC_15 C15\nB22 D15~IO_L12P_T1_MRCC_15 D15\nD8 T5~IO_L12P_T1_MRCC_34 T5\nD9 T4~IO_L12N_T1_MRCC_34 T4\nD14 T3~IO_L11N_T1_SRCC_34 T3\nD15 R3~IO_L11P_T1_SRCC_34 R3\nD19 P5~IO_L13N_T2_MRCC_34 P5\nD20 N5~IO_L13P_T2_MRCC_34 N5\nD21 P4~IO_L14P_T2_SRCC_34 P4\nD22 P3~IO_L14N_T2_SRCC_34 P3\n\nUnfortunately various 2.1x modules have different clock assignment. B22 hsould be a P-side MRCC for 2.14 (perhaps 2.18), but is a n-side SRCC on 2.16 so not usable there.
|
||||
Wire Wire Line
|
||||
1450 2550 1450 2750
|
||||
Wire Wire Line
|
||||
7150 2650 7150 2850
|
||||
Wire Wire Line
|
||||
7150 2850 6700 2850
|
||||
$Comp
|
||||
L Connector:Conn_01x06_Male J2
|
||||
U 1 1 5F69129B
|
||||
P 9250 850
|
||||
F 0 "J2" H 9356 1228 50 0000 C CNN
|
||||
F 1 "Conn_01x06_Male" H 9356 1137 50 0000 C CNN
|
||||
F 2 "For_SeeedStudio:PinHeader_1x06_P2.54mm_Horizontal_For_SeeedStudio" H 9250 850 50 0001 C CNN
|
||||
F 3 "~" H 9250 850 50 0001 C CNN
|
||||
F 4 "22-28-8060" H 9250 850 50 0001 C CNN "MPN-ALT"
|
||||
F 5 "PZ254R-11-06P" H 9250 850 50 0001 C CNN "MPN"
|
||||
F 6 "https://www2.mouser.com/ProductDetail/Molex/22-28-8060?qs=4XSMV6Twtb2rYD%2F%2F316gfQ==" H 9250 850 50 0001 C CNN "URL-ALT"
|
||||
F 7 "https://lcsc.com/product-detail/Pin-Header-Female-Header_XFCN-PZ254R-11-06P_C492414.html" H 9250 850 50 0001 C CNN "URL"
|
||||
1 9250 850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0103
|
||||
U 1 1 5F6913A1
|
||||
P 9950 650
|
||||
F 0 "#PWR0103" H 9950 400 50 0001 C CNN
|
||||
F 1 "GND" H 9955 477 50 0000 C CNN
|
||||
F 2 "" H 9950 650 50 0001 C CNN
|
||||
F 3 "" H 9950 650 50 0001 C CNN
|
||||
1 9950 650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
9450 650 9950 650
|
||||
Wire Wire Line
|
||||
9450 950 7150 950
|
||||
Wire Wire Line
|
||||
7150 950 7150 1350
|
||||
Text Label 9450 1050 0 50 ~ 0
|
||||
TX
|
||||
Text Label 9450 950 0 50 ~ 0
|
||||
RX
|
||||
$Comp
|
||||
L ztex_CD:ZTEX_CD JCD1
|
||||
U 1 1 5F676F65
|
||||
P 7600 2650
|
||||
AR Path="/5F676F65" Ref="JCD1" Part="1"
|
||||
AR Path="/5F67E4B9/5F676F65" Ref="JCD1" Part="1"
|
||||
AR Path="/618E8C75/5F676F65" Ref="JCD1" Part="1"
|
||||
F 0 "JCD1" H 7650 4375 50 0000 C CNN
|
||||
F 1 "ZTEX_CD-ztex_CD" H 7650 4284 50 0000 C CNN
|
||||
F 2 "For_SeeedStudio:PinHeader_2x32_P2.54mm_Vertical_For_SeeedStudio" H 7600 2650 50 0001 C CNN
|
||||
F 3 "" H 7600 2650 50 0001 C CNN
|
||||
F 4 "10-89-7642" H 7600 2650 50 0001 C CNN "MPN"
|
||||
F 5 "https://www2.mouser.com/ProductDetail/Molex/10-89-7642?qs=%2Fha2pyFadugCxzQFZUdvioDcljDVidgd4vXrOFuSRYM%3D" H 7600 2650 50 0001 C CNN "URL"
|
||||
1 7600 2650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Connector_Generic:Conn_02x07_Odd_Even J1
|
||||
U 1 1 5F749BE1
|
||||
P 3150 7250
|
||||
F 0 "J1" H 3200 7767 50 0000 C CNN
|
||||
F 1 "Conn_02x07_Odd_Even" H 3200 7676 50 0000 C CNN
|
||||
F 2 "For_SeeedStudio:PinHeader_2x07_P2.00mm_Vertical_For_SeeedStudio" H 3150 7250 50 0001 C CNN
|
||||
F 3 "https://www.molex.com/pdm_docs/sd/878331420_sd.pdf" H 3150 7250 50 0001 C CNN
|
||||
F 4 "87833-1420" H 3150 7250 50 0001 C CNN "MPN Right Angle"
|
||||
F 5 "A2005WR-N-2X7P-B" H 3150 7250 50 0001 C CNN "MPN-ALT Right Angle"
|
||||
F 6 "https://www2.mouser.com/ProductDetail/Molex/87833-1420?qs=%2Fha2pyFadujYFYCIYI1IvFCvLi7no9WQYzIL%2FpYxKhg%3D" H 3150 7250 50 0001 C CNN "URL Rihgt Angle"
|
||||
F 7 "87831-1420" H 3150 7250 50 0001 C CNN "MPN"
|
||||
F 8 "https://www2.mouser.com/ProductDetail/Molex/87831-1420?qs=QtQX4uD3c2VDCL534TqpVg%3D%3D" H 3150 7250 50 0001 C CNN "URL"
|
||||
1 3150 7250
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text HLabel 1600 4250 0 50 Input ~ 0
|
||||
JTAG_VIO
|
||||
Text HLabel 3450 6950 2 50 Input ~ 0
|
||||
JTAG_VIO
|
||||
Wire Wire Line
|
||||
2950 6950 2950 7050
|
||||
Connection ~ 2950 7050
|
||||
Wire Wire Line
|
||||
2950 7050 2950 7150
|
||||
Connection ~ 2950 7150
|
||||
Wire Wire Line
|
||||
2950 7150 2950 7250
|
||||
Connection ~ 2950 7250
|
||||
Wire Wire Line
|
||||
2950 7250 2950 7350
|
||||
Connection ~ 2950 7350
|
||||
Wire Wire Line
|
||||
2950 7350 2950 7450
|
||||
Connection ~ 2950 7450
|
||||
$Comp
|
||||
L power:GND #PWR0104
|
||||
U 1 1 5F755CF4
|
||||
P 2700 7550
|
||||
F 0 "#PWR0104" H 2700 7300 50 0001 C CNN
|
||||
F 1 "GND" H 2705 7377 50 0000 C CNN
|
||||
F 2 "" H 2700 7550 50 0001 C CNN
|
||||
F 3 "" H 2700 7550 50 0001 C CNN
|
||||
1 2700 7550
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2950 7450 2700 7450
|
||||
Wire Wire Line
|
||||
2700 7450 2700 7550
|
||||
Text Notes 2850 7650 0 50 ~ 0
|
||||
PGND
|
||||
Text Notes 3500 7600 0 50 ~ 0
|
||||
HALT
|
||||
Text Notes 3500 7500 0 50 ~ 0
|
||||
NC
|
||||
Wire Wire Line
|
||||
2950 7550 2950 7450
|
||||
Wire Wire Line
|
||||
7150 2650 7400 2650
|
||||
Wire Wire Line
|
||||
7150 1350 7400 1350
|
||||
Wire Wire Line
|
||||
1450 2550 1600 2550
|
||||
Wire Wire Line
|
||||
1450 2750 1600 2750
|
||||
Wire Wire Line
|
||||
500 2650 1600 2650
|
||||
Wire Wire Line
|
||||
1600 1250 4100 1250
|
||||
Wire Wire Line
|
||||
1600 1250 500 1250
|
||||
Wire Wire Line
|
||||
500 1250 500 2650
|
||||
Connection ~ 1600 1250
|
||||
Connection ~ 500 2650
|
||||
Wire Wire Line
|
||||
500 4450 4100 4450
|
||||
Wire Wire Line
|
||||
4100 4450 4100 4250
|
||||
Wire Wire Line
|
||||
500 2650 500 4450
|
||||
Wire Wire Line
|
||||
4100 4450 5800 4450
|
||||
Wire Wire Line
|
||||
7400 4250 7400 4450
|
||||
Connection ~ 4100 4450
|
||||
Wire Wire Line
|
||||
7400 4450 9900 4450
|
||||
Wire Wire Line
|
||||
9900 4450 9900 4250
|
||||
Connection ~ 7400 4450
|
||||
Wire Wire Line
|
||||
7400 2750 5800 2750
|
||||
Connection ~ 5800 4450
|
||||
Wire Wire Line
|
||||
5800 4450 7400 4450
|
||||
$Comp
|
||||
L power:GND #PWR0105
|
||||
U 1 1 5F8F4D66
|
||||
P 5800 4450
|
||||
F 0 "#PWR0105" H 5800 4200 50 0001 C CNN
|
||||
F 1 "GND" H 5805 4277 50 0000 C CNN
|
||||
F 2 "" H 5800 4450 50 0001 C CNN
|
||||
F 3 "" H 5800 4450 50 0001 C CNN
|
||||
1 5800 4450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4100 2650 5800 2650
|
||||
Wire Wire Line
|
||||
5800 2650 5800 2750
|
||||
Connection ~ 5800 2750
|
||||
Wire Wire Line
|
||||
5800 2750 5800 4450
|
||||
Wire Wire Line
|
||||
7400 1250 5800 1250
|
||||
Wire Wire Line
|
||||
5800 1250 5800 2650
|
||||
Connection ~ 5800 2650
|
||||
Wire Wire Line
|
||||
4100 1250 5800 1250
|
||||
Connection ~ 4100 1250
|
||||
Connection ~ 5800 1250
|
||||
Wire Wire Line
|
||||
9900 1250 11000 1250
|
||||
Connection ~ 9900 4450
|
||||
Wire Wire Line
|
||||
4100 2550 2900 2550
|
||||
Connection ~ 1600 2550
|
||||
Wire Wire Line
|
||||
1600 2750 2900 2750
|
||||
Connection ~ 1600 2750
|
||||
Wire Wire Line
|
||||
4100 1150 4100 1000
|
||||
Wire Wire Line
|
||||
4100 1000 2400 1000
|
||||
Wire Wire Line
|
||||
2400 1000 1600 1000
|
||||
Wire Wire Line
|
||||
1600 1000 1600 1150
|
||||
Connection ~ 2400 1000
|
||||
Wire Wire Line
|
||||
2900 2550 2900 2750
|
||||
Connection ~ 2900 2550
|
||||
Wire Wire Line
|
||||
2900 2550 1600 2550
|
||||
Connection ~ 2900 2750
|
||||
Wire Wire Line
|
||||
2900 2750 4100 2750
|
||||
Wire Wire Line
|
||||
9900 2850 8550 2850
|
||||
Wire Wire Line
|
||||
7400 2850 7150 2850
|
||||
Connection ~ 7400 2850
|
||||
Connection ~ 7150 2850
|
||||
Wire Wire Line
|
||||
7400 2650 8550 2650
|
||||
Connection ~ 7400 2650
|
||||
Wire Wire Line
|
||||
9900 2750 11000 2750
|
||||
Wire Wire Line
|
||||
8550 2650 8550 2850
|
||||
Connection ~ 8550 2650
|
||||
Wire Wire Line
|
||||
8550 2650 9900 2650
|
||||
Connection ~ 8550 2850
|
||||
Wire Wire Line
|
||||
8550 2850 7400 2850
|
||||
Wire Wire Line
|
||||
4100 2550 6250 2550
|
||||
Wire Wire Line
|
||||
6250 2550 6250 2700
|
||||
Wire Wire Line
|
||||
6250 2700 6700 2700
|
||||
Connection ~ 4100 2550
|
||||
Wire Wire Line
|
||||
6700 2700 6700 2850
|
||||
$Comp
|
||||
L power:+3V3 #PWR0106
|
||||
U 1 1 5F90D7B8
|
||||
P 6250 2550
|
||||
F 0 "#PWR0106" H 6250 2400 50 0001 C CNN
|
||||
F 1 "+3V3" H 6265 2723 50 0000 C CNN
|
||||
F 2 "" H 6250 2550 50 0001 C CNN
|
||||
F 3 "" H 6250 2550 50 0001 C CNN
|
||||
1 6250 2550
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 6250 2550
|
||||
Wire Wire Line
|
||||
11000 2750 11000 4450
|
||||
Wire Wire Line
|
||||
11000 4450 9900 4450
|
||||
$Comp
|
||||
L power:GND #PWR0107
|
||||
U 1 1 5F912C94
|
||||
P 11000 4450
|
||||
F 0 "#PWR0107" H 11000 4200 50 0001 C CNN
|
||||
F 1 "GND" H 11005 4277 50 0000 C CNN
|
||||
F 2 "" H 11000 4450 50 0001 C CNN
|
||||
F 3 "" H 11000 4450 50 0001 C CNN
|
||||
1 11000 4450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 11000 4450
|
||||
$Comp
|
||||
L power:GND #PWR0108
|
||||
U 1 1 5F912D7C
|
||||
P 500 4450
|
||||
F 0 "#PWR0108" H 500 4200 50 0001 C CNN
|
||||
F 1 "GND" H 505 4277 50 0000 C CNN
|
||||
F 2 "" H 500 4450 50 0001 C CNN
|
||||
F 3 "" H 500 4450 50 0001 C CNN
|
||||
1 500 4450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 500 4450
|
||||
Wire Wire Line
|
||||
10200 1050 10200 1350
|
||||
Wire Wire Line
|
||||
10200 1350 9900 1350
|
||||
Wire Wire Line
|
||||
9450 1050 10200 1050
|
||||
Text GLabel 4100 2050 2 50 Input Italic 0
|
||||
~CLK_3V3
|
||||
Text GLabel 1600 1350 0 50 Input ~ 0
|
||||
~RQST_3V3
|
||||
Text GLabel 4100 1350 2 50 Input ~ 0
|
||||
~NMRQ_3V3
|
||||
Text GLabel 1600 1550 0 50 Input ~ 0
|
||||
~START_3V3
|
||||
Text GLabel 4100 1550 2 50 Input ~ 0
|
||||
~ACK_3V3
|
||||
Text GLabel 1600 2950 0 50 Input ~ 0
|
||||
~AD21_3V3
|
||||
Text GLabel 4100 2950 2 50 Input ~ 0
|
||||
~AD20_3V3
|
||||
Text GLabel 1600 2850 0 50 Input ~ 0
|
||||
~AD23_3V3
|
||||
Text GLabel 4100 2850 2 50 Input ~ 0
|
||||
~AD22_3V3
|
||||
Text GLabel 1600 2350 0 50 Input ~ 0
|
||||
~AD25_3V3
|
||||
Text GLabel 4100 2450 2 50 Input ~ 0
|
||||
~AD24_3V3
|
||||
Text GLabel 1600 2250 0 50 Input ~ 0
|
||||
~AD27_3V3
|
||||
Text GLabel 4100 2350 2 50 Input ~ 0
|
||||
~AD26_3V3
|
||||
Text GLabel 1600 2150 0 50 Input ~ 0
|
||||
~AD29_3V3
|
||||
Text GLabel 4100 2250 2 50 Input ~ 0
|
||||
~AD28_3V3
|
||||
Text GLabel 1600 2050 0 50 Input ~ 0
|
||||
~AD31_3V3
|
||||
Text GLabel 4100 2150 2 50 Input ~ 0
|
||||
~AD30_3V3
|
||||
Text GLabel 1600 1950 0 50 Input ~ 0
|
||||
~RESET_3V3
|
||||
Text GLabel 4100 1450 2 50 Input ~ 0
|
||||
~TM1_3V3
|
||||
Text GLabel 1600 1450 0 50 Input ~ 0
|
||||
~TM0_3V3
|
||||
Text GLabel 1600 3950 0 50 Input ~ 0
|
||||
~AD1_3V3
|
||||
Text GLabel 4100 3950 2 50 Input ~ 0
|
||||
~AD0_3V3
|
||||
Text GLabel 1600 3850 0 50 Input ~ 0
|
||||
~AD3_3V3
|
||||
Text GLabel 4100 3850 2 50 Input ~ 0
|
||||
~AD2_3V3
|
||||
Text GLabel 1600 3750 0 50 Input ~ 0
|
||||
~AD5_3V3
|
||||
Text GLabel 4100 3750 2 50 Input ~ 0
|
||||
~AD4_3V3
|
||||
Text GLabel 1600 3650 0 50 Input ~ 0
|
||||
~AD7_3V3
|
||||
Text GLabel 4100 3650 2 50 Input ~ 0
|
||||
~AD6_3V3
|
||||
Text GLabel 1600 3550 0 50 Input ~ 0
|
||||
~AD9_3V3
|
||||
Text GLabel 4100 3550 2 50 Input ~ 0
|
||||
~AD8_3V3
|
||||
Text GLabel 1600 3450 0 50 Input ~ 0
|
||||
~AD11_3V3
|
||||
Text GLabel 4100 3450 2 50 Input ~ 0
|
||||
~AD10_3V3
|
||||
Text GLabel 1600 3350 0 50 Input ~ 0
|
||||
~AD13_3V3
|
||||
Text GLabel 4100 3350 2 50 Input ~ 0
|
||||
~AD12_3V3
|
||||
Text GLabel 1600 3250 0 50 Input ~ 0
|
||||
~AD15_3V3
|
||||
Text GLabel 4100 3250 2 50 Input ~ 0
|
||||
~AD14_3V3
|
||||
Text GLabel 1600 3150 0 50 Input ~ 0
|
||||
~AD17_3V3
|
||||
Text GLabel 4100 3150 2 50 Input ~ 0
|
||||
~AD16_3V3
|
||||
Text GLabel 1600 3050 0 50 Input ~ 0
|
||||
~AD19_3V3
|
||||
Text GLabel 4100 3050 2 50 Input ~ 0
|
||||
~AD18_3V3
|
||||
Text GLabel 1600 2450 0 39 Input ~ 8
|
||||
NUBUS_OE
|
||||
Text GLabel 9900 2950 2 50 Input ~ 0
|
||||
FPGA_R0
|
||||
Text GLabel 9900 3050 2 50 Input ~ 0
|
||||
FPGA_R1
|
||||
Text GLabel 9900 3150 2 50 Input ~ 0
|
||||
FPGA_R2
|
||||
Text GLabel 9900 3250 2 50 Input ~ 0
|
||||
FPGA_R3
|
||||
Text GLabel 9900 3350 2 50 Input ~ 0
|
||||
FPGA_R4
|
||||
Text GLabel 9900 3450 2 50 Input ~ 0
|
||||
FPGA_R5
|
||||
Text GLabel 9900 3550 2 50 Input ~ 0
|
||||
FPGA_R6
|
||||
Text GLabel 9900 3650 2 50 Input ~ 0
|
||||
FPGA_R7
|
||||
Text GLabel 9900 3750 2 50 Input ~ 0
|
||||
FPGA_G0
|
||||
Text GLabel 9900 3850 2 50 Input ~ 0
|
||||
FPGA_G1
|
||||
Text GLabel 9900 3950 2 50 Input ~ 0
|
||||
FPGA_G2
|
||||
Text GLabel 9900 4050 2 50 Input ~ 0
|
||||
FPGA_G3
|
||||
Text GLabel 7400 4050 0 50 Input ~ 0
|
||||
FPGA_G4
|
||||
Text GLabel 7400 3950 0 50 Input ~ 0
|
||||
FPGA_G5
|
||||
Text GLabel 7400 3850 0 50 Input ~ 0
|
||||
FPGA_G6
|
||||
Text GLabel 7400 3750 0 50 Input ~ 0
|
||||
FPGA_G7
|
||||
Text GLabel 7400 3650 0 50 Input ~ 0
|
||||
FPGA_B0
|
||||
Text GLabel 7400 3550 0 50 Input ~ 0
|
||||
FPGA_B1
|
||||
Text GLabel 7400 3450 0 50 Input ~ 0
|
||||
FPGA_B2
|
||||
Text GLabel 7400 3350 0 50 Input ~ 0
|
||||
FPGA_B3
|
||||
Text GLabel 7400 3250 0 50 Input ~ 0
|
||||
FPGA_B4
|
||||
Text GLabel 7400 3150 0 50 Input ~ 0
|
||||
FPGA_B5
|
||||
Text GLabel 7400 3050 0 50 Input ~ 0
|
||||
FPGA_B6
|
||||
Text GLabel 7400 2950 0 50 Input ~ 0
|
||||
FPGA_B7
|
||||
Text GLabel 7400 2550 0 50 Input ~ 0
|
||||
FPGA_VGA_CLK
|
||||
Text GLabel 9900 2050 2 50 Input ~ 0
|
||||
FPGA_VGA_HS
|
||||
Text GLabel 9900 2150 2 50 Input ~ 0
|
||||
FPGA_VGA_VS
|
||||
Wire Wire Line
|
||||
11000 1250 11000 2750
|
||||
Connection ~ 11000 2750
|
||||
Text GLabel 9900 1550 2 50 Input ~ 0
|
||||
~ID1_3V3
|
||||
Text GLabel 7400 1550 0 50 Input ~ 0
|
||||
~ID0_3V3
|
||||
Text GLabel 7400 1450 0 50 Input ~ 0
|
||||
~ID3_3V3
|
||||
Text GLabel 7400 2150 0 50 Input ~ 0
|
||||
HDMI_CLK+
|
||||
Text GLabel 7400 2250 0 50 Input ~ 0
|
||||
HDMI_CLK-
|
||||
Text GLabel 9900 2350 2 50 Input ~ 0
|
||||
HDMI_D0+
|
||||
Text GLabel 9900 2250 2 50 Input ~ 0
|
||||
HDMI_D0-
|
||||
Text GLabel 7400 2450 0 50 Input ~ 0
|
||||
HDMI_D1+
|
||||
Text GLabel 7400 2350 0 50 Input ~ 0
|
||||
HDMI_D1-
|
||||
Text GLabel 9900 2550 2 50 Input ~ 0
|
||||
HDMI_D2+
|
||||
Text GLabel 9900 2450 2 50 Input ~ 0
|
||||
HDMI_D2-
|
||||
Text GLabel 7400 1750 0 50 Input ~ 0
|
||||
HDMI_HPD_A
|
||||
Text GLabel 7400 2050 0 50 Input ~ 0
|
||||
HDMI_CEC_A
|
||||
Text GLabel 7400 1950 0 50 Input ~ 0
|
||||
HDMI_SCL_A
|
||||
Text GLabel 7400 1850 0 50 Input ~ 0
|
||||
HDMI_SDA_A
|
||||
Wire Wire Line
|
||||
850 5900 700 5900
|
||||
Wire Wire Line
|
||||
700 5900 700 6100
|
||||
Wire Wire Line
|
||||
1150 5900 1550 5900
|
||||
$Comp
|
||||
L Device:R R?
|
||||
U 1 1 61B5DFBC
|
||||
P 1700 5900
|
||||
AR Path="/5F6B165A/61B5DFBC" Ref="R?" Part="1"
|
||||
AR Path="/5F67E4B9/61B5DFBC" Ref="R?" Part="1"
|
||||
AR Path="/618E8C75/61B5DFBC" Ref="R7" Part="1"
|
||||
F 0 "R7" V 1780 5900 50 0000 C CNN
|
||||
F 1 "549" V 1700 5900 50 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0603_1608Metric" V 1630 5900 50 0001 C CNN
|
||||
F 3 "" H 1700 5900 50 0000 C CNN
|
||||
F 4 "0603WAF5490T5E" V 1700 5900 50 0001 C CNN "MPN"
|
||||
F 5 "https://lcsc.com/product-detail/Chip-Resistor-Surface-Mount_UNI-ROYAL-Uniroyal-Elec-0603WAF5490T5E_C23079.html" V 1700 5900 50 0001 C CNN "URL"
|
||||
1 1700 5900
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:LED_ALT D?
|
||||
U 1 1 61B5DFCC
|
||||
P 1000 5900
|
||||
AR Path="/5F6B165A/61B5DFCC" Ref="D?" Part="1"
|
||||
AR Path="/5F67E4B9/61B5DFCC" Ref="D?" Part="1"
|
||||
AR Path="/618E8C75/61B5DFCC" Ref="D2" Part="1"
|
||||
F 0 "D2" H 1000 6000 50 0000 C CNN
|
||||
F 1 "RED" H 650 5900 50 0000 R CNN
|
||||
F 2 "LED_SMD:LED_0805_2012Metric" H 1000 5900 50 0001 C CNN
|
||||
F 3 "https://optoelectronics.liteon.com/upload/download/DS-22-99-0150/LTST-C170KRKT.pdf" H 1000 5900 50 0001 C CNN
|
||||
F 4 "www.liteon.com" H 1000 5900 60 0001 C CNN "MNF1_URL"
|
||||
F 5 "LTST-C170KRKT" H 1000 5900 60 0001 C CNN "MPN"
|
||||
F 6 "https://www.lcsc.com/product-detail/Light-Emitting-Diodes-LED_Lite-On-LTST-C170KRKT_C94868.html" H 1000 5900 50 0001 C CNN "URL"
|
||||
1 1000 5900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0175
|
||||
U 1 1 61B5DFD3
|
||||
P 700 6100
|
||||
F 0 "#PWR0175" H 700 5850 50 0001 C CNN
|
||||
F 1 "GND" H 705 5927 50 0000 C CNN
|
||||
F 2 "" H 700 6100 50 0001 C CNN
|
||||
F 3 "" H 700 6100 50 0001 C CNN
|
||||
1 700 6100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text GLabel 1850 5900 2 60 Input ~ 12
|
||||
LED0
|
||||
Wire Wire Line
|
||||
850 6400 700 6400
|
||||
Wire Wire Line
|
||||
700 6400 700 6600
|
||||
Wire Wire Line
|
||||
1150 6400 1550 6400
|
||||
$Comp
|
||||
L Device:R R?
|
||||
U 1 1 61B5F3F5
|
||||
P 1700 6400
|
||||
AR Path="/5F6B165A/61B5F3F5" Ref="R?" Part="1"
|
||||
AR Path="/5F67E4B9/61B5F3F5" Ref="R?" Part="1"
|
||||
AR Path="/618E8C75/61B5F3F5" Ref="R8" Part="1"
|
||||
F 0 "R8" V 1780 6400 50 0000 C CNN
|
||||
F 1 "549" V 1700 6400 50 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0603_1608Metric" V 1630 6400 50 0001 C CNN
|
||||
F 3 "" H 1700 6400 50 0000 C CNN
|
||||
F 4 "0603WAF5490T5E" V 1700 6400 50 0001 C CNN "MPN"
|
||||
F 5 "https://lcsc.com/product-detail/Chip-Resistor-Surface-Mount_UNI-ROYAL-Uniroyal-Elec-0603WAF5490T5E_C23079.html" V 1700 6400 50 0001 C CNN "URL"
|
||||
1 1700 6400
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:LED_ALT D?
|
||||
U 1 1 61B5F405
|
||||
P 1000 6400
|
||||
AR Path="/5F6B165A/61B5F405" Ref="D?" Part="1"
|
||||
AR Path="/5F67E4B9/61B5F405" Ref="D?" Part="1"
|
||||
AR Path="/618E8C75/61B5F405" Ref="D3" Part="1"
|
||||
F 0 "D3" H 1000 6500 50 0000 C CNN
|
||||
F 1 "RED" H 650 6400 50 0000 R CNN
|
||||
F 2 "LED_SMD:LED_0805_2012Metric" H 1000 6400 50 0001 C CNN
|
||||
F 3 "https://optoelectronics.liteon.com/upload/download/DS-22-99-0150/LTST-C170KRKT.pdf" H 1000 6400 50 0001 C CNN
|
||||
F 4 "www.liteon.com" H 1000 6400 60 0001 C CNN "MNF1_URL"
|
||||
F 5 "LTST-C170KRKT" H 1000 6400 60 0001 C CNN "MPN"
|
||||
F 6 "https://www.lcsc.com/product-detail/Light-Emitting-Diodes-LED_Lite-On-LTST-C170KRKT_C94868.html" H 1000 6400 50 0001 C CNN "URL"
|
||||
1 1000 6400
|
||||
1 0 0 -1
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||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0176
|
||||
U 1 1 61B5F40C
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||||
P 700 6600
|
||||
F 0 "#PWR0176" H 700 6350 50 0001 C CNN
|
||||
F 1 "GND" H 705 6427 50 0000 C CNN
|
||||
F 2 "" H 700 6600 50 0001 C CNN
|
||||
F 3 "" H 700 6600 50 0001 C CNN
|
||||
1 700 6600
|
||||
1 0 0 -1
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||||
$EndComp
|
||||
Text GLabel 1850 6400 2 60 Input ~ 12
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||||
LED1
|
||||
Wire Wire Line
|
||||
850 6900 700 6900
|
||||
Wire Wire Line
|
||||
700 6900 700 7100
|
||||
Wire Wire Line
|
||||
1150 6900 1550 6900
|
||||
$Comp
|
||||
L Device:R R?
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||||
U 1 1 61B60A5F
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||||
P 1700 6900
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||||
AR Path="/5F6B165A/61B60A5F" Ref="R?" Part="1"
|
||||
AR Path="/5F67E4B9/61B60A5F" Ref="R?" Part="1"
|
||||
AR Path="/618E8C75/61B60A5F" Ref="R9" Part="1"
|
||||
F 0 "R9" V 1780 6900 50 0000 C CNN
|
||||
F 1 "549" V 1700 6900 50 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0603_1608Metric" V 1630 6900 50 0001 C CNN
|
||||
F 3 "" H 1700 6900 50 0000 C CNN
|
||||
F 4 "0603WAF5490T5E" V 1700 6900 50 0001 C CNN "MPN"
|
||||
F 5 "https://lcsc.com/product-detail/Chip-Resistor-Surface-Mount_UNI-ROYAL-Uniroyal-Elec-0603WAF5490T5E_C23079.html" V 1700 6900 50 0001 C CNN "URL"
|
||||
1 1700 6900
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:LED_ALT D?
|
||||
U 1 1 61B60A6F
|
||||
P 1000 6900
|
||||
AR Path="/5F6B165A/61B60A6F" Ref="D?" Part="1"
|
||||
AR Path="/5F67E4B9/61B60A6F" Ref="D?" Part="1"
|
||||
AR Path="/618E8C75/61B60A6F" Ref="D4" Part="1"
|
||||
F 0 "D4" H 1000 7000 50 0000 C CNN
|
||||
F 1 "RED" H 650 6900 50 0000 R CNN
|
||||
F 2 "LED_SMD:LED_0805_2012Metric" H 1000 6900 50 0001 C CNN
|
||||
F 3 "https://optoelectronics.liteon.com/upload/download/DS-22-99-0150/LTST-C170KRKT.pdf" H 1000 6900 50 0001 C CNN
|
||||
F 4 "www.liteon.com" H 1000 6900 60 0001 C CNN "MNF1_URL"
|
||||
F 5 "LTST-C170KRKT" H 1000 6900 60 0001 C CNN "MPN"
|
||||
F 6 "https://www.lcsc.com/product-detail/Light-Emitting-Diodes-LED_Lite-On-LTST-C170KRKT_C94868.html" H 1000 6900 50 0001 C CNN "URL"
|
||||
1 1000 6900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0177
|
||||
U 1 1 61B60A76
|
||||
P 700 7100
|
||||
F 0 "#PWR0177" H 700 6850 50 0001 C CNN
|
||||
F 1 "GND" H 705 6927 50 0000 C CNN
|
||||
F 2 "" H 700 7100 50 0001 C CNN
|
||||
F 3 "" H 700 7100 50 0001 C CNN
|
||||
1 700 7100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text GLabel 1850 6900 2 60 Input ~ 12
|
||||
LED2
|
||||
Wire Wire Line
|
||||
850 7400 700 7400
|
||||
Wire Wire Line
|
||||
700 7400 700 7600
|
||||
Wire Wire Line
|
||||
1150 7400 1550 7400
|
||||
$Comp
|
||||
L Device:R R?
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||||
U 1 1 61B62352
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||||
P 1700 7400
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||||
AR Path="/5F6B165A/61B62352" Ref="R?" Part="1"
|
||||
AR Path="/5F67E4B9/61B62352" Ref="R?" Part="1"
|
||||
AR Path="/618E8C75/61B62352" Ref="R10" Part="1"
|
||||
F 0 "R10" V 1780 7400 50 0000 C CNN
|
||||
F 1 "549" V 1700 7400 50 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0603_1608Metric" V 1630 7400 50 0001 C CNN
|
||||
F 3 "" H 1700 7400 50 0000 C CNN
|
||||
F 4 "0603WAF5490T5E" V 1700 7400 50 0001 C CNN "MPN"
|
||||
F 5 "https://lcsc.com/product-detail/Chip-Resistor-Surface-Mount_UNI-ROYAL-Uniroyal-Elec-0603WAF5490T5E_C23079.html" V 1700 7400 50 0001 C CNN "URL"
|
||||
1 1700 7400
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:LED_ALT D?
|
||||
U 1 1 61B62362
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||||
P 1000 7400
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||||
AR Path="/5F6B165A/61B62362" Ref="D?" Part="1"
|
||||
AR Path="/5F67E4B9/61B62362" Ref="D?" Part="1"
|
||||
AR Path="/618E8C75/61B62362" Ref="D5" Part="1"
|
||||
F 0 "D5" H 1000 7500 50 0000 C CNN
|
||||
F 1 "RED" H 650 7400 50 0000 R CNN
|
||||
F 2 "LED_SMD:LED_0805_2012Metric" H 1000 7400 50 0001 C CNN
|
||||
F 3 "https://optoelectronics.liteon.com/upload/download/DS-22-99-0150/LTST-C170KRKT.pdf" H 1000 7400 50 0001 C CNN
|
||||
F 4 "www.liteon.com" H 1000 7400 60 0001 C CNN "MNF1_URL"
|
||||
F 5 "LTST-C170KRKT" H 1000 7400 60 0001 C CNN "MPN"
|
||||
F 6 "https://www.lcsc.com/product-detail/Light-Emitting-Diodes-LED_Lite-On-LTST-C170KRKT_C94868.html" H 1000 7400 50 0001 C CNN "URL"
|
||||
1 1000 7400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0178
|
||||
U 1 1 61B62369
|
||||
P 700 7600
|
||||
F 0 "#PWR0178" H 700 7350 50 0001 C CNN
|
||||
F 1 "GND" H 705 7427 50 0000 C CNN
|
||||
F 2 "" H 700 7600 50 0001 C CNN
|
||||
F 3 "" H 700 7600 50 0001 C CNN
|
||||
1 700 7600
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text GLabel 1850 7400 2 60 Input ~ 12
|
||||
LED3
|
||||
Text GLabel 9900 1650 2 60 Input ~ 12
|
||||
LED0
|
||||
Text GLabel 9900 1750 2 60 Input ~ 12
|
||||
LED1
|
||||
Text GLabel 9900 1850 2 60 Input ~ 12
|
||||
LED2
|
||||
Text GLabel 9900 1950 2 60 Input ~ 12
|
||||
LED3
|
||||
Text GLabel 1600 4050 0 50 Input ~ 0
|
||||
USBH0_D+
|
||||
Text GLabel 4100 4050 2 50 Input ~ 0
|
||||
USBH0_D-
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||||
$Comp
|
||||
L Device:C C?
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||||
U 1 1 61B7E3FB
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||||
P 2350 6050
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||||
AR Path="/618F532C/61B7E3FB" Ref="C?" Part="1"
|
||||
AR Path="/618E8C75/61B7E3FB" Ref="C19" Part="1"
|
||||
F 0 "C19" H 2375 6150 50 0000 L CNN
|
||||
F 1 "100nF" H 2375 5950 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric" H 2388 5900 50 0001 C CNN
|
||||
F 3 "" H 2350 6050 50 0000 C CNN
|
||||
F 4 "www.yageo.com" H 2350 6050 50 0001 C CNN "MNF1_URL"
|
||||
F 5 "CC0603KRX7R8BB104" H 2350 6050 50 0001 C CNN "MPN"
|
||||
F 6 "603-CC603KRX7R8BB104" H 2350 6050 50 0001 C CNN "Mouser"
|
||||
F 7 "?" H 2350 6050 50 0001 C CNN "Digikey"
|
||||
F 8 "?" H 2350 6050 50 0001 C CNN "LCSC"
|
||||
F 9 "?" H 2350 6050 50 0001 C CNN "Koncar"
|
||||
F 10 "TB" H 2350 6050 50 0001 C CNN "Side"
|
||||
F 11 "https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_YAGEO-CC0603KRX7R8BB104_C92490.html" H 2350 6050 50 0001 C CNN "URL"
|
||||
1 2350 6050
|
||||
1 0 0 -1
|
||||
$EndComp
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||||
$Comp
|
||||
L power:GND #PWR0185
|
||||
U 1 1 61B81B34
|
||||
P 2350 6200
|
||||
F 0 "#PWR0185" H 2350 5950 50 0001 C CNN
|
||||
F 1 "GND" H 2355 6027 50 0000 C CNN
|
||||
F 2 "" H 2350 6200 50 0001 C CNN
|
||||
F 3 "" H 2350 6200 50 0001 C CNN
|
||||
1 2350 6200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+3V3 #PWR0186
|
||||
U 1 1 61B81BD5
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||||
P 2350 5900
|
||||
F 0 "#PWR0186" H 2350 5750 50 0001 C CNN
|
||||
F 1 "+3V3" H 2365 6073 50 0000 C CNN
|
||||
F 2 "" H 2350 5900 50 0001 C CNN
|
||||
F 3 "" H 2350 5900 50 0001 C CNN
|
||||
1 2350 5900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text GLabel 4750 7350 2 50 Input ~ 0
|
||||
CPLD_JTAG_TDI
|
||||
Text GLabel 3450 7050 2 50 Input ~ 0
|
||||
FPGA_JTAG_TMS
|
||||
Text GLabel 3450 7150 2 50 Input ~ 0
|
||||
FPGA_JTAG_TCK
|
||||
Text GLabel 4750 7250 2 50 Input ~ 0
|
||||
CPLD_JTAG_TDO
|
||||
Text GLabel 9900 4150 2 50 Input ~ 0
|
||||
FPGA_JTAG_TMS
|
||||
Text GLabel 4100 4150 2 50 Input ~ 0
|
||||
FPGA_JTAG_TCK
|
||||
Text GLabel 1600 1650 0 39 Input ~ 8
|
||||
GRANT
|
||||
Text GLabel 4100 1650 2 39 Input ~ 8
|
||||
ARB
|
||||
Text GLabel 9900 1450 2 50 Input ~ 0
|
||||
~ID2_3V3
|
||||
Text GLabel 1600 1850 0 39 Input ~ 8
|
||||
NUBUS_MASTER_DIR
|
||||
Text GLabel 4100 1750 2 39 Input ~ 8
|
||||
fpga_to_cpld_clk
|
||||
Text GLabel 4100 1950 2 39 Input ~ 8
|
||||
NUBUS_AD_DIR
|
||||
Text GLabel 7400 4150 0 50 Input ~ 0
|
||||
FPGA_JTAG_TDO
|
||||
Text GLabel 1600 4150 0 50 Input ~ 0
|
||||
FPGA_JTAG_TDI
|
||||
Text GLabel 3450 7350 2 50 Input ~ 0
|
||||
FPGA_JTAG_TDI
|
||||
Text GLabel 3450 7250 2 50 Input ~ 0
|
||||
FPGA_JTAG_TDO
|
||||
Text GLabel 4750 7050 2 50 Input ~ 0
|
||||
CPLD_JTAG_TMS
|
||||
Text GLabel 4750 7150 2 50 Input ~ 0
|
||||
CPLD_JTAG_TCK
|
||||
$Comp
|
||||
L Connector_Generic:Conn_02x07_Odd_Even J8
|
||||
U 1 1 61CD2AB9
|
||||
P 4450 7250
|
||||
F 0 "J8" H 4500 7767 50 0000 C CNN
|
||||
F 1 "Conn_02x07_Odd_Even" H 4500 7676 50 0000 C CNN
|
||||
F 2 "For_SeeedStudio:PinHeader_2x07_P2.00mm_Vertical_For_SeeedStudio" H 4450 7250 50 0001 C CNN
|
||||
F 3 "https://www.molex.com/pdm_docs/sd/878331420_sd.pdf" H 4450 7250 50 0001 C CNN
|
||||
F 4 "87833-1420" H 4450 7250 50 0001 C CNN "MPN Right Angle"
|
||||
F 5 "A2005WR-N-2X7P-B" H 4450 7250 50 0001 C CNN "MPN-ALT Right Angle"
|
||||
F 6 "https://www2.mouser.com/ProductDetail/Molex/87833-1420?qs=%2Fha2pyFadujYFYCIYI1IvFCvLi7no9WQYzIL%2FpYxKhg%3D" H 4450 7250 50 0001 C CNN "URL Rihgt Angle"
|
||||
F 7 "87831-1420" H 4450 7250 50 0001 C CNN "MPN"
|
||||
F 8 "https://www2.mouser.com/ProductDetail/Molex/87831-1420?qs=QtQX4uD3c2VDCL534TqpVg%3D%3D" H 4450 7250 50 0001 C CNN "URL"
|
||||
1 4450 7250
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4250 7350 4250 7450
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||||
Connection ~ 4250 7450
|
||||
$Comp
|
||||
L power:GND #PWR0193
|
||||
U 1 1 61CD2AC2
|
||||
P 4000 7550
|
||||
F 0 "#PWR0193" H 4000 7300 50 0001 C CNN
|
||||
F 1 "GND" H 4005 7377 50 0000 C CNN
|
||||
F 2 "" H 4000 7550 50 0001 C CNN
|
||||
F 3 "" H 4000 7550 50 0001 C CNN
|
||||
1 4000 7550
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4250 7450 4000 7450
|
||||
Wire Wire Line
|
||||
4000 7450 4000 7550
|
||||
Text Notes 4150 7650 0 50 ~ 0
|
||||
PGND
|
||||
Text Notes 4800 7600 0 50 ~ 0
|
||||
HALT
|
||||
Text Notes 4800 7500 0 50 ~ 0
|
||||
NC
|
||||
Wire Wire Line
|
||||
4250 7550 4250 7450
|
||||
Wire Wire Line
|
||||
4250 7350 4250 7250
|
||||
Connection ~ 4250 7350
|
||||
Wire Wire Line
|
||||
4250 7150 4250 7250
|
||||
Connection ~ 4250 7250
|
||||
Wire Wire Line
|
||||
4250 7050 4250 7150
|
||||
Connection ~ 4250 7150
|
||||
Wire Wire Line
|
||||
4250 6950 4250 7050
|
||||
Connection ~ 4250 7050
|
||||
NoConn ~ 3450 7550
|
||||
NoConn ~ 3450 7450
|
||||
NoConn ~ 4750 7550
|
||||
NoConn ~ 4750 7450
|
||||
$Comp
|
||||
L power:+3V3 #PWR0199
|
||||
U 1 1 61CE94A3
|
||||
P 4750 6950
|
||||
F 0 "#PWR0199" H 4750 6800 50 0001 C CNN
|
||||
F 1 "+3V3" V 4765 7078 50 0000 L CNN
|
||||
F 2 "" H 4750 6950 50 0001 C CNN
|
||||
F 3 "" H 4750 6950 50 0001 C CNN
|
||||
1 4750 6950
|
||||
0 1 1 0
|
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$EndComp
|
||||
Text GLabel 7400 1650 0 39 Input ~ 8
|
||||
tmoen
|
||||
Text GLabel 4100 1850 2 39 Input ~ 8
|
||||
fpga_to_cpld_signal_2
|
||||
Text GLabel 1600 1750 0 39 Input ~ 8
|
||||
fpga_to_cpld_signal
|
||||
$EndSCHEMATC
|
320
nubus-to-ztex/For_SeeedStudio.pretty/ADV7125KSTZ140.kicad_mod
Normal file
320
nubus-to-ztex/For_SeeedStudio.pretty/ADV7125KSTZ140.kicad_mod
Normal file
|
@ -0,0 +1,320 @@
|
|||
(module ST_48_ADI (layer F.Cu)
|
||||
(fp_text reference REF** (at 0 0) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness .15)))
|
||||
)
|
||||
(fp_text value ST_48_ADI (at 0 0) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness .15)))
|
||||
)
|
||||
(fp_text user "Copyright 2021 Accelerated Designs. All rights reserved." (at 0 0) (layer Cmts.User)
|
||||
(effects (font (size .127 .127) (thickness .002)))
|
||||
)
|
||||
(fp_text user "*" (at -5.588 -3.381) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness .15)))
|
||||
)
|
||||
(fp_text user "*" (at -3.2131 -3) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness .15)))
|
||||
)
|
||||
(fp_text user "0.02in/0.5mm" (at 7.6454 -2.5) (layer Dwgs.User)
|
||||
(effects (font (size 1 1) (thickness .15)))
|
||||
)
|
||||
(fp_text user "0.011in/0.279mm" (at 2.75 -7.6454) (layer Dwgs.User)
|
||||
(effects (font (size 1 1) (thickness .15)))
|
||||
)
|
||||
(fp_text user "0.058in/1.473mm" (at 9.1821 -4.2164) (layer Dwgs.User)
|
||||
(effects (font (size 1 1) (thickness .15)))
|
||||
)
|
||||
(fp_text user "0.332in/8.433mm" (at -9.1821 0) (layer Dwgs.User)
|
||||
(effects (font (size 1 1) (thickness .15)))
|
||||
)
|
||||
(fp_text user "0.332in/8.433mm" (at 0 8.9154) (layer Dwgs.User)
|
||||
(effects (font (size 1 1) (thickness .15)))
|
||||
)
|
||||
(fp_text user "*" (at -5.588 -3.381) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness .15)))
|
||||
)
|
||||
(fp_text user "*" (at -3.2131 -3) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness .15)))
|
||||
)
|
||||
(fp_line (start 2.6103 -3.5941) (end 2.8897 -3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start 2.8897 -3.5941) (end 2.8897 -4.5974) (layer F.Fab) (width .1))
|
||||
(fp_line (start 2.8897 -4.5974) (end 2.6103 -4.5974) (layer F.Fab) (width .1))
|
||||
(fp_line (start 2.6103 -4.5974) (end 2.6103 -3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start 2.1103 -3.5941) (end 2.3897 -3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start 2.3897 -3.5941) (end 2.3897 -4.5974) (layer F.Fab) (width .1))
|
||||
(fp_line (start 2.3897 -4.5974) (end 2.1103 -4.5974) (layer F.Fab) (width .1))
|
||||
(fp_line (start 2.1103 -4.5974) (end 2.1103 -3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start 1.6103 -3.5941) (end 1.8897 -3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start 1.8897 -3.5941) (end 1.8897 -4.5974) (layer F.Fab) (width .1))
|
||||
(fp_line (start 1.8897 -4.5974) (end 1.6103 -4.5974) (layer F.Fab) (width .1))
|
||||
(fp_line (start 1.6103 -4.5974) (end 1.6103 -3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start 1.1103 -3.5941) (end 1.3897 -3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start 1.3897 -3.5941) (end 1.3897 -4.5974) (layer F.Fab) (width .1))
|
||||
(fp_line (start 1.3897 -4.5974) (end 1.1103 -4.5974) (layer F.Fab) (width .1))
|
||||
(fp_line (start 1.1103 -4.5974) (end 1.1103 -3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start .6103 -3.5941) (end .8897 -3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start .8897 -3.5941) (end .8897 -4.5974) (layer F.Fab) (width .1))
|
||||
(fp_line (start .8897 -4.5974) (end .6103 -4.5974) (layer F.Fab) (width .1))
|
||||
(fp_line (start .6103 -4.5974) (end .6103 -3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start .1103 -3.5941) (end .3897 -3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start .3897 -3.5941) (end .3897 -4.5974) (layer F.Fab) (width .1))
|
||||
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||||
(fp_line (start -3.5941 3.5941) (end 3.5941 3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start 3.5941 3.5941) (end 3.5941 3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start 3.5941 3.5941) (end 3.5941 -3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start 3.5941 -3.5941) (end 3.5941 -3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start 3.5941 -3.5941) (end -3.5941 -3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start -3.5941 -3.5941) (end -3.5941 -3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start -3.5941 -3.5941) (end -3.5941 3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start -3.5941 3.5941) (end -3.5941 3.5941) (layer F.Fab) (width .1))
|
||||
(fp_line (start 3.22244 3.7211) (end 3.7211 3.7211) (layer F.SilkS) (width .12))
|
||||
(fp_line (start 3.7211 -3.22244) (end 3.7211 -3.7211) (layer F.SilkS) (width .12))
|
||||
(fp_line (start -3.22244 -3.7211) (end -3.7211 -3.7211) (layer F.SilkS) (width .12))
|
||||
(fp_poly (pts (xy -5.461 1.559499) (xy -5.461 1.940499) (xy -5.207 1.940499) (xy -5.207 1.559499)) (layer F.SilkS) (width .1))
|
||||
(fp_poly (pts (xy .559501 5.207) (xy .559501 5.461) (xy .940501 5.461) (xy .940501 5.207)) (layer F.SilkS) (width .1))
|
||||
(fp_poly (pts (xy 5.461 .059499) (xy 5.461 .4405) (xy 5.207 .4405) (xy 5.207 .059499)) (layer F.SilkS) (width .1))
|
||||
(fp_poly (pts (xy 1.0595 -5.207) (xy 1.0595 -5.461) (xy 1.4405 -5.461) (xy 1.4405 -5.207)) (layer F.SilkS) (width .1))
|
||||
(fp_line (start -3.8481 3.8481) (end -3.8481 3.1437) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start -3.8481 3.1437) (end -5.207 3.1437) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start -5.207 3.1437) (end -5.207 -3.1437) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start -5.207 -3.1437) (end -3.8481 -3.1437) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start -3.8481 -3.1437) (end -3.8481 -3.8481) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start -3.8481 -3.8481) (end -3.1437 -3.8481) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start -3.1437 -3.8481) (end -3.1437 -5.207) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start -3.1437 -5.207) (end 3.1437 -5.207) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start 3.1437 -5.207) (end 3.1437 -3.8481) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start 3.1437 -3.8481) (end 3.8481 -3.8481) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start 3.8481 -3.8481) (end 3.8481 -3.1437) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start 3.8481 -3.1437) (end 5.207 -3.1437) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start 5.207 -3.1437) (end 5.207 3.1437) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start 5.207 3.1437) (end 3.8481 3.1437) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start 3.8481 3.1437) (end 3.8481 3.8481) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start 3.8481 3.8481) (end 3.1437 3.8481) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start 3.1437 3.8481) (end 3.1437 5.207) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start 3.1437 5.207) (end -3.1437 5.207) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start -3.1437 5.207) (end -3.1437 3.8481) (layer F.CrtYd) (width .05))
|
||||
(fp_line (start -3.1437 3.8481) (end -3.8481 3.8481) (layer F.CrtYd) (width .05))
|
||||
(fp_circle (center -5.4229 -2.75) (end -5.4229 -2.75) (layer F.CrtYd) (width .05))
|
||||
(pad 1 smd rect (at -4.2164 -2.75 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 2 smd rect (at -4.2164 -2.250001 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 3 smd rect (at -4.2164 -1.749999 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 4 smd rect (at -4.2164 -1.25 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 5 smd rect (at -4.2164 -.750001 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 6 smd rect (at -4.2164 -.25 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 7 smd rect (at -4.2164 .25 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 8 smd rect (at -4.2164 .750001 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 9 smd rect (at -4.2164 1.25 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 10 smd rect (at -4.2164 1.749999 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 11 smd rect (at -4.2164 2.250001 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 12 smd rect (at -4.2164 2.75 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 13 smd rect (at -2.75 4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 14 smd rect (at -2.250001 4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 15 smd rect (at -1.749999 4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 16 smd rect (at -1.25 4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 17 smd rect (at -.750001 4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 18 smd rect (at -.25 4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 19 smd rect (at .25 4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 20 smd rect (at .750001 4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 21 smd rect (at 1.25 4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 22 smd rect (at 1.749999 4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 23 smd rect (at 2.250001 4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 24 smd rect (at 2.75 4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 25 smd rect (at 4.2164 2.75 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 26 smd rect (at 4.2164 2.250001 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 27 smd rect (at 4.2164 1.749999 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 28 smd rect (at 4.2164 1.25 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 29 smd rect (at 4.2164 .750001 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 30 smd rect (at 4.2164 .25 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 31 smd rect (at 4.2164 -.25 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 32 smd rect (at 4.2164 -.750001 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 33 smd rect (at 4.2164 -1.25 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 34 smd rect (at 4.2164 -1.749999 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 35 smd rect (at 4.2164 -2.250001 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 36 smd rect (at 4.2164 -2.75 90) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 37 smd rect (at 2.75 -4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 38 smd rect (at 2.250001 -4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 39 smd rect (at 1.749999 -4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 40 smd rect (at 1.25 -4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 41 smd rect (at .750001 -4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 42 smd rect (at .25 -4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 43 smd rect (at -.25 -4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 44 smd rect (at -.750001 -4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 45 smd rect (at -1.25 -4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 46 smd rect (at -1.749999 -4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 47 smd rect (at -2.250001 -4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 48 smd rect (at -2.75 -4.2164) (size .2794 1.4732) (layers F.Cu F.Paste F.Mask))
|
||||
)
|
|
@ -0,0 +1,188 @@
|
|||
(module DIN41612_C_3x32_Male_Horizontal_THT (layer F.Cu) (tedit 5EAFCB7F)
|
||||
(descr "DIN41612 connector, type C, Horizontal, 3 rows 32 pins wide, https://www.erni-x-press.com/de/downloads/kataloge/englische_kataloge/erni-din41612-iec60603-2-e.pdf")
|
||||
(tags "DIN 41612 IEC 60603 C")
|
||||
(fp_text reference REF** (at -5.08 1) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value DIN41612_C_3x32_Male_Horizontal_THT (at 39.37 7.62) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -4.38 -12.74) (end -4.38 -6.74) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -4.38 -6.74) (end -7.63 -6.74) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -7.63 -6.74) (end -7.63 0) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -7.63 0) (end -2.63 0) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -2.63 0) (end -2.63 -1) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -2.63 -1) (end 81.37 -1) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 81.37 -1) (end 81.37 0) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 81.37 0) (end 86.37 0) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 86.37 0) (end 86.37 -6.74) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 86.37 -6.74) (end 83.12 -6.74) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 83.12 -6.74) (end 83.12 -12.74) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 83.12 -12.74) (end -4.38 -12.74) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -7.89 -5.3) (end -7.89 0.26) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -7.89 0.26) (end -2.37 0.26) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -2.37 0.26) (end -2.37 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 86.63 -5.3) (end 86.63 0.26) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 86.63 0.26) (end 81.11 0.26) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 81.11 0.26) (end 81.11 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -2.371 -0.74) (end -1.095 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1.095 -0.74) (end 1.671 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 3.41 -0.74) (end 4.211 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.95 -0.74) (end 6.751 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 8.49 -0.74) (end 9.291 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 11.03 -0.74) (end 11.831 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 13.57 -0.74) (end 14.371 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 16.11 -0.74) (end 16.911 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 18.65 -0.74) (end 19.451 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 21.19 -0.74) (end 21.991 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 23.73 -0.74) (end 24.531 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 26.27 -0.74) (end 27.071 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 28.81 -0.74) (end 29.611 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 31.35 -0.74) (end 32.151 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 33.89 -0.74) (end 34.691 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 36.43 -0.74) (end 37.231 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 38.97 -0.74) (end 39.771 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 41.51 -0.74) (end 42.311 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 44.05 -0.74) (end 44.851 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 46.59 -0.74) (end 47.391 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 49.13 -0.74) (end 49.931 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 51.67 -0.74) (end 52.471 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 54.21 -0.74) (end 55.011 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 56.75 -0.74) (end 57.551 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 59.29 -0.74) (end 60.091 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 61.83 -0.74) (end 62.631 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 64.37 -0.74) (end 65.171 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 66.91 -0.74) (end 67.711 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 69.45 -0.74) (end 70.251 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 71.99 -0.74) (end 72.791 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 74.53 -0.74) (end 75.331 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 77.07 -0.74) (end 77.871 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 79.61 -0.74) (end 81.11 -0.74) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.095 0) (end -1.695 -0.3) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.695 -0.3) (end -1.695 0.3) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.695 0.3) (end -1.095 0) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0 -1.2) (end -0.5 -1.9) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.5 -1.9) (end 0.5 -1.9) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0.5 -1.9) (end 0 -1.2) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -8.13 -13.23) (end -8.13 0.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -8.13 0.5) (end -1.27 0.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.27 0.5) (end -1.27 6.36) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.27 6.36) (end 80.02 6.36) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 80.02 6.36) (end 80.02 0.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 80.02 0.5) (end 86.87 0.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 86.87 0.5) (end 86.87 -13.23) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 86.87 -13.23) (end -8.13 -13.23) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -7.63 -5.3) (end 86.37 -5.3) (layer Dwgs.User) (width 0.08))
|
||||
(fp_line (start 39.17 -5.9) (end 39.37 -5.4) (layer Cmts.User) (width 0.1))
|
||||
(fp_line (start 39.37 -5.4) (end 39.57 -5.9) (layer Cmts.User) (width 0.1))
|
||||
(fp_line (start 39.37 -5.4) (end 39.37 -6.7) (layer Cmts.User) (width 0.1))
|
||||
(pad "" np_thru_hole circle (at -5.08 -2.54) (size 2.85 2.85) (drill 2.85) (layers *.Cu *.Mask))
|
||||
(pad "" np_thru_hole circle (at 83.82 -2.54) (size 2.85 2.85) (drill 2.85) (layers *.Cu *.Mask))
|
||||
(pad a1 thru_hole roundrect (at 0 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.16129))
|
||||
(pad a2 thru_hole circle (at 2.54 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a3 thru_hole circle (at 5.08 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a4 thru_hole circle (at 7.62 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a5 thru_hole circle (at 10.16 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a6 thru_hole circle (at 12.7 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a7 thru_hole circle (at 15.24 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a8 thru_hole circle (at 17.78 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a9 thru_hole circle (at 20.32 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a10 thru_hole circle (at 22.86 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a11 thru_hole circle (at 25.4 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a12 thru_hole circle (at 27.94 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a13 thru_hole circle (at 30.48 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a14 thru_hole circle (at 33.02 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a15 thru_hole circle (at 35.56 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a16 thru_hole circle (at 38.1 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a17 thru_hole circle (at 40.64 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a18 thru_hole circle (at 43.18 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a19 thru_hole circle (at 45.72 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a20 thru_hole circle (at 48.26 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a21 thru_hole circle (at 50.8 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a22 thru_hole circle (at 53.34 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a23 thru_hole circle (at 55.88 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a24 thru_hole circle (at 58.42 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a25 thru_hole circle (at 60.96 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a26 thru_hole circle (at 63.5 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a27 thru_hole circle (at 66.04 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a28 thru_hole circle (at 68.58 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a29 thru_hole circle (at 71.12 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a30 thru_hole circle (at 73.66 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a31 thru_hole circle (at 76.2 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad a32 thru_hole circle (at 78.74 0) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b1 thru_hole circle (at 0 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b2 thru_hole circle (at 2.54 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b3 thru_hole circle (at 5.08 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b4 thru_hole circle (at 7.62 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b5 thru_hole circle (at 10.16 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b6 thru_hole circle (at 12.7 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b7 thru_hole circle (at 15.24 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b8 thru_hole circle (at 17.78 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b9 thru_hole circle (at 20.32 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b10 thru_hole circle (at 22.86 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b11 thru_hole circle (at 25.4 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b12 thru_hole circle (at 27.94 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b13 thru_hole circle (at 30.48 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b14 thru_hole circle (at 33.02 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b15 thru_hole circle (at 35.56 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b16 thru_hole circle (at 38.1 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b17 thru_hole circle (at 40.64 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b18 thru_hole circle (at 43.18 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b19 thru_hole circle (at 45.72 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b20 thru_hole circle (at 48.26 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b21 thru_hole circle (at 50.8 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b22 thru_hole circle (at 53.34 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b23 thru_hole circle (at 55.88 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b24 thru_hole circle (at 58.42 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b25 thru_hole circle (at 60.96 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b26 thru_hole circle (at 63.5 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b27 thru_hole circle (at 66.04 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b28 thru_hole circle (at 68.58 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b29 thru_hole circle (at 71.12 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b30 thru_hole circle (at 73.66 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b31 thru_hole circle (at 76.2 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad b32 thru_hole circle (at 78.74 2.54) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c1 thru_hole circle (at 0 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c2 thru_hole circle (at 2.54 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c3 thru_hole circle (at 5.08 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c4 thru_hole circle (at 7.62 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c5 thru_hole circle (at 10.16 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c6 thru_hole circle (at 12.7 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c7 thru_hole circle (at 15.24 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c8 thru_hole circle (at 17.78 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c9 thru_hole circle (at 20.32 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c10 thru_hole circle (at 22.86 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c11 thru_hole circle (at 25.4 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c12 thru_hole circle (at 27.94 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c13 thru_hole circle (at 30.48 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c14 thru_hole circle (at 33.02 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c15 thru_hole circle (at 35.56 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c16 thru_hole circle (at 38.1 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c17 thru_hole circle (at 40.64 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c18 thru_hole circle (at 43.18 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c19 thru_hole circle (at 45.72 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c20 thru_hole circle (at 48.26 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c21 thru_hole circle (at 50.8 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c22 thru_hole circle (at 53.34 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c23 thru_hole circle (at 55.88 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c24 thru_hole circle (at 58.42 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c25 thru_hole circle (at 60.96 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c26 thru_hole circle (at 63.5 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c27 thru_hole circle (at 66.04 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c28 thru_hole circle (at 68.58 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c29 thru_hole circle (at 71.12 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c30 thru_hole circle (at 73.66 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c31 thru_hole circle (at 76.2 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad c32 thru_hole circle (at 78.74 5.08) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask))
|
||||
(fp_text user %R (at 39.37 -2.54) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text user "Board edge" (at 39.37 -7.3) (layer Cmts.User)
|
||||
(effects (font (size 0.7 0.7) (thickness 0.1)))
|
||||
)
|
||||
(model ${KISYS3DMOD}/Connector_DIN.3dshapes/DIN41612_C_3x32_Male_Horizontal_THT.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
|
@ -0,0 +1,66 @@
|
|||
(module HDMI_A_Amphenol_10029449-111 (layer F.Cu) (tedit 5E1BB628)
|
||||
(descr "HDMI, Type A, 10029449-111RLF, https://www.amphenol-icc.com/hdmi-10029449111rlf.html")
|
||||
(tags "HDMI type a connector")
|
||||
(attr smd)
|
||||
(fp_text reference REF** (at 0 -4.8) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value HDMI_A_Amphenol_10029449-111 (at 0 8.45) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -8.2 1.7) (end -8.2 -1.3) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -8.2 -3.4) (end -5 -3.4) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -8.2 4.2) (end -8.2 5.2) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 8.2 5.2) (end 8.2 4.2) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 8.2 -3.4) (end 8.2 -2.8) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 8.2 -3.4) (end 5.5 -3.4) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.5 -3.4) (end 5.5 -4.05) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 8.1 -3.3) (end 8.1 6.42) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 8.1 6.42) (end -8.1 6.42) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -8.1 6.42) (end -8.1 -3.3) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -8.1 -3.3) (end 8.1 -3.3) (layer F.Fab) (width 0.1))
|
||||
(fp_text user %R (at 0 1.45) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -9 -4.4) (end 9 -4.4) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 9 -4.4) (end 9 6.92) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 9 6.92) (end -9 6.92) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -9 6.92) (end -9 -4.4) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 4.75 -1.8) (end 4.5 -1.3) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 4.5 -1.3) (end 5 -1.3) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 -1.3) (end 4.75 -1.8) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -3 5.45) (end 3 5.45) (layer Dwgs.User) (width 0.1))
|
||||
(fp_text user "PCB Edge" (at 0 4.7) (layer Dwgs.User)
|
||||
(effects (font (size 0.5 0.5) (thickness 0.1)))
|
||||
)
|
||||
(fp_line (start -8.2 -3.4) (end -8.2 -2.8) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 8.2 1.7) (end 8.2 -1.3) (layer F.SilkS) (width 0.12))
|
||||
(pad 1 smd rect (at 4.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 2 smd rect (at 4.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 3 smd rect (at 3.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 4 smd rect (at 3.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 5 smd rect (at 2.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 6 smd rect (at 2.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 7 smd rect (at 1.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 8 smd rect (at 1.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 9 smd rect (at 0.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 10 smd rect (at 0.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 11 smd rect (at -0.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 12 smd rect (at -0.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 13 smd rect (at -1.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 14 smd rect (at -1.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 15 smd rect (at -2.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 16 smd rect (at -2.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 17 smd rect (at -3.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 18 smd rect (at -3.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 19 smd rect (at -4.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask))
|
||||
(pad SH thru_hole circle (at 7.25 -2.05) (size 2 2) (drill 1.3) (layers *.Cu *.Mask))
|
||||
(pad SH thru_hole circle (at -7.25 -2.05) (size 2 2) (drill 1.3) (layers *.Cu *.Mask))
|
||||
(pad SH thru_hole circle (at 7.85 2.9) (size 2 2) (drill 1.3) (layers *.Cu *.Mask))
|
||||
(pad SH thru_hole circle (at -7.85 2.9) (size 2 2) (drill 1.3) (layers *.Cu *.Mask))
|
||||
(model 10029449-111RLF.stp
|
||||
(offset (xyz 0 0.3 3.5))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 180 0 0))
|
||||
)
|
||||
)
|
|
@ -0,0 +1,30 @@
|
|||
(module L77HDE15SD1CH4RHNVGA (layer F.Cu) (tedit 613DA674)
|
||||
(fp_text reference REF** (at 25.2 -3.4) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value L77HDE15SD1CH4RHNVGA (at 13.3 -4.7) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -2.92 -4) (end -2.92 18.22) (layer F.CrtYd) (width 0.15))
|
||||
(fp_line (start -2.92 18.22) (end 27.92 18.22) (layer F.CrtYd) (width 0.15))
|
||||
(fp_line (start 27.92 -4) (end 27.92 18.22) (layer F.CrtYd) (width 0.15))
|
||||
(fp_line (start -2.92 -4) (end 27.92 -4) (layer F.CrtYd) (width 0.15))
|
||||
(fp_line (start 0 11.43) (end 25 11.43) (layer F.SilkS) (width 0.15))
|
||||
(pad 15 thru_hole circle (at 7.67 2.54) (size 1.5 1.5) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 14 thru_hole circle (at 9.96 2.54) (size 1.5 1.5) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 13 thru_hole circle (at 12.254 2.54) (size 1.5 1.5) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 12 thru_hole circle (at 14.54 2.54) (size 1.5 1.5) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 11 thru_hole circle (at 16.83 2.54) (size 1.5 1.5) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 10 thru_hole circle (at 8.81 0) (size 1.5 1.5) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 9 thru_hole circle (at 11.1 0) (size 1.5 1.5) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 8 thru_hole circle (at 13.39 0) (size 1.5 1.5) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 7 thru_hole circle (at 15.68 0) (size 1.5 1.5) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 6 thru_hole circle (at 17.97 0) (size 1.5 1.5) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 5 thru_hole circle (at 7.67 -2.54) (size 1.5 1.5) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 4 thru_hole circle (at 9.96 -2.54) (size 1.5 1.5) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 3 thru_hole circle (at 12.25 -2.54) (size 1.5 1.5) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 2 thru_hole circle (at 14.54 -2.54) (size 1.5 1.5) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 1 thru_hole circle (at 16.83 -2.54) (size 1.5 1.5) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 0 thru_hole circle (at 25 0) (size 3.5 3.5) (drill 3.05) (layers *.Cu *.Mask))
|
||||
(pad 0 thru_hole circle (at 0 0) (size 3.5 3.5) (drill 3.05) (layers *.Cu *.Mask))
|
||||
)
|
|
@ -0,0 +1,116 @@
|
|||
(module Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Horizontal (layer F.Cu) (tedit 59FED5CB)
|
||||
(descr "Through hole angled pin header, 1x06, 2.54mm pitch, 6mm pin length, single row")
|
||||
(tags "Through hole angled pin header THT 1x06 2.54mm single row")
|
||||
(fp_text reference J1 (at 4.385 -2.27) (layer F.SilkS)
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||||
(effects (font (size 1 1) (thickness 0.15)))
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||||
)
|
||||
(fp_text value Conn_01x06_Male (at 4.385 14.97) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text user %R (at 2.77 6.35 -270) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
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||||
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|
||||
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|
||||
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|
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|
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|
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||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(fp_line (start 4.04 -0.32) (end 10.04 -0.32) (layer F.Fab) (width 0.1))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(fp_line (start 2.135 -1.27) (end 4.04 -1.27) (layer F.Fab) (width 0.1))
|
||||
(pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask))
|
||||
(pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask))
|
||||
(pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask))
|
||||
(pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask))
|
||||
(pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask))
|
||||
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask))
|
||||
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x06_P2.54mm_Horizontal.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
|
@ -0,0 +1,149 @@
|
|||
(module Connector_PinHeader_2.00mm:PinHeader_2x07_P2.00mm_Horizontal (layer F.Cu) (tedit 59FED667)
|
||||
(descr "Through hole angled pin header, 2x07, 2.00mm pitch, 4.2mm pin length, double rows")
|
||||
(tags "Through hole angled pin header THT 2x07 2.00mm double row")
|
||||
(fp_text reference J3 (at 4.1 -2) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value Conn_02x07_Odd_Even (at 4.1 14) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text user %R (at 4.25 6 90) (layer F.Fab)
|
||||
(effects (font (size 0.9 0.9) (thickness 0.135)))
|
||||
)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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(fp_line (start 5.06 -0.25) (end 9.26 -0.25) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 0.31) (end 5.06 0.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 -0.31) (end 9.26 0.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 -0.31) (end 9.26 -0.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 -1.06) (end 3.44 -1.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 13.06) (end 5.06 -1.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 3.44 13.06) (end 5.06 13.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 3.44 -1.06) (end 3.44 13.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5 12.25) (end 9.2 12.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 9.2 11.75) (end 9.2 12.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 11.75) (end 9.2 11.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 12.25) (end 3.5 12.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 11.75) (end -0.25 12.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 11.75) (end 3.5 11.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 10.25) (end 9.2 10.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 9.2 9.75) (end 9.2 10.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 9.75) (end 9.2 9.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 10.25) (end 3.5 10.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 9.75) (end -0.25 10.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 9.75) (end 3.5 9.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 8.25) (end 9.2 8.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 9.2 7.75) (end 9.2 8.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 7.75) (end 9.2 7.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 8.25) (end 3.5 8.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 7.75) (end -0.25 8.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 7.75) (end 3.5 7.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 6.25) (end 9.2 6.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 9.2 5.75) (end 9.2 6.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 5.75) (end 9.2 5.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 6.25) (end 3.5 6.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 5.75) (end -0.25 6.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 5.75) (end 3.5 5.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 4.25) (end 9.2 4.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 9.2 3.75) (end 9.2 4.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 3.75) (end 9.2 3.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 4.25) (end 3.5 4.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 3.75) (end -0.25 4.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 3.75) (end 3.5 3.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 2.25) (end 9.2 2.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 9.2 1.75) (end 9.2 2.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 1.75) (end 9.2 1.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 2.25) (end 3.5 2.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 1.75) (end -0.25 2.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 1.75) (end 3.5 1.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 0.25) (end 9.2 0.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 9.2 -0.25) (end 9.2 0.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 -0.25) (end 9.2 -0.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 0.25) (end 3.5 0.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 -0.25) (end -0.25 0.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 -0.25) (end 3.5 -0.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 3.5 -0.625) (end 3.875 -1) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 3.5 13) (end 3.5 -0.625) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 13) (end 3.5 13) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 -1) (end 5 13) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 3.875 -1) (end 5 -1) (layer F.Fab) (width 0.1))
|
||||
(pad 14 thru_hole oval (at 2 12) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 13 thru_hole oval (at 0 12) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 12 thru_hole oval (at 2 10) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 11 thru_hole oval (at 0 10) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 10 thru_hole oval (at 2 8) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 9 thru_hole oval (at 0 8) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 8 thru_hole oval (at 2 6) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 7 thru_hole oval (at 0 6) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 6 thru_hole oval (at 2 4) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 5 thru_hole oval (at 0 4) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 4 thru_hole oval (at 2 2) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 3 thru_hole oval (at 0 2) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 2 thru_hole oval (at 2 0) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 1 thru_hole rect (at 0 0) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(model ${KISYS3DMOD}/Connector_PinHeader_2.00mm.3dshapes/PinHeader_2x07_P2.00mm_Horizontal.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
|
@ -0,0 +1,49 @@
|
|||
(module PinHeader_2x07_P2.00mm_Vertical_For_SeeedStudio (layer F.Cu) (tedit 61B75E34)
|
||||
(descr "Through hole straight pin header, 2x07, 2.00mm pitch, double rows")
|
||||
(tags "Through hole pin header THT 2x07 2.00mm double row")
|
||||
(fp_text reference J1 (at 1 -2.06) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value Conn_02x07_Odd_Even (at 1 14.06) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start 0 -1) (end 3 -1) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 3 -1) (end 3 13) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 3 13) (end -1 13) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -1 13) (end -1 0) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -1 0) (end 0 -1) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -1.06 13.06) (end 3.06 13.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.06 1) (end -1.06 13.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 3.06 -1.06) (end 3.06 13.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.06 1) (end 1 1) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1 1) (end 1 -1.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1 -1.06) (end 3.06 -1.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.06 0) (end -1.06 -1.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.06 -1.06) (end 0 -1.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.5 -1.5) (end -1.5 13.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.5 13.5) (end 3.5 13.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 3.5 13.5) (end 3.5 -1.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 3.5 -1.5) (end -1.5 -1.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_text user %R (at 1 6 90) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(pad 1 thru_hole rect (at 0 0) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 2 thru_hole oval (at 2 0) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 3 thru_hole oval (at 0 2) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 4 thru_hole oval (at 2 2) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 5 thru_hole oval (at 0 4) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 6 thru_hole oval (at 2 4) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 7 thru_hole oval (at 0 6) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 8 thru_hole oval (at 2 6) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 9 thru_hole oval (at 0 8) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 10 thru_hole oval (at 2 8) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 11 thru_hole oval (at 0 10) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 12 thru_hole oval (at 2 10) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 13 thru_hole oval (at 0 12) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 14 thru_hole oval (at 2 12) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(model ${KISYS3DMOD}/Connector_PinHeader_2.00mm.3dshapes/PinHeader_2x07_P2.00mm_Vertical.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
|
@ -0,0 +1,99 @@
|
|||
(module Connector_PinHeader_2.54mm:PinHeader_2x32_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC)
|
||||
(descr "Through hole straight pin header, 2x32, 2.54mm pitch, double rows")
|
||||
(tags "Through hole pin header THT 2x32 2.54mm double row")
|
||||
(fp_text reference JCD1 (at 1.27 -2.33) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value ZTEX_CD-ztex_CD (at 1.27 81.07) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text user %R (at 1.27 39.37 90) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start 4.35 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 4.35 80.55) (end 4.35 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.8 80.55) (end 4.35 80.55) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.8 -1.8) (end -1.8 80.55) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1.27 -1.33) (end 3.87 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1.27 1.27) (end 1.27 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 3.87 -1.33) (end 3.87 80.07) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 1.27) (end -1.33 80.07) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 80.07) (end 3.87 80.07) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.27 0) (end 0 -1.27) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -1.27 80.01) (end -1.27 0) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 3.81 80.01) (end -1.27 80.01) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 3.81 -1.27) (end 3.81 80.01) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 -1.27) (end 3.81 -1.27) (layer F.Fab) (width 0.1))
|
||||
(pad 64 thru_hole oval (at 2.54 78.74) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 63 thru_hole oval (at 0 78.74) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 62 thru_hole oval (at 2.54 76.2) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 61 thru_hole oval (at 0 76.2) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 60 thru_hole oval (at 2.54 73.66) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 59 thru_hole oval (at 0 73.66) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 58 thru_hole oval (at 2.54 71.12) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 57 thru_hole oval (at 0 71.12) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 56 thru_hole oval (at 2.54 68.58) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 55 thru_hole oval (at 0 68.58) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 54 thru_hole oval (at 2.54 66.04) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 53 thru_hole oval (at 0 66.04) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 52 thru_hole oval (at 2.54 63.5) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 51 thru_hole oval (at 0 63.5) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 50 thru_hole oval (at 2.54 60.96) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 49 thru_hole oval (at 0 60.96) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 48 thru_hole oval (at 2.54 58.42) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 47 thru_hole oval (at 0 58.42) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 46 thru_hole oval (at 2.54 55.88) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 45 thru_hole oval (at 0 55.88) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 44 thru_hole oval (at 2.54 53.34) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 43 thru_hole oval (at 0 53.34) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 42 thru_hole oval (at 2.54 50.8) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 41 thru_hole oval (at 0 50.8) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 40 thru_hole oval (at 2.54 48.26) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 39 thru_hole oval (at 0 48.26) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 38 thru_hole oval (at 2.54 45.72) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 37 thru_hole oval (at 0 45.72) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 36 thru_hole oval (at 2.54 43.18) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 35 thru_hole oval (at 0 43.18) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 34 thru_hole oval (at 2.54 40.64) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 33 thru_hole oval (at 0 40.64) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 32 thru_hole oval (at 2.54 38.1) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 31 thru_hole oval (at 0 38.1) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 30 thru_hole oval (at 2.54 35.56) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 29 thru_hole oval (at 0 35.56) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 28 thru_hole oval (at 2.54 33.02) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 27 thru_hole oval (at 0 33.02) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 26 thru_hole oval (at 2.54 30.48) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 25 thru_hole oval (at 0 30.48) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 24 thru_hole oval (at 2.54 27.94) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 23 thru_hole oval (at 0 27.94) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 22 thru_hole oval (at 2.54 25.4) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 21 thru_hole oval (at 0 25.4) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 20 thru_hole oval (at 2.54 22.86) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 19 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 18 thru_hole oval (at 2.54 20.32) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 17 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 16 thru_hole oval (at 2.54 17.78) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 15 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 14 thru_hole oval (at 2.54 15.24) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 13 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 12 thru_hole oval (at 2.54 12.7) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 11 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 10 thru_hole oval (at 2.54 10.16) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 9 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 8 thru_hole oval (at 2.54 7.62) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 7 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 6 thru_hole oval (at 2.54 5.08) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 5 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 4 thru_hole oval (at 2.54 2.54) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 3 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 2 thru_hole oval (at 2.54 0) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_2x32_P2.54mm_Vertical.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
|
@ -0,0 +1,35 @@
|
|||
(module PinSocket_1x02_P2.54mm_Vertical_for_SeeedStudio (layer F.Cu) (tedit 61BCBDC6)
|
||||
(descr "Through hole straight socket strip, 1x02, 2.54mm pitch, single row (from Kicad 4.0.7), script generated")
|
||||
(tags "Through hole socket strip THT 1x02 2.54mm single row")
|
||||
(fp_text reference J9 (at 0 -2.77) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value Conn_01x02 (at 0 5.31) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -1.27 -1.27) (end 0.635 -1.27) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0.635 -1.27) (end 1.27 -0.635) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 1.27 -0.635) (end 1.27 3.81) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -1.27 3.81) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1.33 -1.33) (end 1.33 0) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0 -1.33) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.8 -1.8) (end 1.75 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.75 -1.8) (end 1.75 4.3) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.75 4.3) (end -1.8 4.3) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.8 4.3) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(fp_text user %R (at 0 1.27 90) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask))
|
||||
(pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask))
|
||||
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_1x02_P2.54mm_Vertical.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
|
@ -0,0 +1,113 @@
|
|||
(module Connector_PinSocket_2.54mm:PinSocket_2x06_P2.54mm_Horizontal (layer F.Cu) (tedit 5A19A42C)
|
||||
(descr "Through hole angled socket strip, 2x06, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated")
|
||||
(tags "Through hole angled socket strip THT 2x06 2.54mm double row")
|
||||
(fp_text reference J5 (at -5.65 -2.77) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value Conn_02x06_Odd_Even (at -5.65 15.47) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text user %R (at -8.315 6.35 90) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start 1.8 14.45) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -13.05 14.45) (end 1.8 14.45) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -13.05 -1.8) (end -13.05 14.45) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.8 -1.8) (end -13.05 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 0 -1.33) (end 1.11 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1.11 -1.33) (end 1.11 0) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 -1.33) (end -12.63 14.03) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 14.03) (end -4 14.03) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -4 -1.33) (end -4 14.03) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 -1.33) (end -4 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 11.43) (end -4 11.43) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 8.89) (end -4 8.89) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 6.35) (end -4 6.35) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 3.81) (end -4 3.81) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 1.27) (end -4 1.27) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.49 13.06) (end -1.05 13.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -4 13.06) (end -3.59 13.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.49 12.34) (end -1.05 12.34) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -4 12.34) (end -3.59 12.34) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.49 10.52) (end -1.05 10.52) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -4 10.52) (end -3.59 10.52) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.49 9.8) (end -1.05 9.8) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -4 9.8) (end -3.59 9.8) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.49 7.98) (end -1.05 7.98) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -4 7.98) (end -3.59 7.98) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.49 7.26) (end -1.05 7.26) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -4 7.26) (end -3.59 7.26) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.49 5.44) (end -1.05 5.44) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -4 5.44) (end -3.59 5.44) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.49 4.72) (end -1.05 4.72) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -4 4.72) (end -3.59 4.72) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.49 2.9) (end -1.05 2.9) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -4 2.9) (end -3.59 2.9) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.49 2.18) (end -1.05 2.18) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -4 2.18) (end -3.59 2.18) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.49 0.36) (end -1.11 0.36) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -4 0.36) (end -3.59 0.36) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.49 -0.36) (end -1.11 -0.36) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -4 -0.36) (end -3.59 -0.36) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 1.1519) (end -4 1.1519) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 1.033805) (end -4 1.033805) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 0.91571) (end -4 0.91571) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 0.797615) (end -4 0.797615) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 0.67952) (end -4 0.67952) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 0.561425) (end -4 0.561425) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 0.44333) (end -4 0.44333) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 0.325235) (end -4 0.325235) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 0.20714) (end -4 0.20714) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 0.089045) (end -4 0.089045) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 -0.02905) (end -4 -0.02905) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 -0.147145) (end -4 -0.147145) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 -0.26524) (end -4 -0.26524) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 -0.383335) (end -4 -0.383335) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 -0.50143) (end -4 -0.50143) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 -0.619525) (end -4 -0.619525) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 -0.73762) (end -4 -0.73762) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 -0.855715) (end -4 -0.855715) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 -0.97381) (end -4 -0.97381) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 -1.091905) (end -4 -1.091905) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -12.63 -1.21) (end -4 -1.21) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0 13) (end 0 12.4) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -4.06 13) (end 0 13) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 12.4) (end -4.06 12.4) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 10.46) (end 0 9.86) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -4.06 10.46) (end 0 10.46) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 9.86) (end -4.06 9.86) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 7.92) (end 0 7.32) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -4.06 7.92) (end 0 7.92) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 7.32) (end -4.06 7.32) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 5.38) (end 0 4.78) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -4.06 5.38) (end 0 5.38) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 4.78) (end -4.06 4.78) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 2.84) (end 0 2.24) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -4.06 2.84) (end 0 2.84) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 2.24) (end -4.06 2.24) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 0.3) (end 0 -0.3) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -4.06 0.3) (end 0 0.3) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 -0.3) (end -4.06 -0.3) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -12.57 13.97) (end -12.57 -1.27) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -4.06 13.97) (end -12.57 13.97) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -4.06 -0.3) (end -4.06 13.97) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -5.03 -1.27) (end -4.06 -0.3) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -12.57 -1.27) (end -5.03 -1.27) (layer F.Fab) (width 0.1))
|
||||
(pad 12 thru_hole oval (at -2.54 12.7) (size 1.7 1.7) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 11 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 10 thru_hole oval (at -2.54 10.16) (size 1.7 1.7) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 9 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 8 thru_hole oval (at -2.54 7.62) (size 1.7 1.7) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 7 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 6 thru_hole oval (at -2.54 5.08) (size 1.7 1.7) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 5 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 4 thru_hole oval (at -2.54 2.54) (size 1.7 1.7) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 3 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 2 thru_hole oval (at -2.54 0) (size 1.7 1.7) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1.19) (layers *.Cu *.Mask))
|
||||
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_2x06_P2.54mm_Horizontal.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
|
@ -0,0 +1,49 @@
|
|||
(module PinSocket_2x07_P2.00mm_Vertical_For_SeeedStudio (layer F.Cu) (tedit 61B75CF9)
|
||||
(descr "Through hole straight socket strip, 2x07, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated")
|
||||
(tags "Through hole socket strip THT 2x07 2.00mm double row")
|
||||
(fp_text reference J1 (at -1 -2.5) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value Conn_02x07_Odd_Even (at -1 14.5) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -3 -1) (end 0 -1) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 -1) (end 1 0) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 1 0) (end 1 13) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 1 13) (end -3 13) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -3 13) (end -3 -1) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -3.06 -1.06) (end -1 -1.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -3.06 -1.06) (end -3.06 13.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -3.06 13.06) (end 1.06 13.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1.06 1) (end 1.06 13.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1 1) (end 1.06 1) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1 -1.06) (end -1 1) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1.06 -1.06) (end 1.06 0) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0 -1.06) (end 1.06 -1.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -3.5 -1.5) (end 1.5 -1.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.5 -1.5) (end 1.5 13.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.5 13.5) (end -3.5 13.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -3.5 13.5) (end -3.5 -1.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_text user %R (at -1 6 90) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(pad 1 thru_hole rect (at 0 0) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 2 thru_hole oval (at -2 0) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 3 thru_hole oval (at 0 2) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 4 thru_hole oval (at -2 2) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 5 thru_hole oval (at 0 4) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 6 thru_hole oval (at -2 4) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 7 thru_hole oval (at 0 6) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 8 thru_hole oval (at -2 6) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 9 thru_hole oval (at 0 8) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 10 thru_hole oval (at -2 8) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 11 thru_hole oval (at 0 10) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 12 thru_hole oval (at -2 10) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 13 thru_hole oval (at 0 12) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 14 thru_hole oval (at -2 12) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(model ${KISYS3DMOD}/Connector_PinSocket_2.00mm.3dshapes/PinSocket_2x07_P2.00mm_Vertical.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
|
@ -0,0 +1,55 @@
|
|||
(module QSOP-20_3.9x8.7mm_P0.635mm_Renesas (layer F.Cu) (tedit 5A02F25C)
|
||||
(descr "20-Lead Plastic Shrink Small Outline Narrow Body (http://www.analog.com/media/en/technical-documentation/data-sheets/ADuM7640_7641_7642_7643.pdf)")
|
||||
(tags "QSOP 0.635")
|
||||
(attr smd)
|
||||
(fp_text reference U9 (at -3 -5.1) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value 74FCT245ATQG (at 0 5.3) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -2.075 3.3) (end -2.075 4.475) (layer F.SilkS) (width 0.12))
|
||||
(fp_text user %R (at 0 0) (layer F.Fab)
|
||||
(effects (font (size 0.8 0.8) (thickness 0.08)))
|
||||
)
|
||||
(fp_line (start -0.95 -4.35) (end 1.95 -4.35) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 1.95 -4.35) (end 1.95 4.35) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 1.95 4.35) (end -1.95 4.35) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -1.95 4.35) (end -1.95 -3.35) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -1.95 -3.35) (end -0.95 -4.35) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -3.71 -4.6) (end -3.71 4.6) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 3.7 -4.6) (end 3.7 4.6) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -3.71 -4.6) (end 3.7 -4.6) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -3.71 4.6) (end 3.7 4.6) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -2.075 4.475) (end 2.075 4.475) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -2.075 -4.475) (end 2.075 -4.475) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -3.5 -3.3) (end -2.075 -3.3) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.075 3.3) (end 2.075 4.475) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -2.075 -3.3) (end -2.075 -4.475) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.075 -3.3) (end 2.075 -4.475) (layer F.SilkS) (width 0.12))
|
||||
(pad 14 smd rect (at 2.6943 0.9525) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 15 smd rect (at 2.6943 0.3175) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 7 smd rect (at -2.6943 0.9525) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 6 smd rect (at -2.6943 0.3175) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 17 smd rect (at 2.6943 -0.9525) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 16 smd rect (at 2.6943 -0.3175) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 5 smd rect (at -2.6943 -0.3175) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 4 smd rect (at -2.6943 -0.9525) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 1 smd rect (at -2.6943 -2.8575) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 2 smd rect (at -2.6943 -2.2225) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 3 smd rect (at -2.6943 -1.5875) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 8 smd rect (at -2.6943 1.5875) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 9 smd rect (at -2.6943 2.2225) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 10 smd rect (at -2.6943 2.8575) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 11 smd rect (at 2.6943 2.8575) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 12 smd rect (at 2.6943 2.2225) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 13 smd rect (at 2.6943 1.5875) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 18 smd rect (at 2.6943 -1.5875) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 19 smd rect (at 2.6943 -2.2225) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 20 smd rect (at 2.6943 -2.8575) (size 1.68 0.41) (layers F.Cu F.Paste F.Mask))
|
||||
(model ${KISYS3DMOD}/Package_SO.3dshapes/QSOP-20_3.9x8.7mm_P0.635mm.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
|
@ -0,0 +1,46 @@
|
|||
|
||||
(module SOP65P640X120-24N (layer F.Cu) (tedit 60DD7FAB)
|
||||
(descr "")
|
||||
(fp_text reference REF** (at -0.645 -4.912 0) (layer F.SilkS)
|
||||
(effects (font (size 1.0 1.0) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value SOP65P640X120-24N (at 6.975 4.912 0) (layer F.Fab)
|
||||
(effects (font (size 1.0 1.0) (thickness 0.15)))
|
||||
)
|
||||
(fp_circle (center -4.44 -3.985) (end -4.34 -3.985) (layer F.SilkS) (width 0.2))
|
||||
(fp_circle (center -4.44 -3.985) (end -4.34 -3.985) (layer F.Fab) (width 0.2))
|
||||
(fp_line (start -2.2 -3.9) (end 2.2 -3.9) (layer F.Fab) (width 0.127))
|
||||
(fp_line (start -2.2 3.9) (end 2.2 3.9) (layer F.Fab) (width 0.127))
|
||||
(fp_line (start -2.2 -4.1) (end 2.2 -4.1) (layer F.SilkS) (width 0.127))
|
||||
(fp_line (start -2.2 4.1) (end 2.2 4.1) (layer F.SilkS) (width 0.127))
|
||||
(fp_line (start -2.2 -3.9) (end -2.2 3.9) (layer F.Fab) (width 0.127))
|
||||
(fp_line (start 2.2 -3.9) (end 2.2 3.9) (layer F.Fab) (width 0.127))
|
||||
(fp_line (start -3.905 -4.15) (end 3.905 -4.15) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -3.905 4.15) (end 3.905 4.15) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -3.905 -4.15) (end -3.905 4.15) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 3.905 -4.15) (end 3.905 4.15) (layer F.CrtYd) (width 0.05))
|
||||
(pad 1 smd rect (at -2.87 -3.575) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 2 smd rect (at -2.87 -2.925) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 3 smd rect (at -2.87 -2.275) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 4 smd rect (at -2.87 -1.625) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 5 smd rect (at -2.87 -0.975) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 6 smd rect (at -2.87 -0.325) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 7 smd rect (at -2.87 0.325) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 8 smd rect (at -2.87 0.975) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 9 smd rect (at -2.87 1.625) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 10 smd rect (at -2.87 2.275) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 11 smd rect (at -2.87 2.925) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 12 smd rect (at -2.87 3.575) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 13 smd rect (at 2.87 3.575) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 14 smd rect (at 2.87 2.925) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 15 smd rect (at 2.87 2.275) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 16 smd rect (at 2.87 1.625) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 17 smd rect (at 2.87 0.975) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 18 smd rect (at 2.87 0.325) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 19 smd rect (at 2.87 -0.325) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 20 smd rect (at 2.87 -0.975) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 21 smd rect (at 2.87 -1.625) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 22 smd rect (at 2.87 -2.275) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 23 smd rect (at 2.87 -2.925) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 24 smd rect (at 2.87 -3.575) (size 1.57 0.41) (layers F.Cu F.Mask F.Paste))
|
||||
)
|
|
@ -0,0 +1,81 @@
|
|||
(module TQFP-44_10x10mm_P0.8mm_Xilinx (layer F.Cu) (tedit 5A02F146)
|
||||
(descr "44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] (see Microchip Packaging Specification 00000049BS.pdf)")
|
||||
(tags "QFP 0.8")
|
||||
(attr smd)
|
||||
(fp_text reference U8 (at -5.8 -7.3) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value XC9536XL-VQ44 (at 0 7.45) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text user %R (at 0 0) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -4 -5) (end 5 -5) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start 5 -5) (end 5 5) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start 5 5) (end -5 5) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start -5 5) (end -5 -4) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start -5 -4) (end -4 -5) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start -6.7 -6.7) (end -6.7 6.7) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 6.7 -6.7) (end 6.7 6.7) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -6.7 -6.7) (end 6.7 -6.7) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -6.7 6.7) (end 6.7 6.7) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -5.175 -5.175) (end -5.175 -4.6) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 5.175 -5.175) (end 5.175 -4.5) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 5.175 5.175) (end 5.175 4.5) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -5.175 5.175) (end -5.175 4.5) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -5.175 -5.175) (end -4.5 -5.175) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -5.175 5.175) (end -4.5 5.175) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 5.175 5.175) (end 4.5 5.175) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 5.175 -5.175) (end 4.5 -5.175) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -5.175 -4.6) (end -6.45 -4.6) (layer F.SilkS) (width 0.15))
|
||||
(pad 1 smd rect (at -5.7 -4) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 2 smd rect (at -5.7 -3.2) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 3 smd rect (at -5.7 -2.4) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 4 smd rect (at -5.7 -1.6) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 5 smd rect (at -5.7 -0.8) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 6 smd rect (at -5.7 0) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 7 smd rect (at -5.7 0.8) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 8 smd rect (at -5.7 1.6) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 9 smd rect (at -5.7 2.4) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 10 smd rect (at -5.7 3.2) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 11 smd rect (at -5.7 4) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 12 smd rect (at -4 5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 13 smd rect (at -3.2 5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 14 smd rect (at -2.4 5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 15 smd rect (at -1.6 5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 16 smd rect (at -0.8 5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 17 smd rect (at 0 5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 18 smd rect (at 0.8 5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 19 smd rect (at 1.6 5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 20 smd rect (at 2.4 5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 21 smd rect (at 3.2 5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 22 smd rect (at 4 5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 23 smd rect (at 5.7 4) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 24 smd rect (at 5.7 3.2) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 25 smd rect (at 5.7 2.4) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 26 smd rect (at 5.7 1.6) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 27 smd rect (at 5.7 0.8) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 28 smd rect (at 5.7 0) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 29 smd rect (at 5.7 -0.8) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 30 smd rect (at 5.7 -1.6) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 31 smd rect (at 5.7 -2.4) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 32 smd rect (at 5.7 -3.2) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 33 smd rect (at 5.7 -4) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 34 smd rect (at 4 -5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 35 smd rect (at 3.2 -5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 36 smd rect (at 2.4 -5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 37 smd rect (at 1.6 -5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 38 smd rect (at 0.8 -5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 39 smd rect (at 0 -5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 40 smd rect (at -0.8 -5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 41 smd rect (at -1.6 -5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 42 smd rect (at -2.4 -5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 43 smd rect (at -3.2 -5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 44 smd rect (at -4 -5.7 90) (size 1.6 0.55) (layers F.Cu F.Paste F.Mask))
|
||||
(model ${KISYS3DMOD}/Package_QFP.3dshapes/TQFP-44_10x10mm_P0.8mm.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
|
@ -0,0 +1,50 @@
|
|||
(module TSSOP-20_4.4x6.5mm_P0.65mm_ForSeeedStudio (layer F.Cu) (tedit 613DC505)
|
||||
(descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)")
|
||||
(tags "SSOP 0.65")
|
||||
(attr smd)
|
||||
(fp_text reference REF** (at 0 -4.3) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value TSSOP-20_4.4x6.5mm_P0.65mm_ForSeeedStudio (at 0 4.3) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -1.2 -3.25) (end 2.2 -3.25) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start 2.2 -3.25) (end 2.2 3.25) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start 2.2 3.25) (end -2.2 3.25) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start -2.2 3.25) (end -2.2 -2.25) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start -2.2 -2.25) (end -1.2 -3.25) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start -3.95 -3.55) (end -3.95 3.55) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 3.95 -3.55) (end 3.95 3.55) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -3.95 -3.55) (end 3.95 -3.55) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -3.95 3.55) (end 3.95 3.55) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -2.225 3.45) (end 2.225 3.45) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -3.75 -3.45) (end 2.225 -3.45) (layer F.SilkS) (width 0.15))
|
||||
(fp_text user %R (at 0 0) (layer F.Fab)
|
||||
(effects (font (size 0.8 0.8) (thickness 0.15)))
|
||||
)
|
||||
(pad 1 smd rect (at -2.8 -2.925) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 2 smd rect (at -2.8 -2.275) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 3 smd rect (at -2.8 -1.625) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 4 smd rect (at -2.8 -0.975) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 5 smd rect (at -2.8 -0.325) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 6 smd rect (at -2.8 0.325) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 7 smd rect (at -2.8 0.975) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 8 smd rect (at -2.8 1.625) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 9 smd rect (at -2.8 2.275) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 10 smd rect (at -2.8 2.925) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 11 smd rect (at 2.8 2.925) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 12 smd rect (at 2.8 2.275) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 13 smd rect (at 2.8 1.625) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 14 smd rect (at 2.8 0.975) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 15 smd rect (at 2.8 0.325) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 16 smd rect (at 2.8 -0.325) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 17 smd rect (at 2.8 -0.975) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 18 smd rect (at 2.8 -1.625) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 19 smd rect (at 2.8 -2.275) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 20 smd rect (at 2.8 -2.925) (size 1.55 0.45) (layers F.Cu F.Paste F.Mask))
|
||||
(model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
|
@ -0,0 +1,89 @@
|
|||
(module Package_SO:TSSOP-56_6.1x14mm_P0.5mm (layer F.Cu) (tedit 5A02F25C)
|
||||
(descr "TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot364-1_po.pdf)")
|
||||
(tags "SSOP 0.5")
|
||||
(attr smd)
|
||||
(fp_text reference U2 (at 0 -8.05) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value SN74CB3T16211DGGR (at 0 8.05) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -2.05 -7) (end 3.05 -7) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start 3.05 -7) (end 3.05 7) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start 3.05 7) (end -3.05 7) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start -3.05 7) (end -3.05 -6) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start -3.05 -6) (end -2.05 -7) (layer F.Fab) (width 0.15))
|
||||
(fp_line (start -4.5 -7.3) (end -4.5 7.3) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 4.5 -7.3) (end 4.5 7.3) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -4.5 -7.3) (end 4.5 -7.3) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -4.5 7.3) (end 4.5 7.3) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 3.175 -7.125) (end 3.175 -7.1175) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 3.175 7.125) (end 3.175 7.1175) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -3.175 7.125) (end -3.175 7.1175) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -4.25 -7.2) (end 3.175 -7.2) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -3.175 7.125) (end 3.175 7.125) (layer F.SilkS) (width 0.15))
|
||||
(fp_text user %R (at 0 0) (layer F.Fab)
|
||||
(effects (font (size 0.8 0.8) (thickness 0.15)))
|
||||
)
|
||||
(pad 1 smd rect (at -3.75 -6.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 2 smd rect (at -3.75 -6.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 3 smd rect (at -3.75 -5.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 4 smd rect (at -3.75 -5.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 5 smd rect (at -3.75 -4.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 6 smd rect (at -3.75 -4.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 7 smd rect (at -3.75 -3.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 8 smd rect (at -3.75 -3.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 9 smd rect (at -3.75 -2.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 10 smd rect (at -3.75 -2.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 11 smd rect (at -3.75 -1.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 12 smd rect (at -3.75 -1.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 13 smd rect (at -3.75 -0.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 14 smd rect (at -3.75 -0.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 15 smd rect (at -3.75 0.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 16 smd rect (at -3.75 0.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 17 smd rect (at -3.75 1.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 18 smd rect (at -3.75 1.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 19 smd rect (at -3.75 2.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 20 smd rect (at -3.75 2.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 21 smd rect (at -3.75 3.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 22 smd rect (at -3.75 3.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 23 smd rect (at -3.75 4.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 24 smd rect (at -3.75 4.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 25 smd rect (at -3.75 5.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 26 smd rect (at -3.75 5.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 27 smd rect (at -3.75 6.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 28 smd rect (at -3.75 6.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 29 smd rect (at 3.75 6.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 30 smd rect (at 3.75 6.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 31 smd rect (at 3.75 5.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 32 smd rect (at 3.75 5.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 33 smd rect (at 3.75 4.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 34 smd rect (at 3.75 4.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 35 smd rect (at 3.75 3.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 36 smd rect (at 3.75 3.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 37 smd rect (at 3.75 2.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 38 smd rect (at 3.75 2.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 39 smd rect (at 3.75 1.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 40 smd rect (at 3.75 1.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 41 smd rect (at 3.75 0.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 42 smd rect (at 3.75 0.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 43 smd rect (at 3.75 -0.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 44 smd rect (at 3.75 -0.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 45 smd rect (at 3.75 -1.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 46 smd rect (at 3.75 -1.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 47 smd rect (at 3.75 -2.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 48 smd rect (at 3.75 -2.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 49 smd rect (at 3.75 -3.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 50 smd rect (at 3.75 -3.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 51 smd rect (at 3.75 -4.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 52 smd rect (at 3.75 -4.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 53 smd rect (at 3.75 -5.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 54 smd rect (at 3.75 -5.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 55 smd rect (at 3.75 -6.25) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 56 smd rect (at 3.75 -6.75) (size 1.5 0.285) (layers F.Cu F.Paste F.Mask))
|
||||
(model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-56_6.1x14mm_P0.5mm.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
|
@ -0,0 +1,58 @@
|
|||
(module USB_A_Molex_67643_Horizontal (layer F.Cu) (tedit 5EA03975)
|
||||
(descr "USB type A, Horizontal, https://www.molex.com/pdm_docs/sd/676433910_sd.pdf")
|
||||
(tags "USB_A Female Connector receptacle")
|
||||
(fp_text reference REF** (at 3.5 -3.19) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value USB_A_Molex_67643_Horizontal (at 3.5 14.5) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text user %R (at 3.5 3.7) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -3.05 -2.27) (end 10.05 -2.27) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 10.05 -2.27) (end 10.05 12.69) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -3.16 12.58) (end -3.16 4.47) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -3.16 12.58) (end -3.81 12.58) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -3.7 12.69) (end -3.7 12.99) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -3.7 12.99) (end 10.7 12.99) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 10.7 12.99) (end 10.7 12.69) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 10.7 12.69) (end 10.05 12.69) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -3.05 9.27) (end 10.05 9.27) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -3.55 -2.77) (end 10.55 -2.77) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 10.55 -2.77) (end 10.55 0.76) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -3.55 -2.77) (end -3.55 0.76) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -4.2 13.49) (end 11.2 13.49) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 11.2 13.49) (end 11.2 12.19) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 11.2 12.19) (end 10.55 12.19) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 10.55 12.19) (end 10.55 4.66) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -4.2 13.49) (end -4.2 12.19) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -4.2 12.19) (end -3.55 12.19) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -3.55 12.19) (end -3.55 4.66) (layer F.CrtYd) (width 0.05))
|
||||
(fp_arc (start -3.07 2.71) (end -3.55 0.76) (angle -152.3426981) (layer F.CrtYd) (width 0.05))
|
||||
(fp_arc (start 10.07 2.71) (end 10.55 4.66) (angle -152.3426981) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -3.16 -2.38) (end 10.16 -2.38) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -3.16 -2.38) (end -3.16 0.95) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 10.16 -2.38) (end 10.16 0.95) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -3.05 12.69) (end -3.05 -2.27) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 10.81 13.1) (end 10.81 12.58) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -3.81 13.1) (end 10.81 13.1) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 10.16 4.47) (end 10.16 12.58) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -3.81 12.58) (end -3.81 13.1) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 10.81 12.58) (end 10.16 12.58) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -3.05 12.69) (end -3.7 12.69) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.9 -2.6) (end 0.9 -2.6) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1 -2.27) (end 0 -1.27) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 0 -1.27) (end 1 -2.27) (layer F.Fab) (width 0.1))
|
||||
(pad 5 thru_hole circle (at -3.07 2.71) (size 3 3) (drill 2.3) (layers *.Cu *.Mask))
|
||||
(pad 5 thru_hole circle (at 10.07 2.71) (size 3 3) (drill 2.3) (layers *.Cu *.Mask))
|
||||
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.5) (drill 0.95) (layers *.Cu *.Mask))
|
||||
(pad 2 thru_hole circle (at 2.5 0) (size 1.6 1.6) (drill 0.95) (layers *.Cu *.Mask))
|
||||
(pad 3 thru_hole circle (at 4.5 0) (size 1.6 1.6) (drill 0.95) (layers *.Cu *.Mask))
|
||||
(pad 4 thru_hole circle (at 7 0) (size 1.6 1.6) (drill 0.95) (layers *.Cu *.Mask))
|
||||
(model ${KISYS3DMOD}/Connector_USB.3dshapes/USB_A_Molex_67643_Horizontal.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
39785
nubus-to-ztex/L77HDE15SD1CH4F--3DModel-STEP-533217.STEP
Normal file
39785
nubus-to-ztex/L77HDE15SD1CH4F--3DModel-STEP-533217.STEP
Normal file
File diff suppressed because it is too large
Load Diff
99
nubus-to-ztex/Molex2x32.pretty/Molex2x32.kicad_mod
Normal file
99
nubus-to-ztex/Molex2x32.pretty/Molex2x32.kicad_mod
Normal file
|
@ -0,0 +1,99 @@
|
|||
(module Molex2x32 (layer F.Cu) (tedit 59FED5CC)
|
||||
(descr "Through hole straight pin header, 2x32, 2.54mm pitch, double rows")
|
||||
(tags "Through hole pin header THT 2x32 2.54mm double row")
|
||||
(fp_text reference REF** (at 1.27 -2.33) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value PinHeader_2x32_P2.54mm_Vertical (at 1.27 81.07) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start 0 -1.27) (end 3.81 -1.27) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 3.81 -1.27) (end 3.81 80.01) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 3.81 80.01) (end -1.27 80.01) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -1.27 80.01) (end -1.27 0) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -1.27 0) (end 0 -1.27) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -1.33 80.07) (end 3.87 80.07) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 1.27) (end -1.33 80.07) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 3.87 -1.33) (end 3.87 80.07) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1.27 1.27) (end 1.27 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1.27 -1.33) (end 3.87 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.8 -1.8) (end -1.8 80.55) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.8 80.55) (end 4.35 80.55) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 4.35 80.55) (end 4.35 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 4.35 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 2 thru_hole oval (at 2.54 0) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 3 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 4 thru_hole oval (at 2.54 2.54) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 5 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 6 thru_hole oval (at 2.54 5.08) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 7 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 8 thru_hole oval (at 2.54 7.62) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 9 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 10 thru_hole oval (at 2.54 10.16) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 11 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 12 thru_hole oval (at 2.54 12.7) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 13 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 14 thru_hole oval (at 2.54 15.24) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 15 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 16 thru_hole oval (at 2.54 17.78) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 17 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 18 thru_hole oval (at 2.54 20.32) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 19 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 20 thru_hole oval (at 2.54 22.86) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 21 thru_hole oval (at 0 25.4) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 22 thru_hole oval (at 2.54 25.4) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 23 thru_hole oval (at 0 27.94) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 24 thru_hole oval (at 2.54 27.94) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 25 thru_hole oval (at 0 30.48) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 26 thru_hole oval (at 2.54 30.48) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 27 thru_hole oval (at 0 33.02) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 28 thru_hole oval (at 2.54 33.02) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 29 thru_hole oval (at 0 35.56) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 30 thru_hole oval (at 2.54 35.56) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 31 thru_hole oval (at 0 38.1) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 32 thru_hole oval (at 2.54 38.1) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 33 thru_hole oval (at 0 40.64) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 34 thru_hole oval (at 2.54 40.64) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 35 thru_hole oval (at 0 43.18) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 36 thru_hole oval (at 2.54 43.18) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 37 thru_hole oval (at 0 45.72) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 38 thru_hole oval (at 2.54 45.72) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 39 thru_hole oval (at 0 48.26) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 40 thru_hole oval (at 2.54 48.26) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 41 thru_hole oval (at 0 50.8) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 42 thru_hole oval (at 2.54 50.8) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 43 thru_hole oval (at 0 53.34) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 44 thru_hole oval (at 2.54 53.34) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 45 thru_hole oval (at 0 55.88) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 46 thru_hole oval (at 2.54 55.88) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 47 thru_hole oval (at 0 58.42) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 48 thru_hole oval (at 2.54 58.42) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 49 thru_hole oval (at 0 60.96) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 50 thru_hole oval (at 2.54 60.96) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 51 thru_hole oval (at 0 63.5) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 52 thru_hole oval (at 2.54 63.5) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 53 thru_hole oval (at 0 66.04) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 54 thru_hole oval (at 2.54 66.04) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 55 thru_hole oval (at 0 68.58) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 56 thru_hole oval (at 2.54 68.58) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 57 thru_hole oval (at 0 71.12) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 58 thru_hole oval (at 2.54 71.12) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 59 thru_hole oval (at 0 73.66) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 60 thru_hole oval (at 2.54 73.66) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 61 thru_hole oval (at 0 76.2) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 62 thru_hole oval (at 2.54 76.2) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 63 thru_hole oval (at 0 78.74) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(pad 64 thru_hole oval (at 2.54 78.74) (size 1.7 1.7) (drill 1.14) (layers *.Cu *.Mask))
|
||||
(fp_text user %R (at 1.27 39.37 90) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_2x32_P2.54mm_Vertical.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
33
nubus-to-ztex/NuBus/47219-2001.lib
Normal file
33
nubus-to-ztex/NuBus/47219-2001.lib
Normal file
|
@ -0,0 +1,33 @@
|
|||
EESchema-LIBRARY Version 2.3
|
||||
#encoding utf-8
|
||||
#(c) SnapEDA 2016 (snapeda.com)
|
||||
#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
|
||||
#
|
||||
# 47219-2001
|
||||
#
|
||||
DEF 47219-2001 J 0 40 Y Y 1 L N
|
||||
F0 "J" -500 430 50 H V L BNN
|
||||
F1 "47219-2001" -500 -470 50 H V L BNN
|
||||
F2 "MOLEX_47219-2001" 0 0 50 H I L BNN
|
||||
F3 "MOLEX" 0 0 50 H I L BNN
|
||||
DRAW
|
||||
P 2 0 0 10 -500 400 -500 -400 N
|
||||
P 2 0 0 10 -500 -400 500 -400 N
|
||||
P 2 0 0 10 500 -400 500 400 N
|
||||
P 2 0 0 10 500 400 -500 400 N
|
||||
X DAT2 1 -700 -200 200 R 40 40 0 0 B
|
||||
X CD/DAT3 2 -700 -300 200 R 40 40 0 0 B
|
||||
X CMD 3 -700 100 200 R 40 40 0 0 B
|
||||
X VDD 4 700 300 200 L 40 40 0 0 W
|
||||
X CLK 5 -700 300 200 R 40 40 0 0 I C
|
||||
X VSS 6 700 -300 200 L 40 40 0 0 W
|
||||
X DAT0 7 -700 0 200 R 40 40 0 0 B
|
||||
X DAT1 8 -700 -100 200 R 40 40 0 0 B
|
||||
X GND@1 G1 700 100 200 L 40 40 0 0 W
|
||||
X GND@2 G2 700 0 200 L 40 40 0 0 W
|
||||
X GND@3 G3 700 -100 200 L 40 40 0 0 W
|
||||
X GND@4 G4 700 -200 200 L 40 40 0 0 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# End Library
|
39
nubus-to-ztex/NuBus/74LVC125APW_112.lib
Normal file
39
nubus-to-ztex/NuBus/74LVC125APW_112.lib
Normal file
|
@ -0,0 +1,39 @@
|
|||
EESchema-LIBRARY Version 2.3
|
||||
#encoding utf-8
|
||||
#(c) SnapEDA 2016 (snapeda.com)
|
||||
#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
|
||||
#
|
||||
# 74LVC125APW,112
|
||||
#
|
||||
DEF 74LVC125APW,112 U 0 40 Y Y 1 L N
|
||||
F0 "U" -211 803 50 H V L BNN
|
||||
F1 "74LVC125APW,112" -160 -1099 50 H V L BNN
|
||||
F2 "SOP65P640X110-14N" 0 0 50 H I L BNN
|
||||
F3 "1826647" 0 0 50 H I L BNN
|
||||
F4 "74LVC125APW,112" 0 0 50 H I L BNN
|
||||
F5 "TSSOP-14" 0 0 50 H I L BNN
|
||||
F6 "78R7407" 0 0 50 H I L BNN
|
||||
F7 "NXP" 0 0 50 H I L BNN
|
||||
DRAW
|
||||
P 2 0 0 16 -500 700 -500 -900 N
|
||||
P 2 0 0 16 -500 -900 500 -900 N
|
||||
P 2 0 0 16 500 -900 500 700 N
|
||||
P 2 0 0 16 500 700 -500 700 N
|
||||
X VCC 14 -700 500 200 R 40 40 0 0 W
|
||||
X 1~OE 1 -700 300 200 R 40 40 0 0 I
|
||||
X 2~OE 4 -700 200 200 R 40 40 0 0 I
|
||||
X 3~OE 10 -700 100 200 R 40 40 0 0 I
|
||||
X 4~OE 13 -700 0 200 R 40 40 0 0 I
|
||||
X 1A 2 -700 -200 200 R 40 40 0 0 I
|
||||
X 2A 5 -700 -300 200 R 40 40 0 0 I
|
||||
X 3A 9 -700 -400 200 R 40 40 0 0 I
|
||||
X 4A 12 -700 -500 200 R 40 40 0 0 I
|
||||
X GND 7 -700 -700 200 R 40 40 0 0 I
|
||||
X 1Y 3 700 -200 200 L 40 40 0 0 O
|
||||
X 2Y 6 700 -300 200 L 40 40 0 0 O
|
||||
X 3Y 8 700 -400 200 L 40 40 0 0 O
|
||||
X 4Y 11 700 -500 200 L 40 40 0 0 O
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# End Library
|
39
nubus-to-ztex/NuBus/74LVC126AD_118.lib
Normal file
39
nubus-to-ztex/NuBus/74LVC126AD_118.lib
Normal file
|
@ -0,0 +1,39 @@
|
|||
EESchema-LIBRARY Version 2.3
|
||||
#encoding utf-8
|
||||
#(c) SnapEDA 2016 (snapeda.com)
|
||||
#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
|
||||
#
|
||||
# 74LVC126AD,118
|
||||
#
|
||||
DEF 74LVC126AD,118 U 0 40 Y Y 1 L N
|
||||
F0 "U" -212 804 50 H V L BNN
|
||||
F1 "74LVC126AD,118" -184 -1082 50 H V L BNN
|
||||
F2 "SOIC127P600X175-14N" 0 0 50 H I L BNN
|
||||
F3 "NXP" 0 0 50 H I L BNN
|
||||
F4 "1631665" 0 0 50 H I L BNN
|
||||
F5 "74LVC126AD,118" 0 0 50 H I L BNN
|
||||
F6 "03P2781" 0 0 50 H I L BNN
|
||||
F7 "SOIC-14" 0 0 50 H I L BNN
|
||||
DRAW
|
||||
P 2 0 0 16 -500 700 -500 -900 N
|
||||
P 2 0 0 16 -500 -900 500 -900 N
|
||||
P 2 0 0 16 500 -900 500 700 N
|
||||
P 2 0 0 16 500 700 -500 700 N
|
||||
X VCC 14 -700 500 200 R 40 40 0 0 W
|
||||
X 1OE 1 -700 300 200 R 40 40 0 0 I
|
||||
X 2OE 4 -700 200 200 R 40 40 0 0 I
|
||||
X 3OE 10 -700 100 200 R 40 40 0 0 I
|
||||
X 4OE 13 -700 0 200 R 40 40 0 0 I
|
||||
X 1A 2 -700 -200 200 R 40 40 0 0 I
|
||||
X 2A 5 -700 -300 200 R 40 40 0 0 I
|
||||
X 3A 9 -700 -400 200 R 40 40 0 0 I
|
||||
X 4A 12 -700 -500 200 R 40 40 0 0 I
|
||||
X GND 7 -700 -700 200 R 40 40 0 0 P
|
||||
X 1Y 3 700 -200 200 L 40 40 0 0 O
|
||||
X 2Y 6 700 -300 200 L 40 40 0 0 O
|
||||
X 3Y 8 700 -400 200 L 40 40 0 0 O
|
||||
X 4Y 11 700 -500 200 L 40 40 0 0 O
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# End Library
|
109
nubus-to-ztex/NuBus/C96ABC.lib
Normal file
109
nubus-to-ztex/NuBus/C96ABC.lib
Normal file
|
@ -0,0 +1,109 @@
|
|||
EESchema-LIBRARY Version 2.4
|
||||
#
|
||||
# C96ABC_NUBUS
|
||||
#
|
||||
DEF C96ABC_NUBUS J 0 20 Y Y 1 F N
|
||||
F0 "J" 0 4950 50 H V C CNN
|
||||
F1 "C96ABC_NUBUS" 250 50 50 V V C CNN
|
||||
F2 "" 0 50 50 H I C CNN
|
||||
F3 "" 0 50 50 H I C CNN
|
||||
DRAW
|
||||
S -150 -4800 150 4900 0 1 10 f
|
||||
X a1 a1 -300 4800 150 R 50 50 1 1 P
|
||||
X a10 a10 -300 2100 150 R 50 50 1 1 P
|
||||
X a11 a11 -300 1800 150 R 50 50 1 1 P
|
||||
X a12 a12 -300 1500 150 R 50 50 1 1 P
|
||||
X a13 a13 -300 1200 150 R 50 50 1 1 P
|
||||
X a14 a14 -300 900 150 R 50 50 1 1 P
|
||||
X a15 a15 -300 600 150 R 50 50 1 1 P
|
||||
X a16 a16 -300 300 150 R 50 50 1 1 P
|
||||
X a17 a17 -300 0 150 R 50 50 1 1 P
|
||||
X a18 a18 -300 -300 150 R 50 50 1 1 P
|
||||
X a19 a19 -300 -600 150 R 50 50 1 1 P
|
||||
X a2 a2 -300 4500 150 R 50 50 1 1 P
|
||||
X a20 a20 -300 -900 150 R 50 50 1 1 P
|
||||
X a21 a21 -300 -1200 150 R 50 50 1 1 T
|
||||
X a22 a22 -300 -1500 150 R 50 50 1 1 P
|
||||
X a23 a23 -300 -1800 150 R 50 50 1 1 P
|
||||
X a24 a24 -300 -2100 150 R 50 50 1 1 P
|
||||
X a25 a25 -300 -2400 150 R 50 50 1 1 P
|
||||
X a26 a26 -300 -2700 150 R 50 50 1 1 P
|
||||
X a27 a27 -300 -3000 150 R 50 50 1 1 P
|
||||
X a28 a28 -300 -3300 150 R 50 50 1 1 P
|
||||
X a29 a29 -300 -3600 150 R 50 50 1 1 P
|
||||
X a3 a3 -300 4200 150 R 50 50 1 1 P
|
||||
X a30 a30 -300 -3900 150 R 50 50 1 1 P
|
||||
X a31 a31 -300 -4200 150 R 50 50 1 1 P
|
||||
X a32 a32 -300 -4500 150 R 50 50 1 1 P
|
||||
X a4 a4 -300 3900 150 R 50 50 1 1 P
|
||||
X a5 a5 -300 3600 150 R 50 50 1 1 P
|
||||
X a6 a6 -300 3300 150 R 50 50 1 1 P
|
||||
X a7 a7 -300 3000 150 R 50 50 1 1 P
|
||||
X a8 a8 -300 2700 150 R 50 50 1 1 P
|
||||
X a9 a9 -300 2400 150 R 50 50 1 1 P
|
||||
X b1 b1 -300 4700 150 R 50 50 1 1 P
|
||||
X b10 b10 -300 2000 150 R 50 50 1 1 P
|
||||
X b11 b11 -300 1700 150 R 50 50 1 1 P
|
||||
X b12 b12 -300 1400 150 R 50 50 1 1 P
|
||||
X b13 b13 -300 1100 150 R 50 50 1 1 P
|
||||
X b14 b14 -300 800 150 R 50 50 1 1 P
|
||||
X b15 b15 -300 500 150 R 50 50 1 1 P
|
||||
X b16 b16 -300 200 150 R 50 50 1 1 P
|
||||
X b17 b17 -300 -100 150 R 50 50 1 1 P
|
||||
X b18 b18 -300 -400 150 R 50 50 1 1 P
|
||||
X b19 b19 -300 -700 150 R 50 50 1 1 P
|
||||
X b2 b2 -300 4400 150 R 50 50 1 1 P
|
||||
X b20 b20 -300 -1000 150 R 50 50 1 1 P
|
||||
X b21 b21 -300 -1300 150 R 50 50 1 1 P
|
||||
X b22 b22 -300 -1600 150 R 50 50 1 1 P
|
||||
X b23 b23 -300 -1900 150 R 50 50 1 1 P
|
||||
X b24 b24 -300 -2200 150 R 50 50 1 1 P
|
||||
X b25 b25 -300 -2500 150 R 50 50 1 1 P
|
||||
X b26 b26 -300 -2800 150 R 50 50 1 1 P
|
||||
X b27 b27 -300 -3100 150 R 50 50 1 1 P
|
||||
X b28 b28 -300 -3400 150 R 50 50 1 1 P
|
||||
X b29 b29 -300 -3700 150 R 50 50 1 1 P
|
||||
X b3 b3 -300 4100 150 R 50 50 1 1 P
|
||||
X b30 b30 -300 -4000 150 R 50 50 1 1 P
|
||||
X b31 b31 -300 -4300 150 R 50 50 1 1 P
|
||||
X b32 b32 -300 -4600 150 R 50 50 1 1 P
|
||||
X b4 b4 -300 3800 150 R 50 50 1 1 P
|
||||
X b5 b5 -300 3500 150 R 50 50 1 1 P
|
||||
X b6 b6 -300 3200 150 R 50 50 1 1 P
|
||||
X b7 b7 -300 2900 150 R 50 50 1 1 P
|
||||
X b8 b8 -300 2600 150 R 50 50 1 1 P
|
||||
X b9 b9 -300 2300 150 R 50 50 1 1 P
|
||||
X c1 c1 -300 4600 150 R 50 50 1 1 P
|
||||
X c10 c10 -300 1900 150 R 50 50 1 1 P
|
||||
X c11 c11 -300 1600 150 R 50 50 1 1 P
|
||||
X c12 c12 -300 1300 150 R 50 50 1 1 P
|
||||
X c13 c13 -300 1000 150 R 50 50 1 1 P
|
||||
X c14 c14 -300 700 150 R 50 50 1 1 P
|
||||
X c15 c15 -300 400 150 R 50 50 1 1 P
|
||||
X c16 c16 -300 100 150 R 50 50 1 1 P
|
||||
X c17 c17 -300 -200 150 R 50 50 1 1 P
|
||||
X c18 c18 -300 -500 150 R 50 50 1 1 P
|
||||
X c19 c19 -300 -800 150 R 50 50 1 1 P
|
||||
X c2 c2 -300 4300 150 R 50 50 1 1 P
|
||||
X c20 c20 -300 -1100 150 R 50 50 1 1 P
|
||||
X c21 c21 -300 -1400 150 R 50 50 1 1 P
|
||||
X c22 c22 -300 -1700 150 R 50 50 1 1 P
|
||||
X c23 c23 -300 -2000 150 R 50 50 1 1 P
|
||||
X c24 c24 -300 -2300 150 R 50 50 1 1 P
|
||||
X c25 c25 -300 -2600 150 R 50 50 1 1 P
|
||||
X c26 c26 -300 -2900 150 R 50 50 1 1 P
|
||||
X c27 c27 -300 -3200 150 R 50 50 1 1 P
|
||||
X c28 c28 -300 -3500 150 R 50 50 1 1 P
|
||||
X c29 c29 -300 -3800 150 R 50 50 1 1 P
|
||||
X c3 c3 -300 4000 150 R 50 50 1 1 P
|
||||
X c30 c30 -300 -4100 150 R 50 50 1 1 P
|
||||
X c31 c31 -300 -4400 150 R 50 50 1 1 P
|
||||
X c32 c32 -300 -4700 150 R 50 50 1 1 P
|
||||
X c4 c4 -300 3700 150 R 50 50 1 1 P
|
||||
X c5 c5 -300 3400 150 R 50 50 1 1 P
|
||||
X c6 c6 -300 3100 150 R 50 50 1 1 P
|
||||
X c7 c7 -300 2800 150 R 50 50 1 1 P
|
||||
X c8 c8 -300 2500 150 R 50 50 1 1 P
|
||||
X c9 c9 -300 2200 150 R 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
|
@ -0,0 +1,41 @@
|
|||
SBUS_A=71.0;
|
||||
SBUS_B=59.69;
|
||||
SBUS_C=64.06;
|
||||
SBUS_HOLE_WIDE=64.06;
|
||||
SBUS_HOLE_NARROW=59.69;
|
||||
SBUS_HOLE_WIDTH=5.7;
|
||||
SBUS_WIDTH=7.3;
|
||||
SBUS_HEIGHT=9.3;
|
||||
|
||||
HolePoints = [
|
||||
[ -SBUS_HOLE_NARROW/2, -SBUS_HOLE_WIDTH/2, -SBUS_HEIGHT/2+3 ], //0
|
||||
[ +SBUS_HOLE_NARROW/2, -SBUS_HOLE_WIDTH/2, -SBUS_HEIGHT/2+3 ], //1
|
||||
[ +SBUS_HOLE_WIDE/2, +SBUS_HOLE_WIDTH/2, -SBUS_HEIGHT/2+3 ], //2
|
||||
[ -SBUS_HOLE_WIDE/2, +SBUS_HOLE_WIDTH/2, ], //3
|
||||
[ -SBUS_HOLE_NARROW/2, -SBUS_HOLE_WIDTH/2, 20 ], //4
|
||||
[ +SBUS_HOLE_NARROW/2, -SBUS_HOLE_WIDTH/2, 20 ], //5
|
||||
[ +SBUS_HOLE_WIDE/2, +SBUS_HOLE_WIDTH/2, 20 ], //6
|
||||
[ -SBUS_HOLE_WIDE/2, +SBUS_HOLE_WIDTH/2, 20 ], //7
|
||||
]; //7
|
||||
|
||||
HoleFaces = [
|
||||
[0,1,2,3], // bottom
|
||||
[4,5,1,0], // front
|
||||
[7,6,5,4], // top
|
||||
[5,6,2,1], // right
|
||||
[6,7,3,2], // back
|
||||
[7,4,0,3]]; // left
|
||||
|
||||
difference() {
|
||||
color("black") cube([SBUS_A, SBUS_WIDTH, SBUS_HEIGHT], center=true);
|
||||
color("black") polyhedron( HolePoints, HoleFaces );
|
||||
}
|
||||
|
||||
for (i = [0 : 47]) {
|
||||
translate([-SBUS_B/2+i*1.27, -1.27, 0]) {
|
||||
color("silver") cylinder(h = 8, r1 = 0.2, r2 = 0.2, center = true);
|
||||
}
|
||||
translate([-SBUS_B/2+i*1.27, +1.27, 0]) {
|
||||
color("silver") cylinder(h = 8, r1 = 0.2, r2 = 0.2, center = true);
|
||||
}
|
||||
}
|
5578
nubus-to-ztex/NuBus/FCN-234P096-GY.3dshapes/FCN-234P096-GY.wrl
Normal file
5578
nubus-to-ztex/NuBus/FCN-234P096-GY.3dshapes/FCN-234P096-GY.wrl
Normal file
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,119 @@
|
|||
(module FCN-234P096-GY (layer F.Cu) (tedit 5F5F8C3D)
|
||||
(descr "FCN-234P096-GY connector (daughtercard)")
|
||||
(tags FCN-234P096-GY)
|
||||
(fp_text reference FCN-234P096-GY (at -32.5 0) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value FCN-234P096-GY (at -32.5 0) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -35.5 -3.65) (end -35.5 3.65) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -35.5 3.65) (end 35.5 3.65) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 35.5 3.65) (end 35.5 -3.65) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 35.5 -3.65) (end -35.5 -3.65) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -35.5 -3.65) (end -35.5 3.65) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -35.5 3.65) (end 35.5 3.65) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 35.5 3.65) (end 35.5 -3.65) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 35.5 -3.65) (end -35.5 -3.65) (layer F.CrtYd) (width 0.05))
|
||||
(pad 01 thru_hole rect (at -29.845 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 03 thru_hole circle (at -27.305 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 05 thru_hole circle (at -24.765 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 07 thru_hole circle (at -22.225 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 09 thru_hole circle (at -19.685 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 11 thru_hole circle (at -17.145 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 13 thru_hole circle (at -14.605 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 15 thru_hole circle (at -12.065 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 17 thru_hole circle (at -9.525 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 19 thru_hole circle (at -6.985 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 21 thru_hole circle (at -4.445 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 23 thru_hole circle (at -1.905 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 25 thru_hole circle (at 0.635 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 27 thru_hole circle (at 3.175 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 29 thru_hole circle (at 5.715 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 31 thru_hole circle (at 8.255 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 33 thru_hole circle (at 10.795 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 35 thru_hole circle (at 13.335 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 37 thru_hole circle (at 15.875 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 39 thru_hole circle (at 18.415 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 41 thru_hole circle (at 20.955 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 43 thru_hole circle (at 23.495 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 45 thru_hole circle (at 26.035 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 47 thru_hole circle (at 28.575 -2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 02 thru_hole circle (at -28.575 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 04 thru_hole circle (at -26.035 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 06 thru_hole circle (at -23.495 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 08 thru_hole circle (at -20.955 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 10 thru_hole circle (at -18.415 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 12 thru_hole circle (at -15.875 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 14 thru_hole circle (at -13.335 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 16 thru_hole circle (at -10.795 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 18 thru_hole circle (at -8.255 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 20 thru_hole circle (at -5.715 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 22 thru_hole circle (at -3.175 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 24 thru_hole circle (at -0.635 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 26 thru_hole circle (at 1.905 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 28 thru_hole circle (at 4.445 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 30 thru_hole circle (at 6.985 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 32 thru_hole circle (at 9.525 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 34 thru_hole circle (at 12.065 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 36 thru_hole circle (at 14.605 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 38 thru_hole circle (at 17.145 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 40 thru_hole circle (at 19.685 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 42 thru_hole circle (at 22.225 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 44 thru_hole circle (at 24.765 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 46 thru_hole circle (at 27.305 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 48 thru_hole circle (at 29.845 -0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 49 thru_hole circle (at -29.845 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 51 thru_hole circle (at -27.305 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 53 thru_hole circle (at -24.765 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 55 thru_hole circle (at -22.225 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 57 thru_hole circle (at -19.685 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 59 thru_hole circle (at -17.145 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 61 thru_hole circle (at -14.605 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 63 thru_hole circle (at -12.065 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 65 thru_hole circle (at -9.525 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 67 thru_hole circle (at -6.985 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 69 thru_hole circle (at -4.445 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 71 thru_hole circle (at -1.905 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 73 thru_hole circle (at 0.635 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 75 thru_hole circle (at 3.175 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 77 thru_hole circle (at 5.715 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 79 thru_hole circle (at 8.255 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 81 thru_hole circle (at 10.795 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 83 thru_hole circle (at 13.335 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 85 thru_hole circle (at 15.875 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 87 thru_hole circle (at 18.415 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 89 thru_hole circle (at 20.955 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 91 thru_hole circle (at 23.495 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 93 thru_hole circle (at 26.035 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 95 thru_hole circle (at 28.575 0.9525) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 50 thru_hole circle (at -28.575 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 52 thru_hole circle (at -26.035 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 54 thru_hole circle (at -23.495 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 56 thru_hole circle (at -20.955 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 58 thru_hole circle (at -18.415 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 60 thru_hole circle (at -15.875 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 62 thru_hole circle (at -13.335 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 64 thru_hole circle (at -10.795 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 66 thru_hole circle (at -8.255 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 68 thru_hole circle (at -5.715 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 70 thru_hole circle (at -3.175 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 72 thru_hole circle (at -0.635 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 74 thru_hole circle (at 1.905 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 76 thru_hole circle (at 4.445 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 78 thru_hole circle (at 6.985 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 80 thru_hole circle (at 9.525 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 82 thru_hole circle (at 12.065 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 84 thru_hole circle (at 14.605 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 86 thru_hole circle (at 17.145 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 88 thru_hole circle (at 19.685 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 90 thru_hole circle (at 22.225 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 92 thru_hole circle (at 24.765 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 94 thru_hole circle (at 27.305 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 96 thru_hole circle (at 29.845 2.8575) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(model ./footprints/SBus/FCN-234P096-GY.3dshapes/FCN-234P096-GY.wrl
|
||||
(at (xyz 0 0 .18307086614173228346))
|
||||
(scale (xyz 0.3937 0.3937 0.3937))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
|
@ -0,0 +1,41 @@
|
|||
|
||||
(module MOLEX_47219-2001 (layer F.Cu) (tedit 5F6EE96D)
|
||||
(descr "")
|
||||
(fp_text reference REF** (at -8.845525 2.928495 900) (layer F.SilkS)
|
||||
(effects (font (size 1.00118897638 1.00118897638) (thickness 0.015)))
|
||||
)
|
||||
(fp_text value MOLEX_47219-2001 (at 8.61729 -4.41119 900) (layer F.Fab)
|
||||
(effects (font (size 1.00026771654 1.00026771654) (thickness 0.015)))
|
||||
)
|
||||
(fp_line (start -6.8 7.25) (end 6.8 7.25) (layer F.SilkS) (width 0.127))
|
||||
(fp_line (start -6.8 -7.25) (end 6.8 -7.25) (layer F.SilkS) (width 0.127))
|
||||
(fp_line (start -6.8 -7.2) (end -6.8 -4.8) (layer F.SilkS) (width 0.127))
|
||||
(fp_line (start -6.8 5.9) (end -6.8 3.5) (layer F.Fab) (width 0.127))
|
||||
(fp_line (start -6.8 -2.3) (end -6.8 -4.8) (layer F.Fab) (width 0.127))
|
||||
(fp_line (start 6.8 -7.2) (end 6.8 -4.8) (layer F.SilkS) (width 0.127))
|
||||
(fp_line (start 6.8 -4.8) (end 6.8 5.9) (layer F.Fab) (width 0.127))
|
||||
(fp_line (start -6.0 7.2) (end -6.0 6.5) (layer F.SilkS) (width 0.127))
|
||||
(fp_line (start 6.0 7.2) (end 6.0 6.5) (layer F.SilkS) (width 0.127))
|
||||
(fp_line (start -6.0 6.5) (end -4.3 5.5) (layer F.SilkS) (width 0.127))
|
||||
(fp_line (start -4.3 5.5) (end -1.9 4.9) (layer F.SilkS) (width 0.127))
|
||||
(fp_line (start -1.9 4.9) (end 1.6 4.9) (layer F.SilkS) (width 0.127))
|
||||
(fp_line (start 1.6 4.9) (end 4.2 5.5) (layer F.SilkS) (width 0.127))
|
||||
(fp_line (start 4.2 5.5) (end 6.0 6.5) (layer F.SilkS) (width 0.127))
|
||||
(fp_line (start -6.8 -4.8) (end 6.8 -4.8) (layer F.SilkS) (width 0.127))
|
||||
(fp_line (start -7.9 -7.6) (end 7.9 -7.6) (layer F.CrtYd) (width 0.127))
|
||||
(fp_line (start 7.9 -7.6) (end 7.9 7.6) (layer F.CrtYd) (width 0.127))
|
||||
(fp_line (start 7.9 7.6) (end -7.9 7.6) (layer F.CrtYd) (width 0.127))
|
||||
(fp_line (start -7.9 7.6) (end -7.9 -7.6) (layer F.CrtYd) (width 0.127))
|
||||
(pad 1 smd rect (at 3.2 2.1) (size 0.8 1.5) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 2 smd rect (at 2.1 2.1) (size 0.8 1.5) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 3 smd rect (at 1.0 2.1) (size 0.8 1.5) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 4 smd rect (at -0.1 2.1) (size 0.8 1.5) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 5 smd rect (at -1.2 2.1) (size 0.8 1.5) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 6 smd rect (at -2.3 2.1) (size 0.8 1.5) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 7 smd rect (at -3.4 2.1) (size 0.8 1.5) (layers F.Cu F.Mask F.Paste))
|
||||
(pad 8 smd rect (at -4.5 2.1) (size 0.8 1.5) (layers F.Cu F.Mask F.Paste))
|
||||
(pad G1 smd rect (at 6.875 4.7) (size 1.5 2.05) (layers F.Cu F.Mask F.Paste))
|
||||
(pad G2 smd rect (at 6.875 -3.6) (size 1.5 2.05) (layers F.Cu F.Mask F.Paste))
|
||||
(pad G3 smd rect (at -6.875 -3.6) (size 1.5 2.05) (layers F.Cu F.Mask F.Paste))
|
||||
(pad G4 smd rect (at -6.875 4.7) (size 1.5 2.05) (layers F.Cu F.Mask F.Paste))
|
||||
)
|
114
nubus-to-ztex/NuBus/NuBus.lib
Normal file
114
nubus-to-ztex/NuBus/NuBus.lib
Normal file
|
@ -0,0 +1,114 @@
|
|||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# NuBus
|
||||
#
|
||||
DEF NuBus NuBus 0 40 Y Y 1 F N
|
||||
F0 "NuBus" -300 0 50 H V C CNN
|
||||
F1 "NuBus" 0 0 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
X GND 01 0 1100 25 R 50 50 1 1 P X
|
||||
X BR* 02 0 1000 25 R 50 50 1 1 B X
|
||||
X SEL* 03 0 900 25 R 50 50 1 1 B X
|
||||
X INT[1]* 04 0 800 25 R 50 50 1 1 B X
|
||||
X D[00] 05 0 700 25 R 50 50 1 1 B X
|
||||
X D[02] 06 0 600 25 R 50 50 1 1 B X
|
||||
X D[04] 07 0 500 25 R 50 50 1 1 B X
|
||||
X INT[2]* 08 0 400 25 R 50 50 1 1 B X
|
||||
X D[06] 09 0 300 25 R 50 50 1 1 B X
|
||||
X D[08] 10 0 200 25 R 50 50 1 1 B X
|
||||
X D[10] 11 0 100 25 R 50 50 1 1 B X
|
||||
X INT[3]* 12 0 0 25 R 50 50 1 1 B X
|
||||
X D[12] 13 0 -100 25 R 50 50 1 1 B X
|
||||
X D[14] 14 0 -200 25 R 50 50 1 1 B X
|
||||
X D[16] 15 0 -300 25 R 50 50 1 1 B X
|
||||
X INT[4]* 16 0 -400 25 R 50 50 1 1 B X
|
||||
X D[19] 17 0 -500 25 R 50 50 1 1 B X
|
||||
X D[21] 18 0 -600 25 R 50 50 1 1 B X
|
||||
X D[23] 19 0 -700 25 R 50 50 1 1 B X
|
||||
X INT[5]* 20 0 -800 25 R 50 50 1 1 B X
|
||||
X D[25] 21 0 -900 25 R 50 50 1 1 B X
|
||||
X D[27] 22 0 -1000 25 R 50 50 1 1 B X
|
||||
X D[29] 23 0 -1100 25 R 50 50 1 1 B X
|
||||
X INT[6]* 24 0 -1200 25 R 50 50 1 1 B X
|
||||
X D[31] 25 500 1100 25 R 50 50 1 1 B X
|
||||
X SIZ[0] 26 500 1000 25 R 50 50 1 1 B X
|
||||
X SIZ[2] 27 500 900 25 R 50 50 1 1 B X
|
||||
X INT[7]* 28 500 800 25 R 50 50 1 1 B X
|
||||
X PA[00] 29 500 700 25 R 50 50 1 1 B X
|
||||
X PA[02] 30 500 600 25 R 50 50 1 1 B X
|
||||
X PA[04] 31 500 500 25 R 50 50 1 1 B X
|
||||
X EER* 32 500 400 25 R 50 50 1 1 B X
|
||||
X PA[06] 33 500 300 25 R 50 50 1 1 B X
|
||||
X PA[08] 34 500 200 25 R 50 50 1 1 B X
|
||||
X PA[10] 35 500 100 25 R 50 50 1 1 B X
|
||||
X ACK[0]* 36 500 0 25 R 50 50 1 1 B X
|
||||
X PA[12] 37 500 -100 25 R 50 50 1 1 B X
|
||||
X PA[14] 38 500 -200 25 R 50 50 1 1 B X
|
||||
X PA[16] 39 500 -300 25 R 50 50 1 1 B X
|
||||
X ACK[1]* 40 500 -400 25 R 50 50 1 1 B X
|
||||
X PA[18] 41 500 -500 25 R 50 50 1 1 B X
|
||||
X PA[20] 42 500 -600 25 R 50 50 1 1 B X
|
||||
X PA[22] 43 500 -700 25 R 50 50 1 1 B X
|
||||
X ACK[2]* 44 500 -800 25 R 50 50 1 1 B X
|
||||
X PA[24] 45 500 -900 25 R 50 50 1 1 B X
|
||||
X PA[26] 46 500 -1000 25 R 50 50 1 1 B X
|
||||
X DP 47 500 -1100 25 R 50 50 1 1 B X
|
||||
X -12V 48 500 -1200 25 R 50 50 1 1 W X
|
||||
X CLK 49 1000 1100 25 R 50 50 1 1 B X
|
||||
X BG* 50 1000 1000 25 R 50 50 1 1 B X
|
||||
X AS* 51 1000 900 25 R 50 50 1 1 B X
|
||||
X GND 52 1000 800 25 R 50 50 1 1 P X
|
||||
X D[01] 53 1000 700 25 R 50 50 1 1 B X
|
||||
X D[03] 54 1000 600 25 R 50 50 1 1 B X
|
||||
X D[05] 55 1000 500 25 R 50 50 1 1 B X
|
||||
X +5V 56 1000 400 25 R 50 50 1 1 W X
|
||||
X D[07] 57 1000 300 25 R 50 50 1 1 B X
|
||||
X D[09] 58 1000 200 25 R 50 50 1 1 B X
|
||||
X D[11] 59 1000 100 25 R 50 50 1 1 B X
|
||||
X GND 60 1000 0 25 R 50 50 1 1 P X
|
||||
X D[13] 61 1000 -100 25 R 50 50 1 1 B X
|
||||
X D[15] 62 1000 -200 25 R 50 50 1 1 B X
|
||||
X D[17] 63 1000 -300 25 R 50 50 1 1 B X
|
||||
X +5V 64 1000 -400 25 R 50 50 1 1 W X
|
||||
X D[18] 65 1000 -500 25 R 50 50 1 1 B X
|
||||
X D[20] 66 1000 -600 25 R 50 50 1 1 B X
|
||||
X D[22] 67 1000 -700 25 R 50 50 1 1 B X
|
||||
X GND 68 1000 -800 25 R 50 50 1 1 P X
|
||||
X D[24] 69 1000 -900 25 R 50 50 1 1 B X
|
||||
X D[26] 70 1000 -1000 25 R 50 50 1 1 B X
|
||||
X D[28] 71 1000 -1100 25 R 50 50 1 1 B X
|
||||
X +5V 72 1000 -1200 25 R 50 50 1 1 W X
|
||||
X D[30] 73 1500 1100 25 R 50 50 1 1 B X
|
||||
X SIZ[1] 74 1500 1000 25 R 50 50 1 1 B X
|
||||
X PPRD 75 1500 900 25 R 50 50 1 1 B X
|
||||
X GND 76 1500 800 25 R 50 50 1 1 P X
|
||||
X PA[01] 77 1500 700 25 R 50 50 1 1 B X
|
||||
X PA[03] 78 1500 600 25 R 50 50 1 1 B X
|
||||
X PA[05] 79 1500 500 25 R 50 50 1 1 B X
|
||||
X +5V 80 1500 400 25 R 50 50 1 1 W X
|
||||
X PA[07] 81 1500 300 25 R 50 50 1 1 B X
|
||||
X PA[09] 82 1500 200 25 R 50 50 1 1 B X
|
||||
X PA[11] 83 1500 100 25 R 50 50 1 1 B X
|
||||
X GND 84 1500 0 25 R 50 50 1 1 P X
|
||||
X PA[13] 85 1500 -100 25 R 50 50 1 1 B X
|
||||
X PA[15] 86 1500 -200 25 R 50 50 1 1 B X
|
||||
X PA[17] 87 1500 -300 25 R 50 50 1 1 B X
|
||||
X +5V 88 1500 -400 25 R 50 50 1 1 W X
|
||||
X PA[19] 89 1500 -500 25 R 50 50 1 1 B X
|
||||
X PA[21] 90 1500 -600 25 R 50 50 1 1 B X
|
||||
X PA[23] 91 1500 -700 25 R 50 50 1 1 B X
|
||||
X GND 92 1500 -800 25 R 50 50 1 1 P X
|
||||
X PA[25] 93 1500 -900 25 R 50 50 1 1 B X
|
||||
X PA[27] 94 1500 -1000 25 R 50 50 1 1 B X
|
||||
X RST* 95 1500 -1100 25 R 50 50 1 1 B X
|
||||
X +12V 96 1500 -1200 25 R 50 50 1 1 W X
|
||||
ENDDRAW
|
||||
$FPLIST
|
||||
FCN-234P096-GY
|
||||
$ENDFPLIST
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
68
nubus-to-ztex/NuBus/SN74LVC16245ADGGR.lib
Normal file
68
nubus-to-ztex/NuBus/SN74LVC16245ADGGR.lib
Normal file
|
@ -0,0 +1,68 @@
|
|||
EESchema-LIBRARY Version 2.3
|
||||
#encoding utf-8
|
||||
#(c) SnapEDA 2016 (snapeda.com)
|
||||
#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
|
||||
#
|
||||
# SN74LVC16245ADGGR
|
||||
#
|
||||
DEF SN74LVC16245ADGGR U 0 40 Y Y 1 L N
|
||||
F0 "U" -500 1939 50 H V L BNN
|
||||
F1 "SN74LVC16245ADGGR" -500 -2057 50 H V L BNN
|
||||
F2 "SOP50P810X120-48N" 0 0 50 H I L BNN
|
||||
DRAW
|
||||
P 2 0 0 16 -500 1900 500 1900 N
|
||||
P 2 0 0 16 500 1900 500 -1900 N
|
||||
P 2 0 0 16 500 -1900 -500 -1900 N
|
||||
P 2 0 0 16 -500 -1900 -500 1900 N
|
||||
X 1DIR 1 -700 1300 200 R 40 40 0 0 I
|
||||
X 1OE 48 -700 1200 200 R 40 40 0 0 I
|
||||
X 2DIR 24 -700 1100 200 R 40 40 0 0 I
|
||||
X 2OE 25 -700 1000 200 R 40 40 0 0 I
|
||||
X 1A1 47 -700 800 200 R 40 40 0 0 B
|
||||
X 1A2 46 -700 700 200 R 40 40 0 0 B
|
||||
X 1A3 44 -700 600 200 R 40 40 0 0 B
|
||||
X 1A4 43 -700 500 200 R 40 40 0 0 B
|
||||
X 1A5 41 -700 400 200 R 40 40 0 0 B
|
||||
X 1A6 40 -700 300 200 R 40 40 0 0 B
|
||||
X 1A7 38 -700 200 200 R 40 40 0 0 B
|
||||
X 1A8 37 -700 100 200 R 40 40 0 0 B
|
||||
X 2A1 36 -700 -100 200 R 40 40 0 0 B
|
||||
X 2A2 35 -700 -200 200 R 40 40 0 0 B
|
||||
X 2A3 33 -700 -300 200 R 40 40 0 0 B
|
||||
X 2A4 32 -700 -400 200 R 40 40 0 0 B
|
||||
X 2A5 30 -700 -500 200 R 40 40 0 0 B
|
||||
X 2A6 29 -700 -600 200 R 40 40 0 0 B
|
||||
X 2A7 27 -700 -700 200 R 40 40 0 0 B
|
||||
X 2A8 26 -700 -800 200 R 40 40 0 0 B
|
||||
X VCC 7 700 1800 200 L 40 40 0 0 W
|
||||
X VCC-1 42 700 1700 200 L 40 40 0 0 W
|
||||
X VCC-2 18 700 1600 200 L 40 40 0 0 W
|
||||
X VCC-3 31 700 1500 200 L 40 40 0 0 W
|
||||
X 1B1 2 700 800 200 L 40 40 0 0 B
|
||||
X 1B2 3 700 700 200 L 40 40 0 0 B
|
||||
X 1B3 5 700 600 200 L 40 40 0 0 B
|
||||
X 1B4 6 700 500 200 L 40 40 0 0 B
|
||||
X 1B5 8 700 400 200 L 40 40 0 0 B
|
||||
X 1B6 9 700 300 200 L 40 40 0 0 B
|
||||
X 1B7 11 700 200 200 L 40 40 0 0 B
|
||||
X 1B8 12 700 100 200 L 40 40 0 0 B
|
||||
X 2B1 13 700 -100 200 L 40 40 0 0 B
|
||||
X 2B2 14 700 -200 200 L 40 40 0 0 B
|
||||
X 2B3 16 700 -300 200 L 40 40 0 0 B
|
||||
X 2B4 17 700 -400 200 L 40 40 0 0 B
|
||||
X 2B5 19 700 -500 200 L 40 40 0 0 B
|
||||
X 2B6 20 700 -600 200 L 40 40 0 0 B
|
||||
X 2B7 22 700 -700 200 L 40 40 0 0 B
|
||||
X 2B8 23 700 -800 200 L 40 40 0 0 B
|
||||
X GND-7 10 700 -1000 200 L 40 40 0 0 W
|
||||
X GND-6 34 700 -1100 200 L 40 40 0 0 W
|
||||
X GND-5 28 700 -1200 200 L 40 40 0 0 W
|
||||
X GND-4 45 700 -1300 200 L 40 40 0 0 W
|
||||
X GND-3 39 700 -1400 200 L 40 40 0 0 W
|
||||
X GND-2 4 700 -1500 200 L 40 40 0 0 W
|
||||
X GND-1 21 700 -1600 200 L 40 40 0 0 W
|
||||
X GND 15 700 -1700 200 L 40 40 0 0 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# End Library
|
70
nubus-to-ztex/NuBus/ul_SN74CB3T16210DGGR.lib
Normal file
70
nubus-to-ztex/NuBus/ul_SN74CB3T16210DGGR.lib
Normal file
|
@ -0,0 +1,70 @@
|
|||
EESchema-LIBRARY Version 2.3 Date: 21-02-2013 11:13:20
|
||||
#encoding utf-8
|
||||
#
|
||||
# SN74CB3T16210DGGR
|
||||
#
|
||||
DEF SN74CB3T16210DGGR U 0 10 Y Y 1 F N
|
||||
F0 "U" 800 400 60 H V C CNN
|
||||
F1 "SN74CB3T16210DGGR" 800 300 60 H V C CNN
|
||||
F2 "" 800 240 60 H I C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
$FPLIST
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
X NC 1 0 -2500 300 R 59 59 1 1 U
|
||||
X 1A1 2 1600 -300 300 L 59 59 1 1 B
|
||||
X 1A2 3 1600 -400 300 L 59 59 1 1 B
|
||||
X 1A3 4 1600 -500 300 L 59 59 1 1 B
|
||||
X 1A4 5 1600 -600 300 L 59 59 1 1 B
|
||||
X 1A5 6 1600 -700 300 L 59 59 1 1 B
|
||||
X 1A6 7 1600 -800 300 L 59 59 1 1 B
|
||||
X GND 8 1600 -2500 300 L 59 59 1 1 W
|
||||
X 1A7 9 1600 -900 300 L 59 59 1 1 B
|
||||
X 1A8 10 1600 -1000 300 L 59 59 1 1 B
|
||||
X 1A9 11 1600 -1100 300 L 59 59 1 1 B
|
||||
X 1A10 12 1600 -1200 300 L 59 59 1 1 B
|
||||
X 2A1 13 1600 -1400 300 L 59 59 1 1 B
|
||||
X 2A2 14 1600 -1500 300 L 59 59 1 1 B
|
||||
X VCC 15 0 -2600 300 R 59 59 1 1 W
|
||||
X 2A3 16 1600 -1600 300 L 59 59 1 1 B
|
||||
X GND 17 1600 -2600 300 L 59 59 1 1 W
|
||||
X 2A4 18 1600 -1700 300 L 59 59 1 1 B
|
||||
X 2A5 19 1600 -1800 300 L 59 59 1 1 B
|
||||
X 2A6 20 1600 -1900 300 L 59 59 1 1 B
|
||||
X 2A7 21 1600 -2000 300 L 59 59 1 1 B
|
||||
X 2A8 22 1600 -2100 300 L 59 59 1 1 B
|
||||
X 2A9 23 1600 -2200 300 L 59 59 1 1 B
|
||||
X 2A10 24 1600 -2300 300 L 59 59 1 1 B
|
||||
X 2B10 25 0 -2300 300 R 59 59 1 1 B
|
||||
X 2B9 26 0 -2200 300 R 59 59 1 1 B
|
||||
X 2B8 27 0 -2100 300 R 59 59 1 1 B
|
||||
X 2B7 28 0 -2000 300 R 59 59 1 1 B
|
||||
X 2B6 29 0 -1900 300 R 59 59 1 1 B
|
||||
X 2B5 30 0 -1800 300 R 59 59 1 1 B
|
||||
X 2B4 31 0 -1700 300 R 59 59 1 1 B
|
||||
X GND 32 1600 -2700 300 L 59 59 1 1 W
|
||||
X 2B3 33 0 -1600 300 R 59 59 1 1 B
|
||||
X 2B2 34 0 -1500 300 R 59 59 1 1 B
|
||||
X 2B1 35 0 -1400 300 R 59 59 1 1 B
|
||||
X 1B10 36 0 -1200 300 R 59 59 1 1 B
|
||||
X 1B9 37 0 -1100 300 R 59 59 1 1 B
|
||||
X 1B8 38 0 -1000 300 R 59 59 1 1 B
|
||||
X 1B7 39 0 -900 300 R 59 59 1 1 B
|
||||
X 1B6 40 0 -800 300 R 59 59 1 1 B
|
||||
X GND 41 1600 -2800 300 L 59 59 1 1 W
|
||||
X 1B5 42 0 -700 300 R 59 59 1 1 B
|
||||
X 1B4 43 0 -600 300 R 59 59 1 1 B
|
||||
X 1B3 44 0 -500 300 R 59 59 1 1 B
|
||||
X 1B2 45 0 -400 300 R 59 59 1 1 B
|
||||
X 1B1 46 0 -300 300 R 59 59 1 1 B
|
||||
X *2OE 47 0 -100 300 R 59 59 1 1 I
|
||||
X *1OE 48 0 0 300 R 59 59 1 1 I
|
||||
P 2 1 1 5 300 200 300 -3000 N
|
||||
P 2 1 1 5 300 -3000 1300 -3000 N
|
||||
P 2 1 1 5 1300 -3000 1300 200 N
|
||||
P 2 1 1 5 1300 200 300 200 N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
|
||||
#
|
||||
#End Library
|
80
nubus-to-ztex/NuBus/ul_SN74CB3T16211DGGR.lib
Normal file
80
nubus-to-ztex/NuBus/ul_SN74CB3T16211DGGR.lib
Normal file
|
@ -0,0 +1,80 @@
|
|||
EESchema-LIBRARY Version 2.3 Date: 21-02-2013 11:13:20
|
||||
#encoding utf-8
|
||||
#
|
||||
# SN74CB3T16211DGGR
|
||||
#
|
||||
DEF SN74CB3T16211DGGR U 0 10 Y Y 1 F N
|
||||
F0 "U" 800 400 60 H V C CNN
|
||||
F1 "SN74CB3T16211DGGR" 800 300 60 H V C CNN
|
||||
F2 "" 800 240 60 H I C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
$FPLIST
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
X NC 1 0 -3000 300 R 59 59 1 1 U
|
||||
X 1A1 2 1600 -400 300 L 59 59 1 1 B
|
||||
X 1A2 3 1600 -500 300 L 59 59 1 1 B
|
||||
X 1A3 4 1600 -600 300 L 59 59 1 1 B
|
||||
X 1A4 5 1600 -700 300 L 59 59 1 1 B
|
||||
X 1A5 6 1600 -800 300 L 59 59 1 1 B
|
||||
X 1A6 7 1600 -900 300 L 59 59 1 1 B
|
||||
X GND 8 1600 -3000 300 L 59 59 1 1 W
|
||||
X 1A7 9 1600 -1000 300 L 59 59 1 1 B
|
||||
X 1A8 10 1600 -1100 300 L 59 59 1 1 B
|
||||
X 1A9 11 1600 -1200 300 L 59 59 1 1 B
|
||||
X 1A10 12 1600 -1300 300 L 59 59 1 1 B
|
||||
X 1A11 13 1600 -1400 300 L 59 59 1 1 B
|
||||
X 1A12 14 1600 -1500 300 L 59 59 1 1 B
|
||||
X 2A1 15 1600 -1700 300 L 59 59 1 1 W
|
||||
X 2A2 16 1600 -1800 300 L 59 59 1 1 B
|
||||
X VCC 17 0 -3100 300 R 59 59 1 1 W
|
||||
X 2A3 18 1600 -1900 300 L 59 59 1 1 B
|
||||
X GND 19 1600 -3100 300 L 59 59 1 1 W
|
||||
X 2A4 20 1600 -2000 300 L 59 59 1 1 B
|
||||
X 2A5 21 1600 -2100 300 L 59 59 1 1 B
|
||||
X 2A6 22 1600 -2200 300 L 59 59 1 1 B
|
||||
X 2A7 23 1600 -2300 300 L 59 59 1 1 B
|
||||
X 2A8 24 1600 -2400 300 L 59 59 1 1 B
|
||||
X 2A9 25 1600 -2500 300 L 59 59 1 1 B
|
||||
X 2A10 26 1600 -2600 300 L 59 59 1 1 B
|
||||
X 2A11 27 1600 -2700 300 L 59 59 1 1 B
|
||||
X 2A12 28 1600 -2800 300 L 59 59 1 1 B
|
||||
X 2B12 29 0 -2800 300 R 59 59 1 1 B
|
||||
X 2B11 30 0 -2700 300 R 59 59 1 1 B
|
||||
X 2B10 31 0 -2600 300 R 59 59 1 1 B
|
||||
X 2B9 32 0 -2500 300 R 59 59 1 1 B
|
||||
X 2B8 33 0 -2400 300 R 59 59 1 1 B
|
||||
X 2B7 34 0 -2300 300 R 59 59 1 1 B
|
||||
X 2B6 35 0 -2200 300 R 59 59 1 1 B
|
||||
X 2B5 36 0 -2100 300 R 59 59 1 1 B
|
||||
X 2B4 37 0 -2000 300 R 59 59 1 1 B
|
||||
X GND 38 1600 -3200 300 L 59 59 1 1 W
|
||||
X 2B3 39 0 -1900 300 R 59 59 1 1 B
|
||||
X 2B2 40 0 -1800 300 R 59 59 1 1 B
|
||||
X 2B1 41 0 -1700 300 R 59 59 1 1 B
|
||||
X 1B12 42 0 -1500 300 R 59 59 1 1 B
|
||||
X 1B11 43 0 -1400 300 R 59 59 1 1 B
|
||||
X 1B10 44 0 -1300 300 R 59 59 1 1 B
|
||||
X 1B9 45 0 -1200 300 R 59 59 1 1 B
|
||||
X 1B8 46 0 -1100 300 R 59 59 1 1 B
|
||||
X 1B7 47 0 -1000 300 R 59 59 1 1 B
|
||||
X 1B6 48 0 -900 300 R 59 59 1 1 B
|
||||
X GND 49 1600 -3300 300 L 59 59 1 1 W
|
||||
X 1B5 50 0 -800 300 R 59 59 1 1 B
|
||||
X 1B4 51 0 -700 300 R 59 59 1 1 B
|
||||
X 1B3 52 0 -600 300 R 59 59 1 1 B
|
||||
X 1B2 53 0 -500 300 R 59 59 1 1 B
|
||||
X 1B1 54 0 -400 300 R 59 59 1 1 B
|
||||
X *2OE 55 0 -100 300 R 59 59 1 1 I
|
||||
X *1OE 56 0 0 300 R 59 59 1 1 I
|
||||
|
||||
P 2 1 1 5 300 200 300 -3400 N
|
||||
P 2 1 1 5 300 -3400 1300 -3400 N
|
||||
P 2 1 1 5 1300 -3400 1300 200 N
|
||||
P 2 1 1 5 1300 200 300 200 N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
|
||||
|
||||
#
|
||||
#End Library
|
38
nubus-to-ztex/NuBus/ul_SN74CB3T3125PW.lib
Normal file
38
nubus-to-ztex/NuBus/ul_SN74CB3T3125PW.lib
Normal file
|
@ -0,0 +1,38 @@
|
|||
EESchema-LIBRARY Version 2.3 Date: 21-02-2013 11:13:20
|
||||
#encoding utf-8
|
||||
#
|
||||
# SN74CB3T3125PW
|
||||
#
|
||||
DEF SN74CB3T3125PW U 0 10 Y Y 1 L N
|
||||
F0 "U" 800 400 60 H V C CNN
|
||||
F1 "SN74CB3T3125PW" 800 300 60 H V C CNN
|
||||
F2 "PW14" 800 240 60 H I C CNN
|
||||
F3 "~" 0 0 60 H V C CNN
|
||||
$FPLIST
|
||||
PW14
|
||||
PW14-M
|
||||
PW14-L
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
X *1OE 1 0 0 300 R 59 59 1 1 I
|
||||
X 1A 2 0 -500 300 R 59 59 1 1 I
|
||||
X 1B 3 1600 -500 300 L 59 59 1 1 I
|
||||
X *2OE 4 0 -100 300 R 59 59 1 1 I
|
||||
X 2A 5 0 -600 300 R 59 59 1 1 I
|
||||
X 2B 6 1600 -600 300 L 59 59 1 1 I
|
||||
X GND 7 1600 -300 300 L 59 59 1 1 W
|
||||
X 3B 8 1600 -700 300 L 59 59 1 1 I
|
||||
X 3A 9 0 -700 300 R 59 59 1 1 I
|
||||
X *3OE 10 0 -200 300 R 59 59 1 1 I
|
||||
X 4B 11 1600 -800 300 L 59 59 1 1 I
|
||||
X 4A 12 0 -800 300 R 59 59 1 1 I
|
||||
X *4OE 13 0 -300 300 R 59 59 1 1 I
|
||||
X VCC 14 0 -1500 300 R 59 59 1 1 W
|
||||
P 2 1 1 5 300 200 300 -1700 N
|
||||
P 2 1 1 5 300 -1700 1300 -1700 N
|
||||
P 2 1 1 5 1300 -1700 1300 200 N
|
||||
P 2 1 1 5 1300 200 300 200 N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
46
nubus-to-ztex/TPD12S016PWR.lib
Normal file
46
nubus-to-ztex/TPD12S016PWR.lib
Normal file
|
@ -0,0 +1,46 @@
|
|||
EESchema-LIBRARY Version 2.3
|
||||
#encoding utf-8
|
||||
#(c) SnapEDA 2016 (snapeda.com)
|
||||
#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
|
||||
#
|
||||
# TPD12S016PWR
|
||||
#
|
||||
DEF TPD12S016PWR U 0 40 Y Y 1 L N
|
||||
F0 "U" -500 1239 50 H V L BNN
|
||||
F1 "TPD12S016PWR" -500 -1300 50 H V L BNN
|
||||
F2 "SOP65P640X120-24N" 0 0 50 H I L BNN
|
||||
F3 "" 0 0 50 H I L BNN
|
||||
F4 "1.2 mm" 0 0 50 H I L BNN "MAXIMUM_PACKAGE_HEIGHT"
|
||||
F5 "Texas Instruments" 0 0 50 H I L BNN "MANUFACTURER"
|
||||
F6 "F" 0 0 50 H I L BNN "PARTREV"
|
||||
F7 "IPC 7351B" 0 0 50 H I L BNN "STANDARD"
|
||||
DRAW
|
||||
S -500 -1200 500 1200 0 0 10 f
|
||||
X CLK- 15 700 500 200 L 40 40 0 0 B C
|
||||
X CLK+ 16 700 600 200 L 40 40 0 0 B C
|
||||
X CEC_A 1 -700 -400 200 R 40 40 0 0 B
|
||||
X CEC_B 7 700 -400 200 L 40 40 0 0 B
|
||||
X CT_HPD 12 -700 600 200 R 40 40 0 0 I
|
||||
X HPD_A 4 -700 -300 200 R 40 40 0 0 O
|
||||
X HPD_B 10 700 -300 200 L 40 40 0 0 I
|
||||
X LS_OE 5 -700 400 200 R 40 40 0 0 I
|
||||
X SCL_A 2 -700 -500 200 R 40 40 0 0 B
|
||||
X SCL_B 8 700 -500 200 L 40 40 0 0 B
|
||||
X SDA_A 3 -700 -600 200 R 40 40 0 0 B
|
||||
X SDA_B 9 700 -600 200 L 40 40 0 0 B
|
||||
X VCC5V 11 -700 800 200 R 40 40 0 0 I
|
||||
X VCCA 24 -700 1100 200 R 40 40 0 0 W
|
||||
X 5V_OUT 13 700 800 200 L 40 40 0 0 O
|
||||
X GND_6 6 700 -900 200 L 40 40 0 0 W
|
||||
X D1+ 21 700 200 200 L 40 40 0 0 B
|
||||
X D1- 20 700 100 200 L 40 40 0 0 B
|
||||
X GND_14 14 700 -1000 200 L 40 40 0 0 W
|
||||
X GND_19 19 700 -1100 200 L 40 40 0 0 W
|
||||
X D2+ 23 700 0 200 L 40 40 0 0 B
|
||||
X D2- 22 700 -100 200 L 40 40 0 0 B
|
||||
X D0+ 18 700 400 200 L 40 40 0 0 B
|
||||
X D0- 17 700 300 200 L 40 40 0 0 B
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# End Library
|
149
nubus-to-ztex/XilinxJtag.pretty/XilinxJtag.kicad_mod
Normal file
149
nubus-to-ztex/XilinxJtag.pretty/XilinxJtag.kicad_mod
Normal file
|
@ -0,0 +1,149 @@
|
|||
(module XilinxJtag (layer F.Cu) (tedit 59FED667)
|
||||
(descr "Through hole angled pin header, 2x07, 2.00mm pitch, 4.2mm pin length, double rows")
|
||||
(tags "Through hole angled pin header THT 2x07 2.00mm double row")
|
||||
(fp_text reference REF** (at 4.1 -2) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value PinHeader_2x07_P2.00mm_Horizontal (at 4.1 14) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start 3.875 -1) (end 5 -1) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 -1) (end 5 13) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 13) (end 3.5 13) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 3.5 13) (end 3.5 -0.625) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 3.5 -0.625) (end 3.875 -1) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 -0.25) (end 3.5 -0.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 -0.25) (end -0.25 0.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 0.25) (end 3.5 0.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 -0.25) (end 9.2 -0.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 9.2 -0.25) (end 9.2 0.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 0.25) (end 9.2 0.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 1.75) (end 3.5 1.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 1.75) (end -0.25 2.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 2.25) (end 3.5 2.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 1.75) (end 9.2 1.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 9.2 1.75) (end 9.2 2.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 2.25) (end 9.2 2.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 3.75) (end 3.5 3.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 3.75) (end -0.25 4.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 4.25) (end 3.5 4.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 3.75) (end 9.2 3.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 9.2 3.75) (end 9.2 4.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 4.25) (end 9.2 4.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 5.75) (end 3.5 5.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 5.75) (end -0.25 6.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 6.25) (end 3.5 6.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 5.75) (end 9.2 5.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 9.2 5.75) (end 9.2 6.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 6.25) (end 9.2 6.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 7.75) (end 3.5 7.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 7.75) (end -0.25 8.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 8.25) (end 3.5 8.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 7.75) (end 9.2 7.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 9.2 7.75) (end 9.2 8.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 8.25) (end 9.2 8.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 9.75) (end 3.5 9.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 9.75) (end -0.25 10.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 10.25) (end 3.5 10.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 9.75) (end 9.2 9.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 9.2 9.75) (end 9.2 10.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 10.25) (end 9.2 10.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 11.75) (end 3.5 11.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 11.75) (end -0.25 12.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.25 12.25) (end 3.5 12.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 11.75) (end 9.2 11.75) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 9.2 11.75) (end 9.2 12.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 5 12.25) (end 9.2 12.25) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 3.44 -1.06) (end 3.44 13.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 3.44 13.06) (end 5.06 13.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 13.06) (end 5.06 -1.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 -1.06) (end 3.44 -1.06) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 -0.31) (end 9.26 -0.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 -0.31) (end 9.26 0.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 0.31) (end 5.06 0.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 -0.25) (end 9.26 -0.25) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 -0.13) (end 9.26 -0.13) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 -0.01) (end 9.26 -0.01) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 0.11) (end 9.26 0.11) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 0.23) (end 9.26 0.23) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.882114 -0.31) (end 3.44 -0.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.882114 0.31) (end 3.44 0.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0.935 -0.31) (end 1.117886 -0.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0.935 0.31) (end 1.117886 0.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 3.44 1) (end 5.06 1) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 1.69) (end 9.26 1.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 1.69) (end 9.26 2.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 2.31) (end 5.06 2.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.882114 1.69) (end 3.44 1.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.882114 2.31) (end 3.44 2.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0.882114 1.69) (end 1.117886 1.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0.882114 2.31) (end 1.117886 2.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 3.44 3) (end 5.06 3) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 3.69) (end 9.26 3.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 3.69) (end 9.26 4.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 4.31) (end 5.06 4.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.882114 3.69) (end 3.44 3.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.882114 4.31) (end 3.44 4.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0.882114 3.69) (end 1.117886 3.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0.882114 4.31) (end 1.117886 4.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 3.44 5) (end 5.06 5) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 5.69) (end 9.26 5.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 5.69) (end 9.26 6.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 6.31) (end 5.06 6.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.882114 5.69) (end 3.44 5.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.882114 6.31) (end 3.44 6.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0.882114 5.69) (end 1.117886 5.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0.882114 6.31) (end 1.117886 6.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 3.44 7) (end 5.06 7) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 7.69) (end 9.26 7.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 7.69) (end 9.26 8.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 8.31) (end 5.06 8.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.882114 7.69) (end 3.44 7.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.882114 8.31) (end 3.44 8.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0.882114 7.69) (end 1.117886 7.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0.882114 8.31) (end 1.117886 8.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 3.44 9) (end 5.06 9) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 9.69) (end 9.26 9.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 9.69) (end 9.26 10.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 10.31) (end 5.06 10.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.882114 9.69) (end 3.44 9.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.882114 10.31) (end 3.44 10.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0.882114 9.69) (end 1.117886 9.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0.882114 10.31) (end 1.117886 10.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 3.44 11) (end 5.06 11) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 5.06 11.69) (end 9.26 11.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 11.69) (end 9.26 12.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 9.26 12.31) (end 5.06 12.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.882114 11.69) (end 3.44 11.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 2.882114 12.31) (end 3.44 12.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0.882114 11.69) (end 1.117886 11.69) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 0.882114 12.31) (end 1.117886 12.31) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1 0) (end -1 -1) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1 -1) (end 0 -1) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.5 -1.5) (end -1.5 13.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.5 13.5) (end 9.7 13.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 9.7 13.5) (end 9.7 -1.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 9.7 -1.5) (end -1.5 -1.5) (layer F.CrtYd) (width 0.05))
|
||||
(pad 1 thru_hole rect (at 0 0) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 2 thru_hole oval (at 2 0) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 3 thru_hole oval (at 0 2) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 4 thru_hole oval (at 2 2) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 5 thru_hole oval (at 0 4) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 6 thru_hole oval (at 2 4) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 7 thru_hole oval (at 0 6) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 8 thru_hole oval (at 2 6) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 9 thru_hole oval (at 0 8) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 10 thru_hole oval (at 2 8) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 11 thru_hole oval (at 0 10) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 12 thru_hole oval (at 2 10) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 13 thru_hole oval (at 0 12) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(pad 14 thru_hole oval (at 2 12) (size 1.35 1.35) (drill 0.9) (layers *.Cu *.Mask))
|
||||
(fp_text user %R (at 4.25 6 90) (layer F.Fab)
|
||||
(effects (font (size 0.9 0.9) (thickness 0.135)))
|
||||
)
|
||||
(model ${KISYS3DMOD}/Connector_PinHeader_2.00mm.3dshapes/PinHeader_2x07_P2.00mm_Horizontal.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
22
nubus-to-ztex/ad1580.lib
Normal file
22
nubus-to-ztex/ad1580.lib
Normal file
|
@ -0,0 +1,22 @@
|
|||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# AD1580
|
||||
#
|
||||
DEF AD1580 U 0 40 Y Y 1 F N
|
||||
F0 "U" 0 200 50 H V C CNN
|
||||
F1 "AD1580" 0 100 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
SOT-23-3
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -150 50 150 -250 0 1 0 N
|
||||
X V+ 1 -250 0 100 R 50 50 1 1 I
|
||||
X V- 2 -250 -200 100 R 50 50 1 1 O
|
||||
X NC 3 250 -100 100 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
236
nubus-to-ztex/fan.sch
Normal file
236
nubus-to-ztex/fan.sch
Normal file
|
@ -0,0 +1,236 @@
|
|||
EESchema Schematic File Version 4
|
||||
LIBS:nubus-to-ztex-cache
|
||||
EELAYER 26 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 7 7
|
||||
Title "sbus-to-ztex blinkey stuff"
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L Connector:Conn_01x03_Male J7
|
||||
U 1 1 60E1E49E
|
||||
P 4400 4750
|
||||
F 0 "J7" H 4506 5028 50 0000 C CNN
|
||||
F 1 "Conn_01x03_Male" H 4506 4937 50 0000 C CNN
|
||||
F 2 "Connector_Molex:Molex_KK-254_AE-6410-03A_1x03_P2.54mm_Vertical" H 4400 4750 50 0001 C CNN
|
||||
F 3 "~" H 4400 4750 50 0001 C CNN
|
||||
F 4 "22-27-2031" H 4400 4750 50 0001 C CNN "MPN-ALT"
|
||||
F 5 "Molex" H 4400 4750 50 0001 C CNN "Manufacturer-ALT"
|
||||
F 6 "https://www.mouser.fr/ProductDetail/Molex/22-27-2031?qs=%2Fha2pyFadugXOaGYK9vaczm7nZ04txhJn3OGcnGWT3U=" H 4400 4750 50 0001 C CNN "URL-ALT"
|
||||
F 7 "640456-3" H 4400 4750 50 0001 C CNN "MPN"
|
||||
F 8 "TE Connectivity" H 4400 4750 50 0001 C CNN "Manufacturer"
|
||||
F 9 "https://www.lcsc.com/product-detail/Wire-To-Board-Wire-To-Wire-Connector_TE-Connectivity-640456-3_C86503.html" H 4400 4750 50 0001 C CNN "URL"
|
||||
1 4400 4750
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0187
|
||||
U 1 1 60E1EC2C
|
||||
P 4600 4650
|
||||
F 0 "#PWR0187" H 4600 4400 50 0001 C CNN
|
||||
F 1 "GND" V 4605 4522 50 0000 R CNN
|
||||
F 2 "" H 4600 4650 50 0001 C CNN
|
||||
F 3 "" H 4600 4650 50 0001 C CNN
|
||||
1 4600 4650
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+5V #PWR0188
|
||||
U 1 1 60E1ED6C
|
||||
P 4600 4750
|
||||
F 0 "#PWR0188" H 4600 4600 50 0001 C CNN
|
||||
F 1 "+5V" V 4615 4878 50 0000 L CNN
|
||||
F 2 "" H 4600 4750 50 0001 C CNN
|
||||
F 3 "" H 4600 4750 50 0001 C CNN
|
||||
1 4600 4750
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0189
|
||||
U 1 1 60E1FA97
|
||||
P 4600 4850
|
||||
F 0 "#PWR0189" H 4600 4600 50 0001 C CNN
|
||||
F 1 "GND" V 4605 4722 50 0000 R CNN
|
||||
F 2 "" H 4600 4850 50 0001 C CNN
|
||||
F 3 "" H 4600 4850 50 0001 C CNN
|
||||
1 4600 4850
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 60E24715
|
||||
P 5150 4800
|
||||
AR Path="/5F69F4EF/60E24715" Ref="C?" Part="1"
|
||||
AR Path="/5F6B165A/60E24715" Ref="C6" Part="1"
|
||||
AR Path="/61B99D2C/60E24715" Ref="C20" Part="1"
|
||||
F 0 "C20" H 5175 4900 50 0000 L CNN
|
||||
F 1 "47uF 10V+" H 5175 4700 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0805_2012Metric" H 5188 4650 50 0001 C CNN
|
||||
F 3 "" H 5150 4800 50 0000 C CNN
|
||||
F 4 "C2012X5R1A476MTJ00E" H 5150 4800 50 0001 C CNN "MPN"
|
||||
F 5 "https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_TDK-C2012X5R1A476MTJ00E_C76636.html" H 5150 4800 50 0001 C CNN "URL"
|
||||
1 5150 4800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4600 4750 5150 4750
|
||||
Wire Wire Line
|
||||
5150 4750 5150 4650
|
||||
Connection ~ 4600 4750
|
||||
Wire Wire Line
|
||||
4600 4850 5150 4850
|
||||
Wire Wire Line
|
||||
5150 4850 5150 4950
|
||||
Connection ~ 4600 4850
|
||||
$Comp
|
||||
L Connector_Generic:Conn_01x02 J9
|
||||
U 1 1 61BEF34E
|
||||
P 6800 4300
|
||||
F 0 "J9" H 6880 4292 50 0000 L CNN
|
||||
F 1 "Conn_01x02" H 6880 4201 50 0000 L CNN
|
||||
F 2 "For_SeeedStudio:PinSocket_1x02_P2.54mm_Vertical_for_SeeedStudio" H 6800 4300 50 0001 C CNN
|
||||
F 3 "~" H 6800 4300 50 0001 C CNN
|
||||
F 4 "PM254V-11-02-H85" H 6800 4300 50 0001 C CNN "MPN"
|
||||
F 5 "https://www.lcsc.com/product-detail/Pin-Header-Female-Header_XFCN-PM254V-11-02-H85_C541849.html" H 6800 4300 50 0001 C CNN "URL"
|
||||
1 6800 4300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+3V3 #PWR0102
|
||||
U 1 1 61BEF445
|
||||
P 6600 4300
|
||||
F 0 "#PWR0102" H 6600 4150 50 0001 C CNN
|
||||
F 1 "+3V3" V 6615 4428 50 0000 L CNN
|
||||
F 2 "" H 6600 4300 50 0001 C CNN
|
||||
F 3 "" H 6600 4300 50 0001 C CNN
|
||||
1 6600 4300
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0200
|
||||
U 1 1 61BEF4B8
|
||||
P 6600 4400
|
||||
F 0 "#PWR0200" H 6600 4150 50 0001 C CNN
|
||||
F 1 "GND" V 6605 4272 50 0000 R CNN
|
||||
F 2 "" H 6600 4400 50 0001 C CNN
|
||||
F 3 "" H 6600 4400 50 0001 C CNN
|
||||
1 6600 4400
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 61C19258
|
||||
P 6200 4350
|
||||
AR Path="/5F69F4EF/61C19258" Ref="C?" Part="1"
|
||||
AR Path="/5F6B165A/61C19258" Ref="C?" Part="1"
|
||||
AR Path="/61B99D2C/61C19258" Ref="C31" Part="1"
|
||||
F 0 "C31" H 6225 4450 50 0000 L CNN
|
||||
F 1 "47uF 10V+" H 6225 4250 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0805_2012Metric" H 6238 4200 50 0001 C CNN
|
||||
F 3 "" H 6200 4350 50 0000 C CNN
|
||||
F 4 "C2012X5R1A476MTJ00E" H 6200 4350 50 0001 C CNN "MPN"
|
||||
F 5 "https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_TDK-C2012X5R1A476MTJ00E_C76636.html" H 6200 4350 50 0001 C CNN "URL"
|
||||
1 6200 4350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
6200 4200 6600 4200
|
||||
Wire Wire Line
|
||||
6600 4200 6600 4300
|
||||
Connection ~ 6600 4300
|
||||
Wire Wire Line
|
||||
6600 4400 6600 4500
|
||||
Wire Wire Line
|
||||
6600 4500 6200 4500
|
||||
Connection ~ 6600 4400
|
||||
$Comp
|
||||
L Connector:Conn_01x03_Male J10
|
||||
U 1 1 61C52A59
|
||||
P 4400 5800
|
||||
F 0 "J10" H 4506 6078 50 0000 C CNN
|
||||
F 1 "Conn_01x03_Male" H 4506 5987 50 0000 C CNN
|
||||
F 2 "Connector_Molex:Molex_KK-254_AE-6410-03A_1x03_P2.54mm_Vertical" H 4400 5800 50 0001 C CNN
|
||||
F 3 "~" H 4400 5800 50 0001 C CNN
|
||||
F 4 "22-27-2031" H 4400 5800 50 0001 C CNN "MPN-ALT"
|
||||
F 5 "Molex" H 4400 5800 50 0001 C CNN "Manufacturer-ALT"
|
||||
F 6 "https://www.mouser.fr/ProductDetail/Molex/22-27-2031?qs=%2Fha2pyFadugXOaGYK9vaczm7nZ04txhJn3OGcnGWT3U=" H 4400 5800 50 0001 C CNN "URL-ALT"
|
||||
F 7 "640456-3" H 4400 5800 50 0001 C CNN "MPN"
|
||||
F 8 "TE Connectivity" H 4400 5800 50 0001 C CNN "Manufacturer"
|
||||
F 9 "https://www.lcsc.com/product-detail/Wire-To-Board-Wire-To-Wire-Connector_TE-Connectivity-640456-3_C86503.html" H 4400 5800 50 0001 C CNN "URL"
|
||||
1 4400 5800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0208
|
||||
U 1 1 61C52A60
|
||||
P 4600 5700
|
||||
F 0 "#PWR0208" H 4600 5450 50 0001 C CNN
|
||||
F 1 "GND" V 4605 5572 50 0000 R CNN
|
||||
F 2 "" H 4600 5700 50 0001 C CNN
|
||||
F 3 "" H 4600 5700 50 0001 C CNN
|
||||
1 4600 5700
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0209
|
||||
U 1 1 61C52A6C
|
||||
P 4600 5900
|
||||
F 0 "#PWR0209" H 4600 5650 50 0001 C CNN
|
||||
F 1 "GND" V 4605 5772 50 0000 R CNN
|
||||
F 2 "" H 4600 5900 50 0001 C CNN
|
||||
F 3 "" H 4600 5900 50 0001 C CNN
|
||||
1 4600 5900
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 61C52A73
|
||||
P 5150 5850
|
||||
AR Path="/5F69F4EF/61C52A73" Ref="C?" Part="1"
|
||||
AR Path="/5F6B165A/61C52A73" Ref="C?" Part="1"
|
||||
AR Path="/61B99D2C/61C52A73" Ref="C33" Part="1"
|
||||
F 0 "C33" H 5175 5950 50 0000 L CNN
|
||||
F 1 "10uF" H 5175 5750 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0805_2012Metric" H 5188 5700 50 0001 C CNN
|
||||
F 3 "" H 5150 5850 50 0000 C CNN
|
||||
F 4 "GRM21BR61E106MA73L" H 5150 5850 50 0001 C CNN "MPN"
|
||||
F 5 "https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_Murata-Electronics-GRM21BR61E106MA73L_C391262.html" H 5150 5850 50 0001 C CNN "URL"
|
||||
1 5150 5850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4600 5800 5150 5800
|
||||
Wire Wire Line
|
||||
5150 5800 5150 5700
|
||||
Wire Wire Line
|
||||
4600 5900 5150 5900
|
||||
Wire Wire Line
|
||||
5150 5900 5150 6000
|
||||
Connection ~ 4600 5900
|
||||
$Comp
|
||||
L power:+12V #PWR0210
|
||||
U 1 1 61C52B88
|
||||
P 4600 5800
|
||||
F 0 "#PWR0210" H 4600 5650 50 0001 C CNN
|
||||
F 1 "+12V" V 4615 5928 50 0000 L CNN
|
||||
F 2 "" H 4600 5800 50 0001 C CNN
|
||||
F 3 "" H 4600 5800 50 0001 C CNN
|
||||
1 4600 5800
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
Connection ~ 4600 5800
|
||||
Text Notes 3950 4750 0 50 ~ 0
|
||||
5V Fan
|
||||
Text Notes 4000 5850 0 50 ~ 0
|
||||
12V Fan
|
||||
Text Notes 6800 4600 0 50 ~ 0
|
||||
3.3V access
|
||||
$EndSCHEMATC
|
7
nubus-to-ztex/fp-lib-table
Normal file
7
nubus-to-ztex/fp-lib-table
Normal file
|
@ -0,0 +1,7 @@
|
|||
(fp_lib_table
|
||||
(lib (name 74CB3T16211)(type KiCad)(uri ${KIPRJMOD}/74CB3T16211.pretty)(options "")(descr ""))
|
||||
(lib (name For_SeeedStudio)(type KiCad)(uri ${KIPRJMOD}/For_SeeedStudio.pretty)(options "")(descr ""))
|
||||
(lib (name Molex2x32)(type KiCad)(uri ${KIPRJMOD}/Molex2x32.pretty)(options "")(descr ""))
|
||||
(lib (name XilinxJtag)(type KiCad)(uri ${KIPRJMOD}/XilinxJtag.pretty)(options "")(descr ""))
|
||||
(lib (name MOLEX_47219-2001)(type KiCad)(uri ${KIPRJMOD}/NuBus/MOLEX_47219-2001.pretty)(options "")(descr ""))
|
||||
)
|
251
nubus-to-ztex/gui_defaults.par
Normal file
251
nubus-to-ztex/gui_defaults.par
Normal file
|
@ -0,0 +1,251 @@
|
|||
|
||||
(gui_defaults
|
||||
(windows
|
||||
(board_frame
|
||||
visible
|
||||
(bounds
|
||||
120 0 1158 919
|
||||
)
|
||||
)
|
||||
(color_manager
|
||||
not_visible
|
||||
(bounds
|
||||
0 600 1118 171
|
||||
)
|
||||
)
|
||||
(layer_visibility
|
||||
not_visible
|
||||
(bounds
|
||||
0 450 365 217
|
||||
)
|
||||
)
|
||||
(object_visibility
|
||||
not_visible
|
||||
(bounds
|
||||
0 550 408 399
|
||||
)
|
||||
)
|
||||
(display_miscellanious
|
||||
not_visible
|
||||
(bounds
|
||||
0 350 244 336
|
||||
)
|
||||
)
|
||||
(snapshots
|
||||
not_visible
|
||||
(bounds
|
||||
0 250 235 258
|
||||
)
|
||||
)
|
||||
(select_parameter
|
||||
not_visible
|
||||
(bounds
|
||||
0 0 244 520
|
||||
)
|
||||
)
|
||||
(route_parameter
|
||||
not_visible
|
||||
(bounds
|
||||
0 100 263 545
|
||||
)
|
||||
)
|
||||
(manual_rules
|
||||
not_visible
|
||||
(bounds
|
||||
0 0 325 199
|
||||
)
|
||||
)
|
||||
(route_details
|
||||
not_visible
|
||||
(bounds
|
||||
0 0 270 243
|
||||
)
|
||||
)
|
||||
(move_parameter
|
||||
not_visible
|
||||
(bounds
|
||||
0 50 311 142
|
||||
)
|
||||
)
|
||||
(clearance_matrix
|
||||
not_visible
|
||||
(bounds
|
||||
0 150 568 276
|
||||
)
|
||||
)
|
||||
(via_rules
|
||||
not_visible
|
||||
(bounds
|
||||
50 150 333 453
|
||||
)
|
||||
)
|
||||
(edit_vias
|
||||
not_visible
|
||||
(bounds
|
||||
100 150 411 122
|
||||
)
|
||||
)
|
||||
(edit_net_rules
|
||||
not_visible
|
||||
(bounds
|
||||
100 200 911 122
|
||||
)
|
||||
)
|
||||
(assign_net_rules
|
||||
not_visible
|
||||
(bounds
|
||||
100 250 226 375
|
||||
)
|
||||
)
|
||||
(padstack_info
|
||||
not_visible
|
||||
(bounds
|
||||
100 30 0 0
|
||||
)
|
||||
)
|
||||
(package_info
|
||||
not_visible
|
||||
(bounds
|
||||
200 30 0 0
|
||||
)
|
||||
)
|
||||
(component_info
|
||||
not_visible
|
||||
(bounds
|
||||
300 30 0 0
|
||||
)
|
||||
)
|
||||
(net_info
|
||||
not_visible
|
||||
(bounds
|
||||
350 30 0 0
|
||||
)
|
||||
)
|
||||
(incompletes_info
|
||||
not_visible
|
||||
(bounds
|
||||
400 30 0 0
|
||||
)
|
||||
)
|
||||
(violations_info
|
||||
not_visible
|
||||
(bounds
|
||||
500 30 0 0
|
||||
)
|
||||
)
|
||||
)
|
||||
(colors
|
||||
(background
|
||||
0 0 0
|
||||
)
|
||||
(hilight 0.8
|
||||
230 255 255
|
||||
)
|
||||
(incompletes 1.0
|
||||
255 255 255
|
||||
)
|
||||
(outline
|
||||
100 150 255
|
||||
)
|
||||
(component_front
|
||||
0 0 255
|
||||
)
|
||||
(component_back
|
||||
255 0 0
|
||||
)
|
||||
(violations
|
||||
255 0 255
|
||||
)
|
||||
(length_matching 0.1
|
||||
0 255 0
|
||||
)
|
||||
(traces 0.4
|
||||
255 0 0
|
||||
0 255 0
|
||||
255 255 0
|
||||
0 0 255
|
||||
)
|
||||
(fixed_traces 0.4
|
||||
255 0 0
|
||||
0 255 0
|
||||
255 255 0
|
||||
0 0 255
|
||||
)
|
||||
(vias 0.6
|
||||
200 200 0
|
||||
200 200 0
|
||||
200 200 0
|
||||
200 200 0
|
||||
)
|
||||
(fixed_vias 0.6
|
||||
200 200 0
|
||||
200 200 0
|
||||
200 200 0
|
||||
200 200 0
|
||||
)
|
||||
(pins 0.6
|
||||
150 50 0
|
||||
255 150 0
|
||||
255 150 0
|
||||
160 80 0
|
||||
)
|
||||
(conduction 0.2
|
||||
0 150 0
|
||||
0 200 60
|
||||
0 200 60
|
||||
100 100 0
|
||||
)
|
||||
(keepout 0.2
|
||||
0 110 110
|
||||
0 200 200
|
||||
0 200 200
|
||||
0 100 160
|
||||
)
|
||||
(via_keepout 0.2
|
||||
100 100 100
|
||||
100 100 100
|
||||
100 100 100
|
||||
100 100 100
|
||||
)
|
||||
)
|
||||
(parameter
|
||||
(selection_layers
|
||||
all_visible
|
||||
)
|
||||
(selectable_items
|
||||
TRACES VIAS PINS FIXED UNFIXED
|
||||
)
|
||||
(via_snap_to_smd_center
|
||||
on
|
||||
)
|
||||
(route_mode
|
||||
dynamic
|
||||
)
|
||||
(shove_enabled
|
||||
on
|
||||
)
|
||||
(drag_components_enabled
|
||||
on
|
||||
)
|
||||
(hilight_routing_obstacle
|
||||
off
|
||||
)
|
||||
(pull_tight_region
|
||||
2147483647
|
||||
)
|
||||
(pull_tight_accuracy
|
||||
500
|
||||
)
|
||||
(clearance_compensation
|
||||
off
|
||||
)
|
||||
(ignore_conduction_areas
|
||||
on
|
||||
)
|
||||
(automatic_layer_dimming
|
||||
0.7
|
||||
)
|
||||
(deselected_snapshot_attributes
|
||||
)
|
||||
)
|
||||
)
|
359
nubus-to-ztex/hdmi.sch
Normal file
359
nubus-to-ztex/hdmi.sch
Normal file
|
@ -0,0 +1,359 @@
|
|||
EESchema Schematic File Version 4
|
||||
LIBS:nubus-to-ztex-cache
|
||||
EELAYER 26 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 5 7
|
||||
Title "sbus-to-ztex blinkey stuff"
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L TPD12S016PWR:TPD12S016PWR U5
|
||||
U 1 1 6148D344
|
||||
P 3300 2700
|
||||
F 0 "U5" H 3300 4067 50 0000 C CNN
|
||||
F 1 "TPD12S016PWR" H 3300 3976 50 0000 C CNN
|
||||
F 2 "For_SeeedStudio:SOP65P640X120-24N" H 3300 2700 50 0001 L BNN
|
||||
F 3 "" H 3300 2700 50 0001 L BNN
|
||||
F 4 "1.2 mm" H 3300 2700 50 0001 L BNN "MAXIMUM_PACKAGE_HEIGHT"
|
||||
F 5 "Texas Instruments" H 3300 2700 50 0001 L BNN "MANUFACTURER"
|
||||
F 6 "F" H 3300 2700 50 0001 L BNN "PARTREV"
|
||||
F 7 "IPC 7351B" H 3300 2700 50 0001 L BNN "STANDARD"
|
||||
F 8 "TPD12S016PWR" H 3300 2700 50 0001 C CNN "MPN"
|
||||
1 3300 2700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4000 3600 4000 3650
|
||||
Connection ~ 4000 3700
|
||||
Wire Wire Line
|
||||
4000 3700 4000 3800
|
||||
Connection ~ 4000 3800
|
||||
Wire Wire Line
|
||||
4000 3800 4000 3900
|
||||
$Comp
|
||||
L power:GND #PWR0111
|
||||
U 1 1 60DDF342
|
||||
P 4000 3900
|
||||
F 0 "#PWR0111" H 4000 3650 50 0001 C CNN
|
||||
F 1 "GND" H 4005 3727 50 0000 C CNN
|
||||
F 2 "" H 4000 3900 50 0001 C CNN
|
||||
F 3 "" H 4000 3900 50 0001 C CNN
|
||||
1 4000 3900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text GLabel 4000 2100 2 50 Input ~ 0
|
||||
HDMI_CLK+
|
||||
Text GLabel 6250 2350 0 50 Input ~ 0
|
||||
HDMI_CLK+
|
||||
Text GLabel 4000 2200 2 50 Input ~ 0
|
||||
HDMI_CLK-
|
||||
Text GLabel 6250 2450 0 50 Input ~ 0
|
||||
HDMI_CLK-
|
||||
Text GLabel 6250 2150 0 50 Input ~ 0
|
||||
HDMI_D0+
|
||||
Text GLabel 6250 2250 0 50 Input ~ 0
|
||||
HDMI_D0-
|
||||
Text GLabel 6250 1950 0 50 Input ~ 0
|
||||
HDMI_D1+
|
||||
Text GLabel 6250 2050 0 50 Input ~ 0
|
||||
HDMI_D1-
|
||||
Text GLabel 6250 1750 0 50 Input ~ 0
|
||||
HDMI_D2+
|
||||
Text GLabel 6250 1850 0 50 Input ~ 0
|
||||
HDMI_D2-
|
||||
Text GLabel 4000 2300 2 50 Input ~ 0
|
||||
HDMI_D0+
|
||||
Text GLabel 4000 2400 2 50 Input ~ 0
|
||||
HDMI_D0-
|
||||
Text GLabel 4000 2500 2 50 Input ~ 0
|
||||
HDMI_D1+
|
||||
Text GLabel 4000 2600 2 50 Input ~ 0
|
||||
HDMI_D1-
|
||||
Text GLabel 4000 2700 2 50 Input ~ 0
|
||||
HDMI_D2+
|
||||
Text GLabel 4000 2800 2 50 Input ~ 0
|
||||
HDMI_D2-
|
||||
Wire Wire Line
|
||||
6250 2850 5000 2850
|
||||
Wire Wire Line
|
||||
5000 2850 5000 3200
|
||||
Wire Wire Line
|
||||
5000 3200 4000 3200
|
||||
Wire Wire Line
|
||||
6250 2950 5100 2950
|
||||
Wire Wire Line
|
||||
5100 2950 5100 3300
|
||||
Wire Wire Line
|
||||
5100 3300 4000 3300
|
||||
Wire Wire Line
|
||||
6250 2650 4900 2650
|
||||
Wire Wire Line
|
||||
4900 2650 4900 3100
|
||||
Wire Wire Line
|
||||
4900 3100 4000 3100
|
||||
Wire Wire Line
|
||||
4000 3000 5700 3000
|
||||
Wire Wire Line
|
||||
5700 3000 5700 3250
|
||||
Wire Wire Line
|
||||
5700 3250 6250 3250
|
||||
Connection ~ 4000 3650
|
||||
Wire Wire Line
|
||||
4000 3650 4000 3700
|
||||
Text GLabel 6650 1450 0 50 Input ~ 0
|
||||
HDMI_5V
|
||||
Text GLabel 4000 1900 2 50 Input ~ 0
|
||||
HDMI_5V
|
||||
Text GLabel 4650 1050 2 50 Input ~ 0
|
||||
HDMI_5V
|
||||
Wire Wire Line
|
||||
4650 1050 4650 1150
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 6148D345
|
||||
P 4650 1300
|
||||
AR Path="/5F679B53/6148D345" Ref="C?" Part="1"
|
||||
AR Path="/5F6B165A/6148D345" Ref="C7" Part="1"
|
||||
AR Path="/612D28DD/6148D345" Ref="C18" Part="1"
|
||||
AR Path="/61B62C00/6148D345" Ref="C15" Part="1"
|
||||
F 0 "C15" H 4675 1400 50 0000 L CNN
|
||||
F 1 "100nF" H 4675 1200 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric" H 4688 1150 50 0001 C CNN
|
||||
F 3 "" H 4650 1300 50 0000 C CNN
|
||||
F 4 "www.yageo.com" H 4650 1300 50 0001 C CNN "MNF1_URL"
|
||||
F 5 "CC0603KRX7R8BB104" H 4650 1300 50 0001 C CNN "MPN"
|
||||
F 6 "603-CC603KRX7R8BB104" H 4650 1300 50 0001 C CNN "Mouser"
|
||||
F 7 "?" H 4650 1300 50 0001 C CNN "Digikey"
|
||||
F 8 "?" H 4650 1300 50 0001 C CNN "LCSC"
|
||||
F 9 "?" H 4650 1300 50 0001 C CNN "Koncar"
|
||||
F 10 "TB" H 4650 1300 50 0001 C CNN "Side"
|
||||
1 4650 1300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0112
|
||||
U 1 1 6148D346
|
||||
P 4650 1450
|
||||
F 0 "#PWR0112" H 4650 1200 50 0001 C CNN
|
||||
F 1 "GND" H 4655 1277 50 0000 C CNN
|
||||
F 2 "" H 4650 1450 50 0001 C CNN
|
||||
F 3 "" H 4650 1450 50 0001 C CNN
|
||||
1 4650 1450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+3V3 #PWR0113
|
||||
U 1 1 6148D347
|
||||
P 2600 1600
|
||||
F 0 "#PWR0113" H 2600 1450 50 0001 C CNN
|
||||
F 1 "+3V3" H 2615 1773 50 0000 C CNN
|
||||
F 2 "" H 2600 1600 50 0001 C CNN
|
||||
F 3 "" H 2600 1600 50 0001 C CNN
|
||||
1 2600 1600
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+5V #PWR0173
|
||||
U 1 1 6148D348
|
||||
P 2600 1900
|
||||
F 0 "#PWR0173" H 2600 1750 50 0001 C CNN
|
||||
F 1 "+5V" H 2615 2073 50 0000 C CNN
|
||||
F 2 "" H 2600 1900 50 0001 C CNN
|
||||
F 3 "" H 2600 1900 50 0001 C CNN
|
||||
1 2600 1900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2600 2300 2400 2300
|
||||
Wire Wire Line
|
||||
2400 2300 2400 2100
|
||||
Wire Wire Line
|
||||
2400 2100 2600 2100
|
||||
Wire Wire Line
|
||||
2600 1600 2400 1600
|
||||
Wire Wire Line
|
||||
2400 1600 2400 2100
|
||||
Connection ~ 2600 1600
|
||||
Connection ~ 2400 2100
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 6148D349
|
||||
P 2250 1600
|
||||
AR Path="/5F679B53/6148D349" Ref="C?" Part="1"
|
||||
AR Path="/5F6B165A/6148D349" Ref="C4" Part="1"
|
||||
AR Path="/612D28DD/6148D349" Ref="C16" Part="1"
|
||||
AR Path="/61B62C00/6148D349" Ref="C13" Part="1"
|
||||
F 0 "C13" H 2275 1700 50 0000 L CNN
|
||||
F 1 "100nF" H 2275 1500 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric" H 2288 1450 50 0001 C CNN
|
||||
F 3 "" H 2250 1600 50 0000 C CNN
|
||||
F 4 "www.yageo.com" H 2250 1600 50 0001 C CNN "MNF1_URL"
|
||||
F 5 "CC0603KRX7R8BB104" H 2250 1600 50 0001 C CNN "MPN"
|
||||
F 6 "603-CC603KRX7R8BB104" H 2250 1600 50 0001 C CNN "Mouser"
|
||||
F 7 "?" H 2250 1600 50 0001 C CNN "Digikey"
|
||||
F 8 "?" H 2250 1600 50 0001 C CNN "LCSC"
|
||||
F 9 "?" H 2250 1600 50 0001 C CNN "Koncar"
|
||||
F 10 "TB" H 2250 1600 50 0001 C CNN "Side"
|
||||
F 11 "https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_YAGEO-CC0603KRX7R8BB104_C92490.html" H 2250 1600 50 0001 C CNN "URL"
|
||||
1 2250 1600
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0174
|
||||
U 1 1 6148D34A
|
||||
P 2100 1600
|
||||
F 0 "#PWR0174" H 2100 1350 50 0001 C CNN
|
||||
F 1 "GND" V 2105 1472 50 0000 R CNN
|
||||
F 2 "" H 2100 1600 50 0001 C CNN
|
||||
F 3 "" H 2100 1600 50 0001 C CNN
|
||||
1 2100 1600
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 6148D34B
|
||||
P 2450 1900
|
||||
AR Path="/5F679B53/6148D34B" Ref="C?" Part="1"
|
||||
AR Path="/5F6B165A/6148D34B" Ref="C6" Part="1"
|
||||
AR Path="/612D28DD/6148D34B" Ref="C17" Part="1"
|
||||
AR Path="/61B62C00/6148D34B" Ref="C14" Part="1"
|
||||
F 0 "C14" H 2475 2000 50 0000 L CNN
|
||||
F 1 "100nF" H 2475 1800 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric" H 2488 1750 50 0001 C CNN
|
||||
F 3 "" H 2450 1900 50 0000 C CNN
|
||||
F 4 "www.yageo.com" H 2450 1900 50 0001 C CNN "MNF1_URL"
|
||||
F 5 "CC0603KRX7R8BB104" H 2450 1900 50 0001 C CNN "MPN"
|
||||
F 6 "603-CC603KRX7R8BB104" H 2450 1900 50 0001 C CNN "Mouser"
|
||||
F 7 "?" H 2450 1900 50 0001 C CNN "Digikey"
|
||||
F 8 "?" H 2450 1900 50 0001 C CNN "LCSC"
|
||||
F 9 "?" H 2450 1900 50 0001 C CNN "Koncar"
|
||||
F 10 "TB" H 2450 1900 50 0001 C CNN "Side"
|
||||
1 2450 1900
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
Connection ~ 2600 1900
|
||||
Wire Wire Line
|
||||
2300 1900 2100 1900
|
||||
Wire Wire Line
|
||||
2100 1900 2100 1600
|
||||
Text GLabel 2600 3000 0 50 Input ~ 0
|
||||
HDMI_HPD_A
|
||||
Text GLabel 2600 3100 0 50 Input ~ 0
|
||||
HDMI_CEC_A
|
||||
Text GLabel 2600 3200 0 50 Input ~ 0
|
||||
HDMI_SCL_A
|
||||
Text GLabel 2600 3300 0 50 Input ~ 0
|
||||
HDMI_SDA_A
|
||||
$Comp
|
||||
L Connector:HDMI_A J5
|
||||
U 1 1 6148D34C
|
||||
P 6650 2550
|
||||
F 0 "J5" H 7079 2596 50 0000 L CNN
|
||||
F 1 "HDMI_A" H 7079 2505 50 0000 L CNN
|
||||
F 2 "For_SeeedStudio:HDMI_A_Amphenol_10029449-111" H 6675 2550 50 0001 C CNN
|
||||
F 3 "https://en.wikipedia.org/wiki/HDMI" H 6675 2550 50 0001 C CNN
|
||||
F 4 "10029449-111" H 6650 2550 50 0001 C CNN "MPN"
|
||||
F 5 "https://www2.mouser.com/ProductDetail/Amphenol-FCI/10029449-111RLF?qs=fmpTyLOWOey0HPdD9%2F%2FaXA%3D%3D" H 6650 2550 50 0001 C CNN "URL"
|
||||
1 6650 2550
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
6450 3650 6550 3650
|
||||
Connection ~ 6450 3650
|
||||
Wire Wire Line
|
||||
6650 3650 6750 3650
|
||||
Connection ~ 6750 3650
|
||||
Wire Wire Line
|
||||
6750 3650 6850 3650
|
||||
Wire Wire Line
|
||||
6550 3650 6650 3650
|
||||
Connection ~ 6550 3650
|
||||
Connection ~ 6650 3650
|
||||
Text Label 4900 2650 0 50 ~ 0
|
||||
HDMI_CEC_B
|
||||
Text Label 5000 2850 0 50 ~ 0
|
||||
HDMI_SCL_B
|
||||
Text Label 5100 2950 0 50 ~ 0
|
||||
HDMI_SDA_B
|
||||
Text Label 5700 3000 0 50 ~ 0
|
||||
HDMI_HPD_B
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 6148D34D
|
||||
P 2250 1350
|
||||
AR Path="/5F69F4EF/6148D34D" Ref="C?" Part="1"
|
||||
AR Path="/5F6B165A/6148D34D" Ref="C8" Part="1"
|
||||
AR Path="/612D28DD/6148D34D" Ref="C15" Part="1"
|
||||
AR Path="/61B62C00/6148D34D" Ref="C12" Part="1"
|
||||
F 0 "C12" H 2275 1450 50 0000 L CNN
|
||||
F 1 "47uF 10V+" H 2275 1250 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0805_2012Metric" H 2288 1200 50 0001 C CNN
|
||||
F 3 "" H 2250 1350 50 0000 C CNN
|
||||
F 4 "GRM21BR61A476ME15L # 10V" H 2250 1350 50 0001 C CNN "MPN-ALT3"
|
||||
F 5 "GRM21BR60J476ME15L # 6V3 # delay" H 2250 1350 50 0001 C CNN "MPN-ALT2"
|
||||
F 6 "CC0805MRX5R5BB476 # obsolete" H 2250 1350 50 0001 C CNN "MPN-ALT"
|
||||
F 7 "GRM21BR60J476ME01L" H 2250 1350 50 0001 C CNN "MPN-PREV"
|
||||
F 8 "https://www2.mouser.com/ProductDetail/Murata/GRM21BR60J476ME15L?qs=Tw3AuTVwGeLlkNhaDtjM1w%3D%3D" H 2250 1350 50 0001 C CNN "URL-ALT2"
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14
nubus-to-ztex/nubus-to-ztex-NPTH.drl
Normal file
14
nubus-to-ztex/nubus-to-ztex-NPTH.drl
Normal file
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417
nubus-to-ztex/nubus-to-ztex-PTH.drl
Normal file
417
nubus-to-ztex/nubus-to-ztex-PTH.drl
Normal file
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M48
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||||
X5.2402Y-2.937
|
||||
X5.2696Y-3.4646
|
||||
X5.2874Y-3.2945
|
||||
X5.311Y-3.0748
|
||||
X5.3405Y-3.4646
|
||||
X5.3622Y-3.0682
|
||||
X5.3898Y-2.8661
|
||||
X5.4055Y-3.1129
|
||||
X5.4113Y-3.4646
|
||||
X5.4291Y-2.9094
|
||||
X5.4291Y-3.1575
|
||||
X5.4567Y-2.8307
|
||||
X5.4792Y-3.4652
|
||||
X5.4882Y-2.8799
|
||||
X5.4921Y-2.6142
|
||||
X5.5768Y-0.5651
|
||||
X5.5866Y-2.6654
|
||||
X5.6535Y-2.9724
|
||||
X5.6575Y-3.0157
|
||||
X5.7047Y-3.1693
|
||||
X5.7874Y-3.0635
|
||||
X5.8465Y-3.0906
|
||||
X5.8563Y-2.9011
|
||||
X5.9016Y-2.7953
|
||||
X6.1164Y-3.1398
|
||||
X6.3681Y-2.9011
|
||||
X6.4173Y-2.7953
|
||||
X6.6282Y-3.1398
|
||||
X6.6465Y-2.1953
|
||||
X6.9016Y-2.9016
|
||||
X6.9488Y-2.7953
|
||||
X7.1597Y-3.1398
|
||||
X7.3524Y-2.9011
|
||||
X7.4016Y-2.7953
|
||||
X7.6125Y-3.1398
|
||||
X8.6945Y-3.8571
|
||||
X8.7539Y-2.0996
|
||||
X8.8012Y-1.8396
|
||||
X8.8244Y-3.7795
|
||||
X8.828Y-1.993
|
||||
X8.839Y-1.8652
|
||||
X8.9008Y-2.0669
|
||||
X9.1748Y-1.6757
|
||||
X9.1929Y-1.8652
|
||||
X9.2094Y-2.05
|
||||
X9.2213Y-1.9931
|
||||
X9.2736Y-1.7377
|
||||
X9.369Y-1.4634
|
||||
X9.4965Y-1.4165
|
||||
X9.5618Y-1.1878
|
||||
X9.5972Y-1.385
|
||||
X9.6949Y-0.876
|
||||
X9.7165Y-1.0354
|
||||
X9.7252Y-1.1618
|
||||
X9.7902Y-1.365
|
||||
X9.7969Y-1.5861
|
||||
X9.7988Y-0.6366
|
||||
X9.9016Y-0.9094
|
||||
X9.9154Y-1.3673
|
||||
X9.9154Y-1.4354
|
||||
X9.9213Y-1.2303
|
||||
X9.9213Y-1.2992
|
||||
X9.9567Y-3.2571
|
||||
X9.9941Y-3.4512
|
||||
X10.0492Y-1.0728
|
||||
X10.0787Y-0.876
|
||||
X10.0787Y-1.1614
|
||||
X10.0787Y-1.2303
|
||||
X10.0787Y-1.2992
|
||||
X10.0791Y-3.4614
|
||||
X10.2661Y-2.5899
|
||||
X10.3402Y-3.1242
|
||||
X10.5118Y-2.2854
|
||||
X10.5118Y-2.5807
|
||||
X10.5402Y-3.0386
|
||||
X10.5406Y-3.1242
|
||||
T3
|
||||
X9.9425Y-0.5268
|
||||
X9.9425Y-0.6252
|
||||
T4
|
||||
X10.5983Y-3.0146
|
||||
X10.5983Y-3.2114
|
||||
T5
|
||||
X8.513Y-1.0827
|
||||
X8.513Y-1.1614
|
||||
X8.5917Y-1.0827
|
||||
X8.5917Y-1.1614
|
||||
X8.6705Y-1.0827
|
||||
X8.6705Y-1.1614
|
||||
X8.7492Y-1.0827
|
||||
X8.7492Y-1.1614
|
||||
X8.828Y-1.0827
|
||||
X8.828Y-1.1614
|
||||
X8.9067Y-1.0827
|
||||
X8.9067Y-1.1614
|
||||
X8.9854Y-1.0827
|
||||
X8.9854Y-1.1614
|
||||
X4.5118Y-2.5118
|
||||
X4.5118Y-2.5906
|
||||
X4.5118Y-2.6693
|
||||
X4.5118Y-2.748
|
||||
X4.5118Y-2.8268
|
||||
X4.5118Y-2.9055
|
||||
X4.5118Y-2.9843
|
||||
X4.5906Y-2.5118
|
||||
X4.5906Y-2.5906
|
||||
X4.5906Y-2.6693
|
||||
X4.5906Y-2.748
|
||||
X4.5906Y-2.8268
|
||||
X4.5906Y-2.9055
|
||||
X4.5906Y-2.9843
|
||||
T6
|
||||
X4.774Y-3.737
|
||||
X4.774Y-3.837
|
||||
X4.774Y-3.937
|
||||
X4.874Y-3.737
|
||||
X4.874Y-3.837
|
||||
X4.874Y-3.937
|
||||
X4.974Y-3.737
|
||||
X4.974Y-3.837
|
||||
X4.974Y-3.937
|
||||
X5.074Y-3.737
|
||||
X5.074Y-3.837
|
||||
X5.074Y-3.937
|
||||
X5.174Y-3.737
|
||||
X5.174Y-3.837
|
||||
X5.174Y-3.937
|
||||
X5.274Y-3.737
|
||||
X5.274Y-3.837
|
||||
X5.274Y-3.937
|
||||
X5.374Y-3.737
|
||||
X5.374Y-3.837
|
||||
X5.374Y-3.937
|
||||
X5.474Y-3.737
|
||||
X5.474Y-3.837
|
||||
X5.474Y-3.937
|
||||
X5.574Y-3.737
|
||||
X5.574Y-3.837
|
||||
X5.574Y-3.937
|
||||
X5.674Y-3.737
|
||||
X5.674Y-3.837
|
||||
X5.674Y-3.937
|
||||
X5.774Y-3.737
|
||||
X5.774Y-3.837
|
||||
X5.774Y-3.937
|
||||
X5.874Y-3.737
|
||||
X5.874Y-3.837
|
||||
X5.874Y-3.937
|
||||
X5.974Y-3.737
|
||||
X5.974Y-3.837
|
||||
X5.974Y-3.937
|
||||
X6.074Y-3.737
|
||||
X6.074Y-3.837
|
||||
X6.074Y-3.937
|
||||
X6.174Y-3.737
|
||||
X6.174Y-3.837
|
||||
X6.174Y-3.937
|
||||
X6.274Y-3.737
|
||||
X6.274Y-3.837
|
||||
X6.274Y-3.937
|
||||
X6.374Y-3.737
|
||||
X6.374Y-3.837
|
||||
X6.374Y-3.937
|
||||
X6.474Y-3.737
|
||||
X6.474Y-3.837
|
||||
X6.474Y-3.937
|
||||
X6.574Y-3.737
|
||||
X6.574Y-3.837
|
||||
X6.574Y-3.937
|
||||
X6.674Y-3.737
|
||||
X6.674Y-3.837
|
||||
X6.674Y-3.937
|
||||
X6.774Y-3.737
|
||||
X6.774Y-3.837
|
||||
X6.774Y-3.937
|
||||
X6.874Y-3.737
|
||||
X6.874Y-3.837
|
||||
X6.874Y-3.937
|
||||
X6.974Y-3.737
|
||||
X6.974Y-3.837
|
||||
X6.974Y-3.937
|
||||
X7.074Y-3.737
|
||||
X7.074Y-3.837
|
||||
X7.074Y-3.937
|
||||
X7.174Y-3.737
|
||||
X7.174Y-3.837
|
||||
X7.174Y-3.937
|
||||
X7.274Y-3.737
|
||||
X7.274Y-3.837
|
||||
X7.274Y-3.937
|
||||
X7.374Y-3.737
|
||||
X7.374Y-3.837
|
||||
X7.374Y-3.937
|
||||
X7.474Y-3.737
|
||||
X7.474Y-3.837
|
||||
X7.474Y-3.937
|
||||
X7.574Y-3.737
|
||||
X7.574Y-3.837
|
||||
X7.574Y-3.937
|
||||
X7.674Y-3.737
|
||||
X7.674Y-3.837
|
||||
X7.674Y-3.937
|
||||
X7.774Y-3.737
|
||||
X7.774Y-3.837
|
||||
X7.774Y-3.937
|
||||
X7.874Y-3.737
|
||||
X7.874Y-3.837
|
||||
X7.874Y-3.937
|
||||
T7
|
||||
X7.9854Y-3.1134
|
||||
X8.0854Y-3.1134
|
||||
X4.7992Y-0.8189
|
||||
X4.7992Y-0.9189
|
||||
X4.7992Y-1.0189
|
||||
X4.7992Y-1.1189
|
||||
X4.7992Y-1.2189
|
||||
X4.7992Y-1.3189
|
||||
T8
|
||||
X5.1181Y-2.3311
|
||||
X5.1181Y-2.4311
|
||||
X5.2181Y-2.3311
|
||||
X5.2181Y-2.4311
|
||||
X5.3181Y-2.3311
|
||||
X5.3181Y-2.4311
|
||||
X5.4181Y-2.3311
|
||||
X5.4181Y-2.4311
|
||||
X5.5181Y-2.3311
|
||||
X5.5181Y-2.4311
|
||||
X5.6181Y-2.3311
|
||||
X5.6181Y-2.4311
|
||||
X5.7181Y-2.3311
|
||||
X5.7181Y-2.4311
|
||||
X5.8181Y-2.3311
|
||||
X5.8181Y-2.4311
|
||||
X5.9181Y-2.3311
|
||||
X5.9181Y-2.4311
|
||||
X6.0181Y-2.3311
|
||||
X6.0181Y-2.4311
|
||||
X6.1181Y-2.3311
|
||||
X6.1181Y-2.4311
|
||||
X6.2181Y-2.3311
|
||||
X6.2181Y-2.4311
|
||||
X6.3181Y-2.3311
|
||||
X6.3181Y-2.4311
|
||||
X6.4181Y-2.3311
|
||||
X6.4181Y-2.4311
|
||||
X6.5181Y-2.3311
|
||||
X6.5181Y-2.4311
|
||||
X6.6181Y-2.3311
|
||||
X6.6181Y-2.4311
|
||||
X6.7181Y-2.3311
|
||||
X6.7181Y-2.4311
|
||||
X6.8181Y-2.3311
|
||||
X6.8181Y-2.4311
|
||||
X6.9181Y-2.3311
|
||||
X6.9181Y-2.4311
|
||||
X7.0181Y-2.3311
|
||||
X7.0181Y-2.4311
|
||||
X7.1181Y-2.3311
|
||||
X7.1181Y-2.4311
|
||||
X7.2181Y-2.3311
|
||||
X7.2181Y-2.4311
|
||||
X7.3181Y-2.3311
|
||||
X7.3181Y-2.4311
|
||||
X7.4181Y-2.3311
|
||||
X7.4181Y-2.4311
|
||||
X7.5181Y-2.3311
|
||||
X7.5181Y-2.4311
|
||||
X7.6181Y-2.3311
|
||||
X7.6181Y-2.4311
|
||||
X7.7181Y-2.3311
|
||||
X7.7181Y-2.4311
|
||||
X7.8181Y-2.3311
|
||||
X7.8181Y-2.4311
|
||||
X7.9181Y-2.3311
|
||||
X7.9181Y-2.4311
|
||||
X8.0181Y-2.3311
|
||||
X8.0181Y-2.4311
|
||||
X8.1181Y-2.3311
|
||||
X8.1181Y-2.4311
|
||||
X8.2181Y-2.3311
|
||||
X8.2181Y-2.4311
|
||||
X5.1181Y-1.0811
|
||||
X5.1181Y-1.1811
|
||||
X5.2181Y-1.0811
|
||||
X5.2181Y-1.1811
|
||||
X5.3181Y-1.0811
|
||||
X5.3181Y-1.1811
|
||||
X5.4181Y-1.0811
|
||||
X5.4181Y-1.1811
|
||||
X5.5181Y-1.0811
|
||||
X5.5181Y-1.1811
|
||||
X5.6181Y-1.0811
|
||||
X5.6181Y-1.1811
|
||||
X5.7181Y-1.0811
|
||||
X5.7181Y-1.1811
|
||||
X5.8181Y-1.0811
|
||||
X5.8181Y-1.1811
|
||||
X5.9181Y-1.0811
|
||||
X5.9181Y-1.1811
|
||||
X6.0181Y-1.0811
|
||||
X6.0181Y-1.1811
|
||||
X6.1181Y-1.0811
|
||||
X6.1181Y-1.1811
|
||||
X6.2181Y-1.0811
|
||||
X6.2181Y-1.1811
|
||||
X6.3181Y-1.0811
|
||||
X6.3181Y-1.1811
|
||||
X6.4181Y-1.0811
|
||||
X6.4181Y-1.1811
|
||||
X6.5181Y-1.0811
|
||||
X6.5181Y-1.1811
|
||||
X6.6181Y-1.0811
|
||||
X6.6181Y-1.1811
|
||||
X6.7181Y-1.0811
|
||||
X6.7181Y-1.1811
|
||||
X6.8181Y-1.0811
|
||||
X6.8181Y-1.1811
|
||||
X6.9181Y-1.0811
|
||||
X6.9181Y-1.1811
|
||||
X7.0181Y-1.0811
|
||||
X7.0181Y-1.1811
|
||||
X7.1181Y-1.0811
|
||||
X7.1181Y-1.1811
|
||||
X7.2181Y-1.0811
|
||||
X7.2181Y-1.1811
|
||||
X7.3181Y-1.0811
|
||||
X7.3181Y-1.1811
|
||||
X7.4181Y-1.0811
|
||||
X7.4181Y-1.1811
|
||||
X7.5181Y-1.0811
|
||||
X7.5181Y-1.1811
|
||||
X7.6181Y-1.0811
|
||||
X7.6181Y-1.1811
|
||||
X7.7181Y-1.0811
|
||||
X7.7181Y-1.1811
|
||||
X7.8181Y-1.0811
|
||||
X7.8181Y-1.1811
|
||||
X7.9181Y-1.0811
|
||||
X7.9181Y-1.1811
|
||||
X8.0181Y-1.0811
|
||||
X8.0181Y-1.1811
|
||||
X8.1181Y-1.0811
|
||||
X8.1181Y-1.1811
|
||||
X8.2181Y-1.0811
|
||||
X8.2181Y-1.1811
|
||||
T9
|
||||
X10.215Y-1.1535
|
||||
X10.215Y-1.2437
|
||||
X10.215Y-1.3339
|
||||
X10.215Y-1.424
|
||||
X10.215Y-1.5142
|
||||
X10.315Y-1.1087
|
||||
X10.315Y-1.1988
|
||||
X10.315Y-1.289
|
||||
X10.315Y-1.3791
|
||||
X10.315Y-1.4693
|
||||
X10.415Y-1.1535
|
||||
X10.415Y-1.2437
|
||||
X10.415Y-1.3337
|
||||
X10.415Y-1.424
|
||||
X10.415Y-1.5142
|
||||
T10
|
||||
X8.5921Y-3.5933
|
||||
X8.6921Y-3.5933
|
||||
X8.7921Y-3.5933
|
||||
X4.5354Y-3.2567
|
||||
X4.5354Y-3.3567
|
||||
X4.5354Y-3.4567
|
||||
T11
|
||||
X10.4665Y-2.1673
|
||||
X10.4665Y-2.7382
|
||||
X10.6614Y-2.1437
|
||||
X10.6614Y-2.7618
|
||||
T12
|
||||
X10.315Y-0.8319
|
||||
X10.315Y-1.8161
|
||||
T2
|
||||
X10.6908Y-2.9752G85X10.7184Y-2.9752
|
||||
G05
|
||||
X10.7184Y-3.2508G85X10.6908Y-3.2508
|
||||
G05
|
||||
T0
|
||||
M30
|
6
nubus-to-ztex/nubus-to-ztex-bottom.pos
Normal file
6
nubus-to-ztex/nubus-to-ztex-bottom.pos
Normal file
|
@ -0,0 +1,6 @@
|
|||
### Module positions - created on Mon Dec 20 11:52:17 2021 ###
|
||||
### Printed by Pcbnew version kicad 5.0.2+dfsg1-1~bpo9+1
|
||||
## Unit = mm, Angle = deg.
|
||||
## Side : bottom
|
||||
# Ref Val Package PosX PosY Rot Side
|
||||
## End
|
1133
nubus-to-ztex/nubus-to-ztex-cache.lib
Normal file
1133
nubus-to-ztex/nubus-to-ztex-cache.lib
Normal file
File diff suppressed because it is too large
Load Diff
36
nubus-to-ztex/nubus-to-ztex-drl.rpt
Normal file
36
nubus-to-ztex/nubus-to-ztex-drl.rpt
Normal file
|
@ -0,0 +1,36 @@
|
|||
Drill report for /home/dolbeau/MAC/NuBusFPGA/nubus-to-ztex/nubus-to-ztex.kicad_pcb
|
||||
Created on Sun Dec 19 16:53:35 2021
|
||||
|
||||
Copper Layer Stackup:
|
||||
=============================================================
|
||||
L1 : F.Cu front
|
||||
L2 : In1.Cu in1
|
||||
L3 : In2.Cu in2
|
||||
L4 : B.Cu back
|
||||
|
||||
|
||||
Drill file 'nubus-to-ztex-PTH.drl' contains
|
||||
plated through holes:
|
||||
=============================================================
|
||||
T1 0.40mm 0.016" (88 holes)
|
||||
T2 0.60mm 0.024" (2 holes) (with 2 slots)
|
||||
T3 0.80mm 0.031" (2 holes)
|
||||
T4 0.85mm 0.033" (2 holes)
|
||||
T5 0.90mm 0.035" (28 holes)
|
||||
T6 1.00mm 0.039" (96 holes)
|
||||
T7 1.02mm 0.040" (8 holes)
|
||||
T8 1.14mm 0.045" (128 holes)
|
||||
T9 1.19mm 0.047" (15 holes)
|
||||
T10 1.20mm 0.047" (3 holes)
|
||||
T11 1.30mm 0.051" (4 holes)
|
||||
T12 3.05mm 0.120" (2 holes)
|
||||
|
||||
Total plated holes count 378
|
||||
|
||||
|
||||
Drill file 'nubus-to-ztex-NPTH.drl' contains
|
||||
unplated through holes:
|
||||
=============================================================
|
||||
T1 2.85mm 0.112" (2 holes)
|
||||
|
||||
Total unplated holes count 2
|
78
nubus-to-ztex/nubus-to-ztex-top.pos
Normal file
78
nubus-to-ztex/nubus-to-ztex-top.pos
Normal file
|
@ -0,0 +1,78 @@
|
|||
### Module positions - created on Mon Dec 20 11:52:17 2021 ###
|
||||
### Printed by Pcbnew version kicad 5.0.2+dfsg1-1~bpo9+1
|
||||
## Unit = mm, Angle = deg.
|
||||
## Side : top
|
||||
# Ref Val Package PosX PosY Rot Side
|
||||
C1 100nF C_0603_1608Metric 128.4000 -75.1000 270.0000 top
|
||||
C2 100nF C_0603_1608Metric 188.0000 -72.9000 90.0000 top
|
||||
C3 10nF C_0603_1608Metric 144.0000 -78.6000 270.0000 top
|
||||
C4 100nF C_0603_1608Metric 166.8400 -55.7600 0.0000 top
|
||||
C5 10nF C_0603_1608Metric 248.0100 -25.0000 90.0000 top
|
||||
C6 100nF C_0603_1608Metric 238.7600 -35.9800 180.0000 top
|
||||
C7 100nF C_0603_1608Metric 254.0000 -29.5000 0.0000 top
|
||||
C8 10nF C_0603_1608Metric 254.0000 -33.0000 0.0000 top
|
||||
C9 10nF C_0603_1608Metric 240.4200 -37.8800 180.0000 top
|
||||
C10 1uF C_0603_1608Metric 253.3300 -27.8100 0.0000 top
|
||||
C12 47uF_10V+ C_0805_2012Metric 237.5400 -42.5600 180.0000 top
|
||||
C13 100nF C_0603_1608Metric 234.2900 -43.3500 90.0000 top
|
||||
C14 100nF C_0603_1608Metric 222.3500 -51.4100 270.0000 top
|
||||
C15 100nF C_0603_1608Metric 262.0300 -66.5700 270.0000 top
|
||||
C16 150uF C_1206_3216Metric 257.4100 -86.3600 180.0000 top
|
||||
C17 100nF C_0603_1608Metric 254.6300 -89.0600 0.0000 top
|
||||
C18 100nF C_0603_1608Metric 253.0500 -81.4600 180.0000 top
|
||||
C19 100nF C_0603_1608Metric 172.3750 -33.6000 180.0000 top
|
||||
C20 47uF_10V+ C_0805_2012Metric 221.7800 -96.0000 0.0000 top
|
||||
C21 10nF C_0603_1608Metric 231.8200 -41.7700 90.0000 top
|
||||
C22 10nF C_0603_1608Metric 139.8000 -67.7000 0.0000 top
|
||||
C23 100nF C_0603_1608Metric 149.9000 -72.9000 90.0000 top
|
||||
C24 100nF C_0603_1608Metric 163.0000 -72.9000 90.0000 top
|
||||
C25 100nF C_0603_1608Metric 176.5000 -72.9000 90.0000 top
|
||||
C26 100nF C_0603_1608Metric 125.8000 -73.1000 0.0000 top
|
||||
C27 100nF C_0603_1608Metric 145.8000 -78.6000 270.0000 top
|
||||
C28 10nF C_0603_1608Metric 128.4000 -71.0000 90.0000 top
|
||||
C29 100nF C_0603_1608Metric 254.0000 -31.2500 0.0000 top
|
||||
C30 100nF C_0603_1608Metric 141.6500 -66.0000 0.0000 top
|
||||
C31 47uF_10V+ C_0805_2012Metric 204.3000 -82.7000 0.0000 top
|
||||
C32 100nF C_0603_1608Metric 246.2500 -24.2500 90.0000 top
|
||||
C33 10uF C_0805_2012Metric 119.9000 -86.2000 270.0000 top
|
||||
D2 RED LED_0805_2012Metric 143.2200 -15.2900 270.0000 top
|
||||
D3 RED LED_0805_2012Metric 145.4667 -15.2900 270.0000 top
|
||||
D4 RED LED_0805_2012Metric 147.7133 -15.2900 270.0000 top
|
||||
D5 RED LED_0805_2012Metric 149.9600 -15.2900 270.0000 top
|
||||
FB1 Ferrite_Bead_Small L_0805_2012Metric 257.8700 -84.0700 0.0000 top
|
||||
J5 HDMI_A HDMI_A_Amphenol_10029449-111 267.9000 -62.3000 90.0000 top
|
||||
J6 USB_micro-B USB_Micro-B_Molex-105017-0001 270.6600 -79.0700 90.0000 top
|
||||
R1 75 R_0603_1608Metric 251.5000 -25.0000 270.0000 top
|
||||
R2 10k R_0603_1608Metric 160.5000 -72.2000 180.0000 top
|
||||
R3 536 R_0603_1608Metric 249.7500 -25.0000 90.0000 top
|
||||
R4 1M R_1210_3225Metric 246.8200 -14.7700 270.0000 top
|
||||
R5 100 R_0603_1608Metric 253.9200 -34.7300 0.0000 top
|
||||
R6 100 R_0603_1608Metric 253.9100 -36.4600 0.0000 top
|
||||
R7 549 R_0603_1608Metric 143.2200 -18.8800 90.0000 top
|
||||
R8 549 R_0603_1608Metric 145.4667 -18.8800 90.0000 top
|
||||
R9 549 R_0603_1608Metric 147.7133 -18.8800 90.0000 top
|
||||
R10 549 R_0603_1608Metric 149.9600 -18.8800 90.0000 top
|
||||
R11 27 R_0603_1608Metric 263.5100 -76.5600 180.0000 top
|
||||
R12 27 R_0603_1608Metric 263.5100 -82.1500 180.0000 top
|
||||
R13 15k R_0603_1608Metric 260.8600 -77.8100 90.0000 top
|
||||
R14 15k R_0603_1608Metric 260.8600 -80.9000 90.0000 top
|
||||
R15 10k R_0603_1608Metric 249.2400 -86.3100 180.0000 top
|
||||
R16 10k R_0603_1608Metric 249.2400 -84.1100 180.0000 top
|
||||
R17 10k R_0603_1608Metric 125.0000 -66.9000 180.0000 top
|
||||
R18 75 R_0603_1608Metric 250.0000 -39.5000 90.0000 top
|
||||
R19 75 R_0603_1608Metric 252.0000 -39.5000 90.0000 top
|
||||
R20 1k R_0603_1608Metric 254.0000 -22.2500 180.0000 top
|
||||
R23 10k R_0603_1608Metric 139.2478 -86.0071 90.0000 top
|
||||
R24 10k R_0603_1608Metric 137.4478 -86.0071 90.0000 top
|
||||
R25 10k R_0603_1608Metric 135.6478 -86.0071 90.0000 top
|
||||
R26 10k R_0603_1608Metric 133.8478 -86.0071 90.0000 top
|
||||
U1 74LVC1G07 SOT-23-5 124.2000 -70.0000 270.0000 top
|
||||
U2 AD1580 SOT-23 254.2500 -25.0000 90.0000 top
|
||||
U6 SN65220 SOT-23-6 265.4000 -79.3550 180.0000 top
|
||||
U7 TPS2051C SOT-23-5 252.9000 -85.2100 270.0000 top
|
||||
U8 XC9536XL-VQ44 TQFP-44_10x10mm_P0.8mm_Xilinx 136.2000 -76.2000 90.0000 top
|
||||
U9 74FCT245ATQG QSOP-20_3.9x8.7mm_P0.635mm 152.5000 -78.5000 90.0000 top
|
||||
U10 74FCT245ATQG QSOP-20_3.9x8.7mm_P0.635mm 165.5000 -78.5000 90.0000 top
|
||||
U11 74FCT245ATQG QSOP-20_3.9x8.7mm_P0.635mm 179.0000 -78.5000 90.0000 top
|
||||
U12 74FCT245ATQG QSOP-20_3.9x8.7mm_P0.635mm 190.5000 -78.5000 90.0000 top
|
||||
## End
|
BIN
nubus-to-ztex/nubus-to-ztex.bin
Normal file
BIN
nubus-to-ztex/nubus-to-ztex.bin
Normal file
Binary file not shown.
36
nubus-to-ztex/nubus-to-ztex.csv
Normal file
36
nubus-to-ztex/nubus-to-ztex.csv
Normal file
|
@ -0,0 +1,36 @@
|
|||
Part/Designator,Manufacture Part Number/Seeed SKU,Quantity,URL
|
||||
"R5,R6",0603WAF1000T5E,2,https://lcsc.com/product-detail/Chip-Resistor-Surface-Mount_Uniroyal-Elec-0603WAF1000T5E_C22775.html
|
||||
R20,0603WAF1001T5E,1,https://lcsc.com/product-detail/Chip-Resistor-Surface-Mount_UNI-ROYAL-Uniroyal-Elec-0603WAF1001T5E_C21190.html
|
||||
"R2,R15,R16,R17,R23,R24,R25,R26",0603WAF1002T5E,8,https://lcsc.com/product-detail/Chip-Resistor-Surface-Mount_UNI-ROYAL-Uniroyal-Elec-0603WAF1002T5E_C25804.html
|
||||
"R13,R14",0603WAF1502T5E,2,https://lcsc.com/product-detail/Chip-Resistor-Surface-Mount_UNI-ROYAL-Uniroyal-Elec-0603WAF1502T5E_C22809.html
|
||||
"R11,R12",0603WAF270JT5E,2,https://lcsc.com/product-detail/Chip-Resistor-Surface-Mount_UNI-ROYAL-Uniroyal-Elec-0603WAF270JT5E_C25190.html
|
||||
R3,0603WAF5360T5E,1,https://lcsc.com/product-detail/Chip-Resistor-Surface-Mount_UNI-ROYAL-Uniroyal-Elec-0603WAF5360T5E_C23201.html
|
||||
"R7,R8,R9,R10",0603WAF5490T5E,4,https://lcsc.com/product-detail/Chip-Resistor-Surface-Mount_UNI-ROYAL-Uniroyal-Elec-0603WAF5490T5E_C23079.html
|
||||
"R1,R18,R19",0603WAF750JT5E,3,https://www.lcsc.com/product-detail/Chip-Resistor-Surface-Mount_Uniroyal-Elec-0603WAF750JT5E_C4275.html
|
||||
"JAB1,JCD1",10-89-7642,2,https://www2.mouser.com/ProductDetail/Molex/10-89-7642?qs=%2Fha2pyFadugCxzQFZUdvioDcljDVidgd4vXrOFuSRYM%3D
|
||||
J5,10029449-111,1,https://www2.mouser.com/ProductDetail/Amphenol-FCI/10029449-111RLF?qs=fmpTyLOWOey0HPdD9%2F%2FaXA%3D%3D
|
||||
J6,105017-0001,1,https://www.mouser.fr/ProductDetail/Molex/105017-0001?qs=hlXxxvYE36k7QcsR97GUKA%3D%3D
|
||||
R4,1210W2F1004T5E,1,https://www.lcsc.com/product-detail/Chip-Resistor-Surface-Mount_UNI-ROYAL-Uniroyal-Elec-1210W2F1004T5E_C620664.html
|
||||
"J7,J10",640456-3,2,https://www.lcsc.com/product-detail/Wire-To-Board-Wire-To-Wire-Connector_TE-Connectivity-640456-3_C86503.html
|
||||
"U9,U10,U11,U12",74FCT245ATQG,4,https://www.mouser.fr/ProductDetail/Renesas-IDT/74FCT245ATQG?qs=JcGQCygHkIZJMVzrAcertA%3D%3D
|
||||
J3,85003-0567,1,https://www.mouser.fr/ProductDetail/Molex/85003-0567?qs=U4pz39agNJB6P1oBpJ4bJA%3D%3D
|
||||
"J1,J8",87831-1420,2,https://www2.mouser.com/ProductDetail/Molex/87831-1420?qs=QtQX4uD3c2VDCL534TqpVg%3D%3D
|
||||
U2,AD1580ARTZ,1,https://www.mouser.fr/ProductDetail/Analog-Devices/AD1580ARTZ-REEL7?qs=NmRFExCfTkENN3U3%252BacLbA%3D%3D
|
||||
U4,ADV7125JSTZ240,1,https://lcsc.com/product-detail/Digital-To-Analog-Converters-DACs_Analog-Devices-ADV7125KSTZ50_C514374.html
|
||||
"C12,C20,C31",C2012X5R1A476MTJ00E,3,https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_TDK-C2012X5R1A476MTJ00E_C76636.html
|
||||
"C3,C5,C8,C9,C21,C22,C28",CC0603KRX7R8BB103,7,https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_YAGEO-CC0603KRX7R8BB103_C327204.html
|
||||
"C1,C2,C4,C6,C7,C13,C14,C15,C17,C18,C19,C23,C24,C25,C26,C27,C29,C30,C32",CC0603KRX7R8BB104,19,
|
||||
C10,CC0603KRX7R8BB105,1,https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_YAGEO-CC0603KRX7R8BB105_C106858.html
|
||||
C33,GRM21BR61E106MA73L,1,https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_Murata-Electronics-GRM21BR61E106MA73L_C391262.html
|
||||
C16,GRM31CR60J157ME11L,1,https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_Murata-Electronics-GRM31CR60J157ME11L_C528968.html
|
||||
C11,KM010M400E110A,1,https://lcsc.com/product-detail/Aluminum-Electrolytic-Capacitors-Leaded_Capxon-International-Elec-KM010M400E110A_C59365.html
|
||||
J4,L77HDE15SD1CH4F,1,https://www.mouser.fr/ProductDetail/Amphenol/L77HDE15SD1CH4F?qs=mq7kV%2Fq8lk6plQnZOUKCHg%3D%3D
|
||||
"D2,D3,D4,D5",LTST-C170KRKT,4,https://www.lcsc.com/product-detail/Light-Emitting-Diodes-LED_Lite-On-LTST-C170KRKT_C94868.html
|
||||
J9,PM254V-11-02-H85,1,https://www.lcsc.com/product-detail/Pin-Header-Female-Header_XFCN-PM254V-11-02-H85_C541849.html
|
||||
FB1,PZ2012U221-2R0TF,1,https://lcsc.com/product-detail/Ferrite-Beads_Sunlord-PZ2012U221-2R0TF_C44361.html
|
||||
J2,PZ254R-11-06P,1,https://lcsc.com/product-detail/Pin-Header-Female-Header_XFCN-PZ254R-11-06P_C492414.html
|
||||
U6,SN65220DBVR,1,https://www2.mouser.com/ProductDetail/Texas-Instruments/SN65220DBVR?qs=5nGYs9Do7G0gEpYxbYqyeA%3D%3D
|
||||
U1,SN74LVC1G07DBVR,1,https://www.mouser.fr/ProductDetail/Texas-Instruments/SN74LVC1G07DBVR?qs=FM6NhYOeeBXhZlYg%2Fa2W9g%3D%3D
|
||||
U5,TPD12S016PWR,1,
|
||||
U7,TPS2051CDBVR,1,https://www.mouser.fr/ProductDetail/Texas-Instruments/TPS2051CDBVR?qs=PF3AD18CSE5vi2HeWLJCmw%3D%3D
|
||||
U8,XC9536XL-10VQ44C,1,https://www2.mouser.com/ProductDetail/?qs=rrS6PyfT74dzgfwydI2z8g%3D%3D
|
|
752
nubus-to-ztex/nubus-to-ztex.d356
Normal file
752
nubus-to-ztex/nubus-to-ztex.d356
Normal file
|
@ -0,0 +1,752 @@
|
|||
P CODE 00
|
||||
P UNITS CUST 0
|
||||
P DIM N
|
||||
317GND VIA MD0157PA00X+100492Y-010728X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+092213Y-019931X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+091929Y-018652X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+100791Y-034614X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+095972Y-013850X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+105118Y-022854X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+103402Y-031242X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+099567Y-032571X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+087539Y-020996X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+105118Y-025807X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+055768Y-005651X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+091748Y-016757X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+088390Y-018652X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+095618Y-011878X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+055866Y-026654X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+088244Y-037795X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+056575Y-030157X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+057047Y-031693X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+054567Y-028307X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+066465Y-021953X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+066282Y-031398X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+061164Y-031398X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+071597Y-031398X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+076125Y-031398X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+064173Y-027953X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+074016Y-027953X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+069488Y-027953X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+059016Y-027953X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+052874Y-032945X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+050039Y-027643X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+050551Y-030354X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+047480Y-027087X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+100787Y-012992X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+100787Y-012303X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+097902Y-013650X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+097252Y-011618X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+096949Y-008760X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+097988Y-006366X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+105406Y-031242X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+105402Y-030386X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+099016Y-009094X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+097969Y-015861X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+093690Y-014634X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+097165Y-010354X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+073524Y-029011X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+069016Y-029016X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+058563Y-029011X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+063681Y-029011X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+050807Y-028740X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+092736Y-017377X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+054921Y-026142X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+088012Y-018396X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+057874Y-030635X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+049218Y-029291X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+050000Y-026339X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+089008Y-020669X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+099213Y-012303X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+099213Y-012992X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+100787Y-011614X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+100787Y-008760X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+094965Y-014165X0315Y0000R000S3
|
||||
317+5V VIA MD0157PA00X+099941Y-034512X0315Y0000R000S3
|
||||
317+5V VIA MD0157PA00X+088280Y-019930X0315Y0000R000S3
|
||||
317+5V VIA MD0157PA00X+054113Y-034646X0315Y0000R000S3
|
||||
317+5V VIA MD0157PA00X+053405Y-034646X0315Y0000R000S3
|
||||
317+5V VIA MD0157PA00X+052696Y-034646X0315Y0000R000S3
|
||||
317+5V VIA MD0157PA00X+054792Y-034652X0315Y0000R000S3
|
||||
317+5V VIA MD0157PA00X+086945Y-038571X0315Y0000R000S3
|
||||
317~RESET_5V VIA MD0157PA00X+056535Y-029724X0315Y0000R000S3
|
||||
317~TM1_5V VIA MD0157PA00X+051969Y-029685X0315Y0000R000S3
|
||||
317~NMRQ_5V VIA MD0157PA00X+048898Y-032913X0315Y0000R000S3
|
||||
317~TM0_5V VIA MD0157PA00X+052402Y-029370X0315Y0000R000S3
|
||||
317~START_3V3 VIA MD0157PA00X+051929Y-030630X0315Y0000R000S3
|
||||
317~ACK_3V3 VIA MD0157PA00X+050748Y-030945X0315Y0000R000S3
|
||||
317~TM0_3V3 VIA MD0157PA00X+052008Y-026654X0315Y0000R000S3
|
||||
317~TM1_3V3 VIA MD0157PA00X+051220Y-027205X0315Y0000R000S3
|
||||
317FPGA_VGA_HS VIA MD0157PA00X+099154Y-013673X0315Y0000R000S3
|
||||
317FPGA_VGA_VS VIA MD0157PA00X+099154Y-014354X0315Y0000R000S3
|
||||
317HDMI_5V VIA MD0157PA00X+092094Y-020500X0315Y0000R000S3
|
||||
317HDMI_5V VIA MD0157PA00X+102661Y-025899X0315Y0000R000S3
|
||||
317NUBUS_AD_DIR VIA MD0157PA00X+058465Y-030906X0315Y0000R000S3
|
||||
317CPLD_JTAG_TDI VIA MD0157PA00X+053110Y-030748X0315Y0000R000S3
|
||||
317CPLD_JTAG_TDO VIA MD0157PA00X+053622Y-030682X0315Y0000R000S3
|
||||
317CPLD_JTAG_TDO VIA MD0157PA00X+054882Y-028799X0315Y0000R000S3
|
||||
317CPLD_JTAG_TMS VIA MD0157PA00X+054291Y-031575X0315Y0000R000S3
|
||||
317CPLD_JTAG_TCK VIA MD0157PA00X+054055Y-031129X0315Y0000R000S3
|
||||
317_CPLD_SIGNAL_2 VIA MD0157PA00X+054291Y-029094X0315Y0000R000S3
|
||||
317TO_CPLD_SIGNAL VIA MD0157PA00X+053898Y-028661X0315Y0000R000S3
|
||||
327/VGA/VGA_B R19 -2 A01X+099213Y-015241X0344Y0374R270S2
|
||||
327GND R19 -1 A01X+099213Y-015861X0344Y0374R270S2
|
||||
327+12V C33 -1 A01X+047205Y-033568X0384Y0551R090S2
|
||||
327GND C33 -2 A01X+047205Y-034306X0384Y0551R090S2
|
||||
317GND J10 -1 D0472PA00X+045354Y-034567X0685Y0866R270S0
|
||||
317+12V J10 -2 D0472PA00X+045354Y-033567X0685Y0866R270S0
|
||||
317GND J10 -3 D0472PA00X+045354Y-032567X0685Y0866R270S0
|
||||
327SHIELD J6 -6 A01X+107046Y-030736X0591Y0748R270S2
|
||||
317SHIELD J6 -6 D0335PA00X+105983Y-032114X0571Y0000R270S0
|
||||
327/USB/USB_D- J6 -2 A01X+105983Y-031386X0157Y0531R270S2
|
||||
327/USB/VBUS_USB0 J6 -1 A01X+105983Y-031642X0157Y0531R270S2
|
||||
327GND J6 -5 A01X+105983Y-030618X0157Y0531R270S2
|
||||
327NET-(J6-PAD4) J6 -4 A01X+105983Y-030874X0157Y0531R270S2
|
||||
327/USB/USB_D+ J6 -3 A01X+105983Y-031130X0157Y0531R270S2
|
||||
317SHIELD J6 -6 D0335PA00X+105983Y-030146X0571Y0000R270S0
|
||||
327SHIELD J6 -6 A01X+107046Y-031524X0591Y0748R270S2
|
||||
317SHIELD J6 -6 D0236PA00X+107046Y-032508X0472Y0748R090S0
|
||||
317SHIELD J6 -6 D0236PA00X+107046Y-029752X0472Y0748R270S0
|
||||
327SHIELD J6 -6 A01X+107046Y-029988X0472Y0748R270S2
|
||||
327SHIELD J6 -6 A01X+107046Y-032272X0472Y0748R270S2
|
||||
327/VGA/VREF U2 -1 A01X+099724Y-010236X0354Y0315R270S2
|
||||
327GND U2 -2 A01X+100472Y-010236X0354Y0315R270S2
|
||||
327NET-(U2-PAD3) U2 -3 A01X+100098Y-009449X0354Y0315R270S2
|
||||
327+3V3 R20 -1 A01X+100310Y-008760X0344Y0374R180S2
|
||||
327/VGA/VREF R20 -2 A01X+099690Y-008760X0344Y0374R180S2
|
||||
327GND U4 -1 A01X+095100Y-011681X0110Y0580R270S2
|
||||
327GND U4 -2 A01X+095100Y-011878X0110Y0580R270S2
|
||||
327FPGA_G0 U4 -3 A01X+095100Y-012075X0110Y0580R270S2
|
||||
327FPGA_G1 U4 -4 A01X+095100Y-012272X0110Y0580R270S2
|
||||
327FPGA_G2 U4 -5 A01X+095100Y-012469X0110Y0580R270S2
|
||||
327FPGA_G3 U4 -6 A01X+095100Y-012665X0110Y0580R270S2
|
||||
327FPGA_G4 U4 -7 A01X+095100Y-012862X0110Y0580R270S2
|
||||
327FPGA_G5 U4 -8 A01X+095100Y-013059X0110Y0580R270S2
|
||||
327FPGA_G6 U4 -9 A01X+095100Y-013256X0110Y0580R270S2
|
||||
327FPGA_G7 U4 -10 A01X+095100Y-013453X0110Y0580R270S2
|
||||
327+3V3 U4 -11 A01X+095100Y-013650X0110Y0580R270S2
|
||||
327GND U4 -12 A01X+095100Y-013846X0110Y0580R270S2
|
||||
327+3V3 U4 -13 A01X+095677Y-014424X0110Y0580R000S2
|
||||
327GND U4 -14 A01X+095874Y-014424X0110Y0580R000S2
|
||||
327GND U4 -15 A01X+096071Y-014424X0110Y0580R000S2
|
||||
327FPGA_B0 U4 -16 A01X+096268Y-014424X0110Y0580R000S2
|
||||
327FPGA_B1 U4 -17 A01X+096465Y-014424X0110Y0580R000S2
|
||||
327FPGA_B2 U4 -18 A01X+096661Y-014424X0110Y0580R000S2
|
||||
327FPGA_B3 U4 -19 A01X+096858Y-014424X0110Y0580R000S2
|
||||
327FPGA_B4 U4 -20 A01X+097055Y-014424X0110Y0580R000S2
|
||||
327FPGA_B5 U4 -21 A01X+097252Y-014424X0110Y0580R000S2
|
||||
327FPGA_B6 U4 -22 A01X+097449Y-014424X0110Y0580R000S2
|
||||
327FPGA_B7 U4 -23 A01X+097646Y-014424X0110Y0580R000S2
|
||||
327FPGA_VGA_CLK U4 -24 A01X+097843Y-014424X0110Y0580R000S2
|
||||
327GND U4 -25 A01X+098420Y-013846X0110Y0580R270S2
|
||||
327GND U4 -26 A01X+098420Y-013650X0110Y0580R270S2
|
||||
327GND U4 -27 A01X+098420Y-013453X0110Y0580R270S2
|
||||
327/VGA/VGA_B U4 -28 A01X+098420Y-013256X0110Y0580R270S2
|
||||
327+3V3 U4 -29 A01X+098420Y-013059X0110Y0580R270S2
|
||||
327+3V3 U4 -30 A01X+098420Y-012862X0110Y0580R270S2
|
||||
327GND U4 -31 A01X+098420Y-012665X0110Y0580R270S2
|
||||
327/VGA/VGA_G U4 -32 A01X+098420Y-012469X0110Y0580R270S2
|
||||
327GND U4 -33 A01X+098420Y-012272X0110Y0580R270S2
|
||||
327/VGA/VGA_R U4 -34 A01X+098420Y-012075X0110Y0580R270S2
|
||||
327/VGA/COMP U4 -35 A01X+098420Y-011878X0110Y0580R270S2
|
||||
327/VGA/VREF U4 -36 A01X+098420Y-011681X0110Y0580R270S2
|
||||
327/VGA/RSET U4 -37 A01X+097843Y-011104X0110Y0580R000S2
|
||||
327+3V3 U4 -38 A01X+097646Y-011104X0110Y0580R000S2
|
||||
327GND U4 -39 A01X+097449Y-011104X0110Y0580R000S2
|
||||
327GND U4 -40 A01X+097252Y-011104X0110Y0580R000S2
|
||||
327FPGA_R0 U4 -41 A01X+097055Y-011104X0110Y0580R000S2
|
||||
327FPGA_R1 U4 -42 A01X+096858Y-011104X0110Y0580R000S2
|
||||
327FPGA_R2 U4 -43 A01X+096661Y-011104X0110Y0580R000S2
|
||||
327FPGA_R3 U4 -44 A01X+096465Y-011104X0110Y0580R000S2
|
||||
327FPGA_R4 U4 -45 A01X+096268Y-011104X0110Y0580R000S2
|
||||
327FPGA_R5 U4 -46 A01X+096071Y-011104X0110Y0580R000S2
|
||||
327FPGA_R6 U4 -47 A01X+095874Y-011104X0110Y0580R000S2
|
||||
327FPGA_R7 U4 -48 A01X+095677Y-011104X0110Y0580R000S2
|
||||
327GND R18 -1 A01X+098425Y-015861X0344Y0374R270S2
|
||||
327/VGA/VGA_G R18 -2 A01X+098425Y-015241X0344Y0374R270S2
|
||||
327GND R1 -1 A01X+099016Y-009532X0344Y0374R090S2
|
||||
327/VGA/VGA_R R1 -2 A01X+099016Y-010153X0344Y0374R090S2
|
||||
327+3V3 C32 -1 A01X+096949Y-009857X0344Y0374R270S2
|
||||
327GND C32 -2 A01X+096949Y-009237X0344Y0374R270S2
|
||||
327~CLK_5V U8 -44 A01X+051378Y-031575X0630Y0217R180S2
|
||||
327~RQST_5V U8 -43 A01X+051378Y-031260X0630Y0217R180S2
|
||||
327~ACK_3V3 U8 -42 A01X+051378Y-030945X0630Y0217R180S2
|
||||
327~START_3V3 U8 -41 A01X+051378Y-030630X0630Y0217R180S2
|
||||
327_CPLD_SIGNAL_2 U8 -40 A01X+051378Y-030315X0630Y0217R180S2
|
||||
327TO_CPLD_SIGNAL U8 -39 A01X+051378Y-030000X0630Y0217R180S2
|
||||
327~TM1_5V U8 -38 A01X+051378Y-029685X0630Y0217R180S2
|
||||
327~TM0_5V U8 -37 A01X+051378Y-029370X0630Y0217R180S2
|
||||
327~RQST_3V3 U8 -36 A01X+051378Y-029055X0630Y0217R180S2
|
||||
327+3V3 U8 -35 A01X+051378Y-028740X0630Y0217R180S2
|
||||
327~TM1_3V3 U8 -34 A01X+051378Y-028425X0630Y0217R180S2
|
||||
327~TM0_3V3 U8 -33 A01X+052047Y-027756X0630Y0217R270S2
|
||||
327~ID3_3V3 U8 -32 A01X+052362Y-027756X0630Y0217R270S2
|
||||
327~ID2_3V3 U8 -31 A01X+052677Y-027756X0630Y0217R270S2
|
||||
327~ID1_3V3 U8 -30 A01X+052992Y-027756X0630Y0217R270S2
|
||||
327~ID0_3V3 U8 -29 A01X+053307Y-027756X0630Y0217R270S2
|
||||
327ARB U8 -28 A01X+053622Y-027756X0630Y0217R270S2
|
||||
327GRANT U8 -27 A01X+053937Y-027756X0630Y0217R270S2
|
||||
327+3V3 U8 -26 A01X+054252Y-027756X0630Y0217R270S2
|
||||
327GND U8 -25 A01X+054567Y-027756X0630Y0217R270S2
|
||||
327CPLD_JTAG_TDO U8 -24 A01X+054882Y-027756X0630Y0217R270S2
|
||||
327TMOEN U8 -23 A01X+055197Y-027756X0630Y0217R270S2
|
||||
327BUS_MASTER_DIR U8 -22 A01X+055866Y-028425X0630Y0217R180S2
|
||||
327~RESET_3V3 U8 -21 A01X+055866Y-028740X0630Y0217R180S2
|
||||
327~CLK_3V3 U8 -20 A01X+055866Y-029055X0630Y0217R180S2
|
||||
327NUBUS_OE U8 -19 A01X+055866Y-029370X0630Y0217R180S2
|
||||
327~RESET_5V U8 -18 A01X+055866Y-029685X0630Y0217R180S2
|
||||
327GND U8 -17 A01X+055866Y-030000X0630Y0217R180S2
|
||||
327~ARB3_5V U8 -16 A01X+055866Y-030315X0630Y0217R180S2
|
||||
327+3V3 U8 -15 A01X+055866Y-030630X0630Y0217R180S2
|
||||
327~ARB2_5V U8 -14 A01X+055866Y-030945X0630Y0217R180S2
|
||||
327~ARB1_5V U8 -13 A01X+055866Y-031260X0630Y0217R180S2
|
||||
327~ARB0_5V U8 -12 A01X+055866Y-031575X0630Y0217R180S2
|
||||
327CPLD_JTAG_TCK U8 -11 A01X+055197Y-032244X0630Y0217R270S2
|
||||
327CPLD_JTAG_TMS U8 -10 A01X+054882Y-032244X0630Y0217R270S2
|
||||
327CPLD_JTAG_TDI U8 -9 A01X+054567Y-032244X0630Y0217R270S2
|
||||
327~ID0_5V U8 -8 A01X+054252Y-032244X0630Y0217R270S2
|
||||
327~ID1_5V U8 -7 A01X+053937Y-032244X0630Y0217R270S2
|
||||
327~ID2_5V U8 -6 A01X+053622Y-032244X0630Y0217R270S2
|
||||
327~ID3_5V U8 -5 A01X+053307Y-032244X0630Y0217R270S2
|
||||
327GND U8 -4 A01X+052992Y-032244X0630Y0217R270S2
|
||||
327~ACK_5V U8 -3 A01X+052677Y-032244X0630Y0217R270S2
|
||||
327~START_5V U8 -2 A01X+052362Y-032244X0630Y0217R270S2
|
||||
327GA_TO_CPLD_CLK U8 -1 A01X+052047Y-032244X0630Y0217R270S2
|
||||
327+3V3 U11 -20 A01X+069347Y-029861X0630Y0161R270S2
|
||||
327NUBUS_OE U11 -19 A01X+069597Y-029861X0630Y0161R270S2
|
||||
327~AD14_3V3 U11 -18 A01X+069847Y-029861X0630Y0161R270S2
|
||||
327~AD11_3V3 U11 -13 A01X+071097Y-029861X0630Y0161R270S2
|
||||
327~AD8_3V3 U11 -12 A01X+071347Y-029861X0630Y0161R270S2
|
||||
327~AD9_3V3 U11 -11 A01X+071597Y-029861X0630Y0161R270S2
|
||||
327GND U11 -10 A01X+071597Y-031951X0630Y0161R270S2
|
||||
327~AD9_5V U11 -9 A01X+071347Y-031951X0630Y0161R270S2
|
||||
327~AD8_5V U11 -8 A01X+071097Y-031951X0630Y0161R270S2
|
||||
327~AD15_5V U11 -3 A01X+069847Y-031951X0630Y0161R270S2
|
||||
327~AD14_5V U11 -2 A01X+069597Y-031951X0630Y0161R270S2
|
||||
327NUBUS_AD_DIR U11 -1 A01X+069347Y-031951X0630Y0161R270S2
|
||||
327~AD12_5V U11 -4 A01X+070097Y-031951X0630Y0161R270S2
|
||||
327~AD13_5V U11 -5 A01X+070347Y-031951X0630Y0161R270S2
|
||||
327~AD12_3V3 U11 -16 A01X+070347Y-029861X0630Y0161R270S2
|
||||
327~AD15_3V3 U11 -17 A01X+070097Y-029861X0630Y0161R270S2
|
||||
327~AD10_5V U11 -6 A01X+070597Y-031951X0630Y0161R270S2
|
||||
327~AD11_5V U11 -7 A01X+070847Y-031951X0630Y0161R270S2
|
||||
327~AD13_3V3 U11 -15 A01X+070597Y-029861X0630Y0161R270S2
|
||||
327~AD10_3V3 U11 -14 A01X+070847Y-029861X0630Y0161R270S2
|
||||
327~AD18_3V3 U10 -14 A01X+065532Y-029861X0630Y0161R270S2
|
||||
327~AD21_3V3 U10 -15 A01X+065282Y-029861X0630Y0161R270S2
|
||||
327~AD19_5V U10 -7 A01X+065532Y-031951X0630Y0161R270S2
|
||||
327~AD18_5V U10 -6 A01X+065282Y-031951X0630Y0161R270S2
|
||||
327~AD23_3V3 U10 -17 A01X+064782Y-029861X0630Y0161R270S2
|
||||
327~AD20_3V3 U10 -16 A01X+065032Y-029861X0630Y0161R270S2
|
||||
327~AD21_5V U10 -5 A01X+065032Y-031951X0630Y0161R270S2
|
||||
327~AD20_5V U10 -4 A01X+064782Y-031951X0630Y0161R270S2
|
||||
327NUBUS_AD_DIR U10 -1 A01X+064032Y-031951X0630Y0161R270S2
|
||||
327~AD22_5V U10 -2 A01X+064282Y-031951X0630Y0161R270S2
|
||||
327~AD23_5V U10 -3 A01X+064532Y-031951X0630Y0161R270S2
|
||||
327~AD16_5V U10 -8 A01X+065782Y-031951X0630Y0161R270S2
|
||||
327~AD17_5V U10 -9 A01X+066032Y-031951X0630Y0161R270S2
|
||||
327GND U10 -10 A01X+066282Y-031951X0630Y0161R270S2
|
||||
327~AD17_3V3 U10 -11 A01X+066282Y-029861X0630Y0161R270S2
|
||||
327~AD16_3V3 U10 -12 A01X+066032Y-029861X0630Y0161R270S2
|
||||
327~AD19_3V3 U10 -13 A01X+065782Y-029861X0630Y0161R270S2
|
||||
327~AD22_3V3 U10 -18 A01X+064532Y-029861X0630Y0161R270S2
|
||||
327NUBUS_OE U10 -19 A01X+064282Y-029861X0630Y0161R270S2
|
||||
327+3V3 U10 -20 A01X+064032Y-029861X0630Y0161R270S2
|
||||
327+3V3 U9 -20 A01X+058914Y-029861X0630Y0161R270S2
|
||||
327NUBUS_OE U9 -19 A01X+059164Y-029861X0630Y0161R270S2
|
||||
327~AD31_3V3 U9 -18 A01X+059414Y-029861X0630Y0161R270S2
|
||||
327~AD26_3V3 U9 -13 A01X+060664Y-029861X0630Y0161R270S2
|
||||
327~AD25_3V3 U9 -12 A01X+060914Y-029861X0630Y0161R270S2
|
||||
327~AD24_3V3 U9 -11 A01X+061164Y-029861X0630Y0161R270S2
|
||||
327GND U9 -10 A01X+061164Y-031951X0630Y0161R270S2
|
||||
327~AD24_5V U9 -9 A01X+060914Y-031951X0630Y0161R270S2
|
||||
327~AD25_5V U9 -8 A01X+060664Y-031951X0630Y0161R270S2
|
||||
327~AD30_5V U9 -3 A01X+059414Y-031951X0630Y0161R270S2
|
||||
327~AD31_5V U9 -2 A01X+059164Y-031951X0630Y0161R270S2
|
||||
327NUBUS_AD_DIR U9 -1 A01X+058914Y-031951X0630Y0161R270S2
|
||||
327~AD29_5V U9 -4 A01X+059664Y-031951X0630Y0161R270S2
|
||||
327~AD28_5V U9 -5 A01X+059914Y-031951X0630Y0161R270S2
|
||||
327~AD29_3V3 U9 -16 A01X+059914Y-029861X0630Y0161R270S2
|
||||
327~AD30_3V3 U9 -17 A01X+059664Y-029861X0630Y0161R270S2
|
||||
327~AD27_5V U9 -6 A01X+060164Y-031951X0630Y0161R270S2
|
||||
327~AD26_5V U9 -7 A01X+060414Y-031951X0630Y0161R270S2
|
||||
327~AD28_3V3 U9 -15 A01X+060164Y-029861X0630Y0161R270S2
|
||||
327~AD27_3V3 U9 -14 A01X+060414Y-029861X0630Y0161R270S2
|
||||
327~AD2_3V3 U12 -14 A01X+075375Y-029861X0630Y0161R270S2
|
||||
327~AD5_3V3 U12 -15 A01X+075125Y-029861X0630Y0161R270S2
|
||||
327~AD3_5V U12 -7 A01X+075375Y-031951X0630Y0161R270S2
|
||||
327~AD2_5V U12 -6 A01X+075125Y-031951X0630Y0161R270S2
|
||||
327~AD7_3V3 U12 -17 A01X+074625Y-029861X0630Y0161R270S2
|
||||
327~AD4_3V3 U12 -16 A01X+074875Y-029861X0630Y0161R270S2
|
||||
327~AD5_5V U12 -5 A01X+074875Y-031951X0630Y0161R270S2
|
||||
327~AD4_5V U12 -4 A01X+074625Y-031951X0630Y0161R270S2
|
||||
327NUBUS_AD_DIR U12 -1 A01X+073875Y-031951X0630Y0161R270S2
|
||||
327~AD6_5V U12 -2 A01X+074125Y-031951X0630Y0161R270S2
|
||||
327~AD7_5V U12 -3 A01X+074375Y-031951X0630Y0161R270S2
|
||||
327~AD0_5V U12 -8 A01X+075625Y-031951X0630Y0161R270S2
|
||||
327~AD1_5V U12 -9 A01X+075875Y-031951X0630Y0161R270S2
|
||||
327GND U12 -10 A01X+076125Y-031951X0630Y0161R270S2
|
||||
327~AD1_3V3 U12 -11 A01X+076125Y-029861X0630Y0161R270S2
|
||||
327~AD0_3V3 U12 -12 A01X+075875Y-029861X0630Y0161R270S2
|
||||
327~AD3_3V3 U12 -13 A01X+075625Y-029861X0630Y0161R270S2
|
||||
327~AD6_3V3 U12 -18 A01X+074375Y-029861X0630Y0161R270S2
|
||||
327NUBUS_OE U12 -19 A01X+074125Y-029861X0630Y0161R270S2
|
||||
327+3V3 U12 -20 A01X+073875Y-029861X0630Y0161R270S2
|
||||
327N/C U1 -1 A01X+049272Y-027126X0417Y0256R090S2
|
||||
327~NMRQ_3V3 U1 -2 A01X+048898Y-027126X0417Y0256R090S2
|
||||
327GND U1 -3 A01X+048524Y-027126X0417Y0256R090S2
|
||||
327~NMRQ_5V U1 -4 A01X+048524Y-027992X0417Y0256R090S2
|
||||
327+3V3 U1 -5 A01X+049272Y-027992X0417Y0256R090S2
|
||||
327+3V3 C31 -1 A01X+080064Y-032559X0384Y0551R000S2
|
||||
327GND C31 -2 A01X+080802Y-032559X0384Y0551R000S2
|
||||
327GND C24 -2 A01X+064173Y-028391X0344Y0374R270S2
|
||||
327+3V3 C24 -1 A01X+064173Y-029011X0344Y0374R270S2
|
||||
317+3V3 J9 -1 D0402PA00X+079854Y-031134X0669Y0669R270S0
|
||||
317GND J9 -2 D0402PA00X+080854Y-031134X0669Y0669R270S0
|
||||
327+3V3 C30 -1 A01X+055458Y-025984X0344Y0374R000S2
|
||||
327GND C30 -2 A01X+056078Y-025984X0344Y0374R000S2
|
||||
327+3V3 C29 -1 A01X+099690Y-012303X0344Y0374R000S2
|
||||
327GND C29 -2 A01X+100310Y-012303X0344Y0374R000S2
|
||||
317GND J8 -1 D0354PA00X+045906Y-029843X0531Y0531R180S0
|
||||
317+3V3 J8 -2 D0354PA00X+045118Y-029843X0531Y0531R180S0
|
||||
317GND J8 -3 D0354PA00X+045906Y-029055X0531Y0531R180S0
|
||||
317CPLD_JTAG_TMS J8 -4 D0354PA00X+045118Y-029055X0531Y0531R180S0
|
||||
317GND J8 -5 D0354PA00X+045906Y-028268X0531Y0531R180S0
|
||||
317CPLD_JTAG_TCK J8 -6 D0354PA00X+045118Y-028268X0531Y0531R180S0
|
||||
317GND J8 -7 D0354PA00X+045906Y-027480X0531Y0531R180S0
|
||||
317CPLD_JTAG_TDO J8 -8 D0354PA00X+045118Y-027480X0531Y0531R180S0
|
||||
317GND J8 -9 D0354PA00X+045906Y-026693X0531Y0531R180S0
|
||||
317CPLD_JTAG_TDI J8 -10 D0354PA00X+045118Y-026693X0531Y0531R180S0
|
||||
317GND J8 -11 D0354PA00X+045906Y-025906X0531Y0531R180S0
|
||||
317NET-(J8-PAD12) J8 -12 D0354PA00X+045118Y-025906X0531Y0531R180S0
|
||||
317GND J8 -13 D0354PA00X+045906Y-025118X0531Y0531R180S0
|
||||
317NET-(J8-PAD14) J8 -14 D0354PA00X+045118Y-025118X0531Y0531R180S0
|
||||
327+3V3 C28 -1 A01X+050551Y-028263X0344Y0374R270S2
|
||||
327GND C28 -2 A01X+050551Y-027643X0344Y0374R270S2
|
||||
327+3V3 C27 -1 A01X+057402Y-030635X0344Y0374R090S2
|
||||
327GND C27 -2 A01X+057402Y-031255X0344Y0374R090S2
|
||||
327+3V3 C1 -1 A01X+050551Y-029257X0344Y0374R090S2
|
||||
327GND C1 -2 A01X+050551Y-029877X0344Y0374R090S2
|
||||
327+3V3 C25 -1 A01X+069488Y-029011X0344Y0374R270S2
|
||||
327GND C25 -2 A01X+069488Y-028391X0344Y0374R270S2
|
||||
327GND C2 -2 A01X+074016Y-028391X0344Y0374R270S2
|
||||
327+3V3 C2 -1 A01X+074016Y-029011X0344Y0374R270S2
|
||||
327+3V3 C26 -1 A01X+049218Y-028780X0344Y0374R000S2
|
||||
327GND C26 -2 A01X+049838Y-028780X0344Y0374R000S2
|
||||
327~NMRQ_3V3 R17 -2 A01X+048903Y-026339X0344Y0374R180S2
|
||||
327+3V3 R17 -1 A01X+049523Y-026339X0344Y0374R180S2
|
||||
327GND C22 -2 A01X+055349Y-026654X0344Y0374R000S2
|
||||
327+3V3 C22 -1 A01X+054729Y-026654X0344Y0374R000S2
|
||||
327+3V3 C23 -1 A01X+059016Y-029011X0344Y0374R270S2
|
||||
327GND C23 -2 A01X+059016Y-028391X0344Y0374R270S2
|
||||
327+3V3 C3 -1 A01X+056693Y-030635X0344Y0374R090S2
|
||||
327GND C3 -2 A01X+056693Y-031255X0344Y0374R090S2
|
||||
327+5V C20 -1 A01X+086946Y-037795X0384Y0551R000S2
|
||||
327GND C20 -2 A01X+087684Y-037795X0384Y0551R000S2
|
||||
317GND J7 -1 D0472PA00X+085921Y-035933X0685Y0866R000S0
|
||||
317+5V J7 -2 D0472PA00X+086921Y-035933X0685Y0866R000S0
|
||||
317GND J7 -3 D0472PA00X+087921Y-035933X0685Y0866R000S0
|
||||
327~ID1_5V R24 -2 A01X+054113Y-033551X0344Y0374R270S2
|
||||
327+5V R24 -1 A01X+054113Y-034171X0344Y0374R270S2
|
||||
327+5V R25 -1 A01X+053405Y-034171X0344Y0374R270S2
|
||||
327~ID2_5V R25 -2 A01X+053405Y-033551X0344Y0374R270S2
|
||||
327~ID3_5V R26 -2 A01X+052696Y-033551X0344Y0374R270S2
|
||||
327+5V R26 -1 A01X+052696Y-034171X0344Y0374R270S2
|
||||
327+5V R23 -1 A01X+054822Y-034171X0344Y0374R270S2
|
||||
327~ID0_5V R23 -2 A01X+054822Y-033551X0344Y0374R270S2
|
||||
327+3V3 C21 -1 A01X+091268Y-016755X0344Y0374R270S2
|
||||
327GND C21 -2 A01X+091268Y-016135X0344Y0374R270S2
|
||||
317ET-(JCD1-PAD1) JCD1 -1 D0449PA00X+051181Y-011811X0669Y0669R270S0
|
||||
317ET-(JCD1-PAD2) JCD1 -2 D0449PA00X+051181Y-010811X0669Y0669R270S0
|
||||
317GND JCD1 -3 D0449PA00X+052181Y-011811X0669Y0669R270S0
|
||||
317GND JCD1 -4 D0449PA00X+052181Y-010811X0669Y0669R270S0
|
||||
317/B2B/RX JCD1 -5 D0449PA00X+053181Y-011811X0669Y0669R270S0
|
||||
317/B2B/TX JCD1 -6 D0449PA00X+053181Y-010811X0669Y0669R270S0
|
||||
317~ID3_3V3 JCD1 -7 D0449PA00X+054181Y-011811X0669Y0669R270S0
|
||||
317~ID2_3V3 JCD1 -8 D0449PA00X+054181Y-010811X0669Y0669R270S0
|
||||
317~ID0_3V3 JCD1 -9 D0449PA00X+055181Y-011811X0669Y0669R270S0
|
||||
317~ID1_3V3 JCD1 -10 D0449PA00X+055181Y-010811X0669Y0669R270S0
|
||||
317TMOEN JCD1 -11 D0449PA00X+056181Y-011811X0669Y0669R270S0
|
||||
317LED0 JCD1 -12 D0449PA00X+056181Y-010811X0669Y0669R270S0
|
||||
317HDMI_HPD_A JCD1 -13 D0449PA00X+057181Y-011811X0669Y0669R270S0
|
||||
317LED1 JCD1 -14 D0449PA00X+057181Y-010811X0669Y0669R270S0
|
||||
317HDMI_SDA_A JCD1 -15 D0449PA00X+058181Y-011811X0669Y0669R270S0
|
||||
317LED2 JCD1 -16 D0449PA00X+058181Y-010811X0669Y0669R270S0
|
||||
317HDMI_SCL_A JCD1 -17 D0449PA00X+059181Y-011811X0669Y0669R270S0
|
||||
317LED3 JCD1 -18 D0449PA00X+059181Y-010811X0669Y0669R270S0
|
||||
317HDMI_CEC_A JCD1 -19 D0449PA00X+060181Y-011811X0669Y0669R270S0
|
||||
317FPGA_VGA_HS JCD1 -20 D0449PA00X+060181Y-010811X0669Y0669R270S0
|
||||
317HDMI_CLK+ JCD1 -21 D0449PA00X+061181Y-011811X0669Y0669R270S0
|
||||
317FPGA_VGA_VS JCD1 -22 D0449PA00X+061181Y-010811X0669Y0669R270S0
|
||||
317HDMI_CLK- JCD1 -23 D0449PA00X+062181Y-011811X0669Y0669R270S0
|
||||
317HDMI_D0- JCD1 -24 D0449PA00X+062181Y-010811X0669Y0669R270S0
|
||||
317HDMI_D1- JCD1 -25 D0449PA00X+063181Y-011811X0669Y0669R270S0
|
||||
317HDMI_D0+ JCD1 -26 D0449PA00X+063181Y-010811X0669Y0669R270S0
|
||||
317HDMI_D1+ JCD1 -27 D0449PA00X+064181Y-011811X0669Y0669R270S0
|
||||
317HDMI_D2- JCD1 -28 D0449PA00X+064181Y-010811X0669Y0669R270S0
|
||||
317FPGA_VGA_CLK JCD1 -29 D0449PA00X+065181Y-011811X0669Y0669R270S0
|
||||
317HDMI_D2+ JCD1 -30 D0449PA00X+065181Y-010811X0669Y0669R270S0
|
||||
317+3V3 JCD1 -31 D0449PA00X+066181Y-011811X0669Y0669R270S0
|
||||
317+3V3 JCD1 -32 D0449PA00X+066181Y-010811X0669Y0669R270S0
|
||||
317GND JCD1 -33 D0449PA00X+067181Y-011811X0669Y0669R270S0
|
||||
317GND JCD1 -34 D0449PA00X+067181Y-010811X0669Y0669R270S0
|
||||
317+3V3 JCD1 -35 D0449PA00X+068181Y-011811X0669Y0669R270S0
|
||||
317+3V3 JCD1 -36 D0449PA00X+068181Y-010811X0669Y0669R270S0
|
||||
317FPGA_B7 JCD1 -37 D0449PA00X+069181Y-011811X0669Y0669R270S0
|
||||
317FPGA_R0 JCD1 -38 D0449PA00X+069181Y-010811X0669Y0669R270S0
|
||||
317FPGA_B6 JCD1 -39 D0449PA00X+070181Y-011811X0669Y0669R270S0
|
||||
317FPGA_R1 JCD1 -40 D0449PA00X+070181Y-010811X0669Y0669R270S0
|
||||
317FPGA_B5 JCD1 -41 D0449PA00X+071181Y-011811X0669Y0669R270S0
|
||||
317FPGA_R2 JCD1 -42 D0449PA00X+071181Y-010811X0669Y0669R270S0
|
||||
317FPGA_B4 JCD1 -43 D0449PA00X+072181Y-011811X0669Y0669R270S0
|
||||
317FPGA_R3 JCD1 -44 D0449PA00X+072181Y-010811X0669Y0669R270S0
|
||||
317FPGA_B3 JCD1 -45 D0449PA00X+073181Y-011811X0669Y0669R270S0
|
||||
317FPGA_R4 JCD1 -46 D0449PA00X+073181Y-010811X0669Y0669R270S0
|
||||
317FPGA_B2 JCD1 -47 D0449PA00X+074181Y-011811X0669Y0669R270S0
|
||||
317FPGA_R5 JCD1 -48 D0449PA00X+074181Y-010811X0669Y0669R270S0
|
||||
317FPGA_B1 JCD1 -49 D0449PA00X+075181Y-011811X0669Y0669R270S0
|
||||
317FPGA_R6 JCD1 -50 D0449PA00X+075181Y-010811X0669Y0669R270S0
|
||||
317FPGA_B0 JCD1 -51 D0449PA00X+076181Y-011811X0669Y0669R270S0
|
||||
317FPGA_R7 JCD1 -52 D0449PA00X+076181Y-010811X0669Y0669R270S0
|
||||
317FPGA_G7 JCD1 -53 D0449PA00X+077181Y-011811X0669Y0669R270S0
|
||||
317FPGA_G0 JCD1 -54 D0449PA00X+077181Y-010811X0669Y0669R270S0
|
||||
317FPGA_G6 JCD1 -55 D0449PA00X+078181Y-011811X0669Y0669R270S0
|
||||
317FPGA_G1 JCD1 -56 D0449PA00X+078181Y-010811X0669Y0669R270S0
|
||||
317FPGA_G5 JCD1 -57 D0449PA00X+079181Y-011811X0669Y0669R270S0
|
||||
317FPGA_G2 JCD1 -58 D0449PA00X+079181Y-010811X0669Y0669R270S0
|
||||
317FPGA_G4 JCD1 -59 D0449PA00X+080181Y-011811X0669Y0669R270S0
|
||||
317FPGA_G3 JCD1 -60 D0449PA00X+080181Y-010811X0669Y0669R270S0
|
||||
317FPGA_JTAG_TDO JCD1 -61 D0449PA00X+081181Y-011811X0669Y0669R270S0
|
||||
317FPGA_JTAG_TMS JCD1 -62 D0449PA00X+081181Y-010811X0669Y0669R270S0
|
||||
317GND JCD1 -63 D0449PA00X+082181Y-011811X0669Y0669R270S0
|
||||
317GND JCD1 -64 D0449PA00X+082181Y-010811X0669Y0669R270S0
|
||||
327+3V3 C19 -1 A01X+068174Y-013228X0344Y0374R180S2
|
||||
327GND C19 -2 A01X+067554Y-013228X0344Y0374R180S2
|
||||
317GND J1 -1 D0354PA00X+089854Y-010827X0531Y0531R090S0
|
||||
317/B2B/JTAG_VIO J1 -2 D0354PA00X+089854Y-011614X0531Y0531R090S0
|
||||
317GND J1 -3 D0354PA00X+089067Y-010827X0531Y0531R090S0
|
||||
317FPGA_JTAG_TMS J1 -4 D0354PA00X+089067Y-011614X0531Y0531R090S0
|
||||
317GND J1 -5 D0354PA00X+088280Y-010827X0531Y0531R090S0
|
||||
317FPGA_JTAG_TCK J1 -6 D0354PA00X+088280Y-011614X0531Y0531R090S0
|
||||
317GND J1 -7 D0354PA00X+087492Y-010827X0531Y0531R090S0
|
||||
317FPGA_JTAG_TDO J1 -8 D0354PA00X+087492Y-011614X0531Y0531R090S0
|
||||
317GND J1 -9 D0354PA00X+086705Y-010827X0531Y0531R090S0
|
||||
317FPGA_JTAG_TDI J1 -10 D0354PA00X+086705Y-011614X0531Y0531R090S0
|
||||
317GND J1 -11 D0354PA00X+085917Y-010827X0531Y0531R090S0
|
||||
317NET-(J1-PAD12) J1 -12 D0354PA00X+085917Y-011614X0531Y0531R090S0
|
||||
317GND J1 -13 D0354PA00X+085130Y-010827X0531Y0531R090S0
|
||||
317NET-(J1-PAD14) J1 -14 D0354PA00X+085130Y-011614X0531Y0531R090S0
|
||||
327GND C17 -2 A01X+100558Y-035063X0344Y0374R000S2
|
||||
327+5V C17 -1 A01X+099938Y-035063X0344Y0374R000S2
|
||||
327/USB/VBUS C18 -1 A01X+099936Y-032071X0344Y0374R180S2
|
||||
327GND C18 -2 A01X+099316Y-032071X0344Y0374R180S2
|
||||
327/USB/VBUS_USB0 C16 -1 A01X+101894Y-034000X0492Y0689R180S2
|
||||
327GND C16 -2 A01X+100791Y-034000X0492Y0689R180S2
|
||||
327/USB/VBUS FB1 -1 A01X+101155Y-033098X0384Y0551R000S2
|
||||
327/USB/VBUS_USB0 FB1 -2 A01X+101893Y-033098X0384Y0551R000S2
|
||||
327/USB/VBUS U7 -1 A01X+099941Y-033114X0417Y0256R090S2
|
||||
327GND U7 -2 A01X+099567Y-033114X0417Y0256R090S2
|
||||
327/USB/USB_FLT U7 -3 A01X+099193Y-033114X0417Y0256R090S2
|
||||
327/USB/USB_EN U7 -4 A01X+099193Y-033980X0417Y0256R090S2
|
||||
327+5V U7 -5 A01X+099941Y-033980X0417Y0256R090S2
|
||||
327NET-(U6-PAD1) U6 -1 A01X+104921Y-031616X0417Y0256R180S2
|
||||
327GND U6 -2 A01X+104921Y-031242X0417Y0256R180S2
|
||||
327NET-(U6-PAD3) U6 -3 A01X+104921Y-030868X0417Y0256R180S2
|
||||
327/USB/USB_D+ U6 -4 A01X+104055Y-030868X0417Y0256R180S2
|
||||
327/USB/USB_D- U6 -6 A01X+104055Y-031616X0417Y0256R180S2
|
||||
327GND U6 -5 A01X+104055Y-031242X0417Y0256R180S2
|
||||
327USBH0_D+ R11 -2 A01X+103434Y-030142X0344Y0374R180S2
|
||||
327/USB/USB_D+ R11 -1 A01X+104054Y-030142X0344Y0374R180S2
|
||||
327/USB/USB_D- R12 -1 A01X+104054Y-032343X0344Y0374R180S2
|
||||
327USBH0_D- R12 -2 A01X+103434Y-032343X0344Y0374R180S2
|
||||
327GND R14 -2 A01X+102701Y-031540X0344Y0374R270S2
|
||||
327/USB/USB_D- R14 -1 A01X+102701Y-032160X0344Y0374R270S2
|
||||
327/USB/USB_EN R15 -1 A01X+098436Y-033980X0344Y0374R180S2
|
||||
327+5V R15 -2 A01X+097816Y-033980X0344Y0374R180S2
|
||||
327/USB/USB_D+ R13 -2 A01X+102701Y-030324X0344Y0374R270S2
|
||||
327GND R13 -1 A01X+102701Y-030944X0344Y0374R270S2
|
||||
327/USB/USB_FLT R16 -1 A01X+098436Y-033114X0344Y0374R180S2
|
||||
327+5V R16 -2 A01X+097816Y-033114X0344Y0374R180S2
|
||||
327GND D3 -1 A01X+057270Y-005651X0384Y0551R090S2
|
||||
327NET-(D3-PAD2) D3 -2 A01X+057270Y-006389X0384Y0551R090S2
|
||||
327NET-(D2-PAD2) D2 -2 A01X+056386Y-006389X0384Y0551R090S2
|
||||
327GND D2 -1 A01X+056386Y-005651X0384Y0551R090S2
|
||||
327NET-(D4-PAD2) D4 -2 A01X+058155Y-006389X0384Y0551R090S2
|
||||
327GND D4 -1 A01X+058155Y-005651X0384Y0551R090S2
|
||||
327GND D5 -1 A01X+059039Y-005651X0384Y0551R090S2
|
||||
327NET-(D5-PAD2) D5 -2 A01X+059039Y-006389X0384Y0551R090S2
|
||||
327NET-(D3-PAD2) R8 -2 A01X+057270Y-007123X0344Y0374R270S2
|
||||
327LED1 R8 -1 A01X+057270Y-007743X0344Y0374R270S2
|
||||
327LED0 R7 -1 A01X+056386Y-007743X0344Y0374R270S2
|
||||
327NET-(D2-PAD2) R7 -2 A01X+056386Y-007123X0344Y0374R270S2
|
||||
327NET-(D4-PAD2) R9 -2 A01X+058155Y-007123X0344Y0374R270S2
|
||||
327LED2 R9 -1 A01X+058155Y-007743X0344Y0374R270S2
|
||||
327LED3 R10 -1 A01X+059039Y-007743X0344Y0374R270S2
|
||||
327NET-(D5-PAD2) R10 -2 A01X+059039Y-007123X0344Y0374R270S2
|
||||
327GND C15 -2 A01X+103161Y-026519X0344Y0374R090S2
|
||||
327HDMI_5V C15 -1 A01X+103161Y-025899X0344Y0374R090S2
|
||||
327GND C14 -2 A01X+087539Y-020550X0344Y0374R090S2
|
||||
327+5V C14 -1 A01X+087539Y-019930X0344Y0374R090S2
|
||||
327+3V3 C13 -1 A01X+092240Y-017377X0344Y0374R270S2
|
||||
327GND C13 -2 A01X+092240Y-016757X0344Y0374R270S2
|
||||
327+3V3 C12 -1 A01X+093889Y-016756X0384Y0551R180S2
|
||||
327GND C12 -2 A01X+093151Y-016756X0384Y0551R180S2
|
||||
317SHIELD J5 -SH D0512PA00X+106614Y-027618X0787Y0000R270S0
|
||||
317SHIELD J5 -SH D0512PA00X+106614Y-021437X0787Y0000R270S0
|
||||
317SHIELD J5 -SH D0512PA00X+104665Y-027382X0787Y0000R270S0
|
||||
317SHIELD J5 -SH D0512PA00X+104665Y-021673X0787Y0000R270S0
|
||||
327/HDMI/HPD_B J5 -19 A01X+104311Y-026201X0118Y0748R270S2
|
||||
327HDMI_5V J5 -18 A01X+104311Y-026004X0118Y0748R270S2
|
||||
327GND J5 -17 A01X+104311Y-025807X0118Y0748R270S2
|
||||
327/HDMI/SDA_B J5 -16 A01X+104311Y-025610X0118Y0748R270S2
|
||||
327/HDMI/SCL_B J5 -15 A01X+104311Y-025413X0118Y0748R270S2
|
||||
327NET-(J5-PAD14) J5 -14 A01X+104311Y-025217X0118Y0748R270S2
|
||||
327/HDMI/CEC_B J5 -13 A01X+104311Y-025020X0118Y0748R270S2
|
||||
327HDMI_CLK- J5 -12 A01X+104311Y-024823X0118Y0748R270S2
|
||||
327GND J5 -11 A01X+104311Y-024626X0118Y0748R270S2
|
||||
327HDMI_CLK+ J5 -10 A01X+104311Y-024429X0118Y0748R270S2
|
||||
327HDMI_D0- J5 -9 A01X+104311Y-024232X0118Y0748R270S2
|
||||
327GND J5 -8 A01X+104311Y-024035X0118Y0748R270S2
|
||||
327HDMI_D0+ J5 -7 A01X+104311Y-023839X0118Y0748R270S2
|
||||
327HDMI_D1- J5 -6 A01X+104311Y-023642X0118Y0748R270S2
|
||||
327GND J5 -5 A01X+104311Y-023445X0118Y0748R270S2
|
||||
327HDMI_D1+ J5 -4 A01X+104311Y-023248X0118Y0748R270S2
|
||||
327HDMI_D2- J5 -3 A01X+104311Y-023051X0118Y0748R270S2
|
||||
327GND J5 -2 A01X+104311Y-022854X0118Y0748R270S2
|
||||
327HDMI_D2+ J5 -1 A01X+104311Y-022657X0118Y0748R270S2
|
||||
327HDMI_CEC_A U5 -1 A01X+089008Y-017372X0618Y0161R000S2
|
||||
327HDMI_SCL_A U5 -2 A01X+089008Y-017628X0618Y0161R000S2
|
||||
327HDMI_SDA_A U5 -3 A01X+089008Y-017884X0618Y0161R000S2
|
||||
327HDMI_HPD_A U5 -4 A01X+089008Y-018140X0618Y0161R000S2
|
||||
327+3V3 U5 -5 A01X+089008Y-018396X0618Y0161R000S2
|
||||
327GND U5 -6 A01X+089008Y-018652X0618Y0161R000S2
|
||||
327/HDMI/CEC_B U5 -7 A01X+089008Y-018907X0618Y0161R000S2
|
||||
327/HDMI/SCL_B U5 -8 A01X+089008Y-019163X0618Y0161R000S2
|
||||
327/HDMI/SDA_B U5 -9 A01X+089008Y-019419X0618Y0161R000S2
|
||||
327/HDMI/HPD_B U5 -10 A01X+089008Y-019675X0618Y0161R000S2
|
||||
327+5V U5 -11 A01X+089008Y-019931X0618Y0161R000S2
|
||||
327+3V3 U5 -12 A01X+089008Y-020187X0618Y0161R000S2
|
||||
327HDMI_5V U5 -13 A01X+091268Y-020187X0618Y0161R000S2
|
||||
327GND U5 -14 A01X+091268Y-019931X0618Y0161R000S2
|
||||
327HDMI_CLK- U5 -15 A01X+091268Y-019675X0618Y0161R000S2
|
||||
327HDMI_CLK+ U5 -16 A01X+091268Y-019419X0618Y0161R000S2
|
||||
327HDMI_D0- U5 -17 A01X+091268Y-019163X0618Y0161R000S2
|
||||
327HDMI_D0+ U5 -18 A01X+091268Y-018907X0618Y0161R000S2
|
||||
327GND U5 -19 A01X+091268Y-018652X0618Y0161R000S2
|
||||
327HDMI_D1- U5 -20 A01X+091268Y-018396X0618Y0161R000S2
|
||||
327HDMI_D1+ U5 -21 A01X+091268Y-018140X0618Y0161R000S2
|
||||
327HDMI_D2- U5 -22 A01X+091268Y-017884X0618Y0161R000S2
|
||||
327HDMI_D2+ U5 -23 A01X+091268Y-017628X0618Y0161R000S2
|
||||
327+3V3 U5 -24 A01X+091268Y-017372X0618Y0161R000S2
|
||||
317NET-(J4-PAD15) J4 -15 D0469PA00X+104150Y-015142X0591Y0000R270S0
|
||||
317/VGA/VGA_VS J4 -14 D0469PA00X+104150Y-014240X0591Y0000R270S0
|
||||
317/VGA/VGA_HS J4 -13 D0469PA00X+104150Y-013337X0591Y0000R270S0
|
||||
317NET-(J4-PAD12) J4 -12 D0469PA00X+104150Y-012437X0591Y0000R270S0
|
||||
317NET-(J4-PAD11) J4 -11 D0469PA00X+104150Y-011535X0591Y0000R270S0
|
||||
317GND J4 -10 D0469PA00X+103150Y-014693X0591Y0000R270S0
|
||||
317NET-(J4-PAD9) J4 -9 D0469PA00X+103150Y-013791X0591Y0000R270S0
|
||||
317GND J4 -8 D0469PA00X+103150Y-012890X0591Y0000R270S0
|
||||
317GND J4 -7 D0469PA00X+103150Y-011988X0591Y0000R270S0
|
||||
317GND J4 -6 D0469PA00X+103150Y-011087X0591Y0000R270S0
|
||||
317GND J4 -5 D0469PA00X+102150Y-015142X0591Y0000R270S0
|
||||
317NET-(J4-PAD4) J4 -4 D0469PA00X+102150Y-014240X0591Y0000R270S0
|
||||
317/VGA/VGA_B J4 -3 D0469PA00X+102150Y-013339X0591Y0000R270S0
|
||||
317/VGA/VGA_G J4 -2 D0469PA00X+102150Y-012437X0591Y0000R270S0
|
||||
317/VGA/VGA_R J4 -1 D0469PA00X+102150Y-011535X0591Y0000R270S0
|
||||
317SHIELD J4 -0 D1201PA00X+103150Y-008319X1378Y0000R270S0
|
||||
317SHIELD J4 -0 D1201PA00X+103150Y-018161X1378Y0000R270S0
|
||||
327GND C9 -2 A01X+094344Y-014913X0344Y0374R180S2
|
||||
327+3V3 C9 -1 A01X+094964Y-014913X0344Y0374R180S2
|
||||
327+3V3 C8 -1 A01X+099690Y-012992X0344Y0374R000S2
|
||||
327GND C8 -2 A01X+100310Y-012992X0344Y0374R000S2
|
||||
327GND C5 -2 A01X+097642Y-009532X0344Y0374R270S2
|
||||
327+3V3 C5 -1 A01X+097642Y-010153X0344Y0374R270S2
|
||||
327+3V3 C6 -1 A01X+094310Y-014165X0344Y0374R180S2
|
||||
327GND C6 -2 A01X+093690Y-014165X0344Y0374R180S2
|
||||
327+3V3 C7 -2 A01X+100310Y-011614X0344Y0374R000S2
|
||||
327/VGA/COMP C7 -1 A01X+099690Y-011614X0344Y0374R000S2
|
||||
327/VGA/VREF C10 -1 A01X+099426Y-010949X0344Y0374R000S2
|
||||
327GND C10 -2 A01X+100046Y-010949X0344Y0374R000S2
|
||||
317SHIELD C11 -1 D0315PA00X+099425Y-005268X0630Y0630R090S0
|
||||
317GND C11 -2 D0315PA00X+099425Y-006252X0630Y0000R090S0
|
||||
327FPGA_VGA_VS R6 -1 A01X+099655Y-014354X0344Y0374R000S2
|
||||
327/VGA/VGA_VS R6 -2 A01X+100275Y-014354X0344Y0374R000S2
|
||||
327GND R3 -2 A01X+098327Y-009532X0344Y0374R270S2
|
||||
327/VGA/RSET R3 -1 A01X+098327Y-010153X0344Y0374R270S2
|
||||
327FPGA_VGA_HS R5 -1 A01X+099658Y-013673X0344Y0374R000S2
|
||||
327/VGA/VGA_HS R5 -2 A01X+100279Y-013673X0344Y0374R000S2
|
||||
327SHIELD R4 -1 A01X+097173Y-005264X0492Y1043R090S2
|
||||
327GND R4 -2 A01X+097173Y-006366X0492Y1043R090S2
|
||||
367N/C J3 D1122UA00X+080740Y-040370X1122Y0000R180S0
|
||||
367N/C J3 D1122UA00X+045740Y-040370X1122Y0000R180S0
|
||||
317-12V J3 -a1 D0394PA00X+078740Y-039370X0610Y0610R180S0
|
||||
317SB0_5V J3 -a2 D0394PA00X+077740Y-039370X0610Y0000R180S0
|
||||
317~SPV_5V J3 -a3 D0394PA00X+076740Y-039370X0610Y0000R180S0
|
||||
317~SP_5V J3 -a4 D0394PA00X+075740Y-039370X0610Y0000R180S0
|
||||
317~TM1_5V J3 -a5 D0394PA00X+074740Y-039370X0610Y0000R180S0
|
||||
317~AD1_5V J3 -a6 D0394PA00X+073740Y-039370X0610Y0000R180S0
|
||||
317~AD3_5V J3 -a7 D0394PA00X+072740Y-039370X0610Y0000R180S0
|
||||
317~AD5_5V J3 -a8 D0394PA00X+071740Y-039370X0610Y0000R180S0
|
||||
317~AD7_5V J3 -a9 D0394PA00X+070740Y-039370X0610Y0000R180S0
|
||||
317~AD9_5V J3 -a10 D0394PA00X+069740Y-039370X0610Y0000R180S0
|
||||
317~AD11_5V J3 -a11 D0394PA00X+068740Y-039370X0610Y0000R180S0
|
||||
317~AD13_5V J3 -a12 D0394PA00X+067740Y-039370X0610Y0000R180S0
|
||||
317~AD15_5V J3 -a13 D0394PA00X+066740Y-039370X0610Y0000R180S0
|
||||
317~AD17_5V J3 -a14 D0394PA00X+065740Y-039370X0610Y0000R180S0
|
||||
317~AD19_5V J3 -a15 D0394PA00X+064740Y-039370X0610Y0000R180S0
|
||||
317~AD21_5V J3 -a16 D0394PA00X+063740Y-039370X0610Y0000R180S0
|
||||
317~AD23_5V J3 -a17 D0394PA00X+062740Y-039370X0610Y0000R180S0
|
||||
317~AD25_5V J3 -a18 D0394PA00X+061740Y-039370X0610Y0000R180S0
|
||||
317~AD27_5V J3 -a19 D0394PA00X+060740Y-039370X0610Y0000R180S0
|
||||
317~AD29_5V J3 -a20 D0394PA00X+059740Y-039370X0610Y0000R180S0
|
||||
317~AD31_5V J3 -a21 D0394PA00X+058740Y-039370X0610Y0000R180S0
|
||||
317GND J3 -a22 D0394PA00X+057740Y-039370X0610Y0000R180S0
|
||||
317GND J3 -a23 D0394PA00X+056740Y-039370X0610Y0000R180S0
|
||||
317~ARB1_5V J3 -a24 D0394PA00X+055740Y-039370X0610Y0000R180S0
|
||||
317~ARB3_5V J3 -a25 D0394PA00X+054740Y-039370X0610Y0000R180S0
|
||||
317~ID1_5V J3 -a26 D0394PA00X+053740Y-039370X0610Y0000R180S0
|
||||
317~ID3_5V J3 -a27 D0394PA00X+052740Y-039370X0610Y0000R180S0
|
||||
317~ACK_5V J3 -a28 D0394PA00X+051740Y-039370X0610Y0000R180S0
|
||||
317+5V J3 -a29 D0394PA00X+050740Y-039370X0610Y0000R180S0
|
||||
317~RQST_5V J3 -a30 D0394PA00X+049740Y-039370X0610Y0000R180S0
|
||||
317~NMRQ_5V J3 -a31 D0394PA00X+048740Y-039370X0610Y0000R180S0
|
||||
317+12V J3 -a32 D0394PA00X+047740Y-039370X0610Y0000R180S0
|
||||
317-12V J3 -b1 D0394PA00X+078740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b2 D0394PA00X+077740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b3 D0394PA00X+076740Y-038370X0610Y0000R180S0
|
||||
317+5V J3 -b4 D0394PA00X+075740Y-038370X0610Y0000R180S0
|
||||
317+5V J3 -b5 D0394PA00X+074740Y-038370X0610Y0000R180S0
|
||||
317+5V J3 -b6 D0394PA00X+073740Y-038370X0610Y0000R180S0
|
||||
317+5V J3 -b7 D0394PA00X+072740Y-038370X0610Y0000R180S0
|
||||
317~TM2_5V J3 -b8 D0394PA00X+071740Y-038370X0610Y0000R180S0
|
||||
317~CM0_5V J3 -b9 D0394PA00X+070740Y-038370X0610Y0000R180S0
|
||||
317~CM1_5V J3 -b10 D0394PA00X+069740Y-038370X0610Y0000R180S0
|
||||
317~CM2_5V J3 -b11 D0394PA00X+068740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b12 D0394PA00X+067740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b13 D0394PA00X+066740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b14 D0394PA00X+065740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b15 D0394PA00X+064740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b16 D0394PA00X+063740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b17 D0394PA00X+062740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b18 D0394PA00X+061740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b19 D0394PA00X+060740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b20 D0394PA00X+059740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b21 D0394PA00X+058740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b22 D0394PA00X+057740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b23 D0394PA00X+056740Y-038370X0610Y0000R180S0
|
||||
317~CLK2X_5V J3 -b24 D0394PA00X+055740Y-038370X0610Y0000R180S0
|
||||
317STDBYPWR J3 -b25 D0394PA00X+054740Y-038370X0610Y0000R180S0
|
||||
317~CLK2XEN_5V J3 -b26 D0394PA00X+053740Y-038370X0610Y0000R180S0
|
||||
317~CBUSY_5V J3 -b27 D0394PA00X+052740Y-038370X0610Y0000R180S0
|
||||
317+5V J3 -b28 D0394PA00X+051740Y-038370X0610Y0000R180S0
|
||||
317+5V J3 -b29 D0394PA00X+050740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b30 D0394PA00X+049740Y-038370X0610Y0000R180S0
|
||||
317GND J3 -b31 D0394PA00X+048740Y-038370X0610Y0000R180S0
|
||||
317+12V J3 -b32 D0394PA00X+047740Y-038370X0610Y0000R180S0
|
||||
317~RESET_5V J3 -c1 D0394PA00X+078740Y-037370X0610Y0000R180S0
|
||||
317SB1_5V J3 -c2 D0394PA00X+077740Y-037370X0610Y0000R180S0
|
||||
317+5V J3 -c3 D0394PA00X+076740Y-037370X0610Y0000R180S0
|
||||
317+5V J3 -c4 D0394PA00X+075740Y-037370X0610Y0000R180S0
|
||||
317~TM0_5V J3 -c5 D0394PA00X+074740Y-037370X0610Y0000R180S0
|
||||
317~AD0_5V J3 -c6 D0394PA00X+073740Y-037370X0610Y0000R180S0
|
||||
317~AD2_5V J3 -c7 D0394PA00X+072740Y-037370X0610Y0000R180S0
|
||||
317~AD4_5V J3 -c8 D0394PA00X+071740Y-037370X0610Y0000R180S0
|
||||
317~AD6_5V J3 -c9 D0394PA00X+070740Y-037370X0610Y0000R180S0
|
||||
317~AD8_5V J3 -c10 D0394PA00X+069740Y-037370X0610Y0000R180S0
|
||||
317~AD10_5V J3 -c11 D0394PA00X+068740Y-037370X0610Y0000R180S0
|
||||
317~AD12_5V J3 -c12 D0394PA00X+067740Y-037370X0610Y0000R180S0
|
||||
317~AD14_5V J3 -c13 D0394PA00X+066740Y-037370X0610Y0000R180S0
|
||||
317~AD16_5V J3 -c14 D0394PA00X+065740Y-037370X0610Y0000R180S0
|
||||
317~AD18_5V J3 -c15 D0394PA00X+064740Y-037370X0610Y0000R180S0
|
||||
317~AD20_5V J3 -c16 D0394PA00X+063740Y-037370X0610Y0000R180S0
|
||||
317~AD22_5V J3 -c17 D0394PA00X+062740Y-037370X0610Y0000R180S0
|
||||
317~AD24_5V J3 -c18 D0394PA00X+061740Y-037370X0610Y0000R180S0
|
||||
317~AD26_5V J3 -c19 D0394PA00X+060740Y-037370X0610Y0000R180S0
|
||||
317~AD28_5V J3 -c20 D0394PA00X+059740Y-037370X0610Y0000R180S0
|
||||
317~AD30_5V J3 -c21 D0394PA00X+058740Y-037370X0610Y0000R180S0
|
||||
317GND J3 -c22 D0394PA00X+057740Y-037370X0610Y0000R180S0
|
||||
317~PFW_5V J3 -c23 D0394PA00X+056740Y-037370X0610Y0000R180S0
|
||||
317~ARB0_5V J3 -c24 D0394PA00X+055740Y-037370X0610Y0000R180S0
|
||||
317~ARB2_5V J3 -c25 D0394PA00X+054740Y-037370X0610Y0000R180S0
|
||||
317~ID0_5V J3 -c26 D0394PA00X+053740Y-037370X0610Y0000R180S0
|
||||
317~ID2_5V J3 -c27 D0394PA00X+052740Y-037370X0610Y0000R180S0
|
||||
317~START_5V J3 -c28 D0394PA00X+051740Y-037370X0610Y0000R180S0
|
||||
317+5V J3 -c29 D0394PA00X+050740Y-037370X0610Y0000R180S0
|
||||
317+5V J3 -c30 D0394PA00X+049740Y-037370X0610Y0000R180S0
|
||||
317GND J3 -c31 D0394PA00X+048740Y-037370X0610Y0000R180S0
|
||||
317~CLK_5V J3 -c32 D0394PA00X+047740Y-037370X0610Y0000R180S0
|
||||
327GND C4 -2 A01X+065995Y-021953X0344Y0374R000S2
|
||||
327+3V3 C4 -1 A01X+065375Y-021953X0344Y0374R000S2
|
||||
327NUBUS_OE R2 -2 A01X+062879Y-028425X0344Y0374R180S2
|
||||
327+3V3 R2 -1 A01X+063499Y-028425X0344Y0374R180S2
|
||||
317NET-(J2-PAD6) J2 -6 D0402PA00X+047992Y-008189X0669Y0669R180S0
|
||||
317/B2B/TX J2 -5 D0402PA00X+047992Y-009189X0669Y0669R180S0
|
||||
317/B2B/RX J2 -4 D0402PA00X+047992Y-010189X0669Y0669R180S0
|
||||
317NET-(J2-PAD3) J2 -3 D0402PA00X+047992Y-011189X0669Y0669R180S0
|
||||
317NET-(J2-PAD2) J2 -2 D0402PA00X+047992Y-012189X0669Y0669R180S0
|
||||
317GND J2 -1 D0402PA00X+047992Y-013189X0669Y0669R180S0
|
||||
317GND JAB1 -64 D0449PA00X+082181Y-023311X0669Y0669R270S0
|
||||
317/B2B/JTAG_VIO JAB1 -63 D0449PA00X+082181Y-024311X0669Y0669R270S0
|
||||
317FPGA_JTAG_TCK JAB1 -62 D0449PA00X+081181Y-023311X0669Y0669R270S0
|
||||
317FPGA_JTAG_TDI JAB1 -61 D0449PA00X+081181Y-024311X0669Y0669R270S0
|
||||
317USBH0_D- JAB1 -60 D0449PA00X+080181Y-023311X0669Y0669R270S0
|
||||
317USBH0_D+ JAB1 -59 D0449PA00X+080181Y-024311X0669Y0669R270S0
|
||||
317~AD0_3V3 JAB1 -58 D0449PA00X+079181Y-023311X0669Y0669R270S0
|
||||
317~AD1_3V3 JAB1 -57 D0449PA00X+079181Y-024311X0669Y0669R270S0
|
||||
317~AD2_3V3 JAB1 -56 D0449PA00X+078181Y-023311X0669Y0669R270S0
|
||||
317~AD3_3V3 JAB1 -55 D0449PA00X+078181Y-024311X0669Y0669R270S0
|
||||
317~AD4_3V3 JAB1 -54 D0449PA00X+077181Y-023311X0669Y0669R270S0
|
||||
317~AD5_3V3 JAB1 -53 D0449PA00X+077181Y-024311X0669Y0669R270S0
|
||||
317~AD6_3V3 JAB1 -52 D0449PA00X+076181Y-023311X0669Y0669R270S0
|
||||
317~AD7_3V3 JAB1 -51 D0449PA00X+076181Y-024311X0669Y0669R270S0
|
||||
317~AD8_3V3 JAB1 -50 D0449PA00X+075181Y-023311X0669Y0669R270S0
|
||||
317~AD9_3V3 JAB1 -49 D0449PA00X+075181Y-024311X0669Y0669R270S0
|
||||
317~AD10_3V3 JAB1 -48 D0449PA00X+074181Y-023311X0669Y0669R270S0
|
||||
317~AD11_3V3 JAB1 -47 D0449PA00X+074181Y-024311X0669Y0669R270S0
|
||||
317~AD12_3V3 JAB1 -46 D0449PA00X+073181Y-023311X0669Y0669R270S0
|
||||
317~AD13_3V3 JAB1 -45 D0449PA00X+073181Y-024311X0669Y0669R270S0
|
||||
317~AD14_3V3 JAB1 -44 D0449PA00X+072181Y-023311X0669Y0669R270S0
|
||||
317~AD15_3V3 JAB1 -43 D0449PA00X+072181Y-024311X0669Y0669R270S0
|
||||
317~AD16_3V3 JAB1 -42 D0449PA00X+071181Y-023311X0669Y0669R270S0
|
||||
317~AD17_3V3 JAB1 -41 D0449PA00X+071181Y-024311X0669Y0669R270S0
|
||||
317~AD18_3V3 JAB1 -40 D0449PA00X+070181Y-023311X0669Y0669R270S0
|
||||
317~AD19_3V3 JAB1 -39 D0449PA00X+070181Y-024311X0669Y0669R270S0
|
||||
317~AD20_3V3 JAB1 -38 D0449PA00X+069181Y-023311X0669Y0669R270S0
|
||||
317~AD21_3V3 JAB1 -37 D0449PA00X+069181Y-024311X0669Y0669R270S0
|
||||
317~AD22_3V3 JAB1 -36 D0449PA00X+068181Y-023311X0669Y0669R270S0
|
||||
317~AD23_3V3 JAB1 -35 D0449PA00X+068181Y-024311X0669Y0669R270S0
|
||||
317+3V3 JAB1 -34 D0449PA00X+067181Y-023311X0669Y0669R270S0
|
||||
317+3V3 JAB1 -33 D0449PA00X+067181Y-024311X0669Y0669R270S0
|
||||
317GND JAB1 -32 D0449PA00X+066181Y-023311X0669Y0669R270S0
|
||||
317GND JAB1 -31 D0449PA00X+066181Y-024311X0669Y0669R270S0
|
||||
317+3V3 JAB1 -30 D0449PA00X+065181Y-023311X0669Y0669R270S0
|
||||
317+3V3 JAB1 -29 D0449PA00X+065181Y-024311X0669Y0669R270S0
|
||||
317~AD24_3V3 JAB1 -28 D0449PA00X+064181Y-023311X0669Y0669R270S0
|
||||
317NUBUS_OE JAB1 -27 D0449PA00X+064181Y-024311X0669Y0669R270S0
|
||||
317~AD26_3V3 JAB1 -26 D0449PA00X+063181Y-023311X0669Y0669R270S0
|
||||
317~AD25_3V3 JAB1 -25 D0449PA00X+063181Y-024311X0669Y0669R270S0
|
||||
317~AD28_3V3 JAB1 -24 D0449PA00X+062181Y-023311X0669Y0669R270S0
|
||||
317~AD27_3V3 JAB1 -23 D0449PA00X+062181Y-024311X0669Y0669R270S0
|
||||
317~AD30_3V3 JAB1 -22 D0449PA00X+061181Y-023311X0669Y0669R270S0
|
||||
317~AD29_3V3 JAB1 -21 D0449PA00X+061181Y-024311X0669Y0669R270S0
|
||||
317~CLK_3V3 JAB1 -20 D0449PA00X+060181Y-023311X0669Y0669R270S0
|
||||
317~AD31_3V3 JAB1 -19 D0449PA00X+060181Y-024311X0669Y0669R270S0
|
||||
317NUBUS_AD_DIR JAB1 -18 D0449PA00X+059181Y-023311X0669Y0669R270S0
|
||||
317~RESET_3V3 JAB1 -17 D0449PA00X+059181Y-024311X0669Y0669R270S0
|
||||
317_CPLD_SIGNAL_2 JAB1 -16 D0449PA00X+058181Y-023311X0669Y0669R270S0
|
||||
317BUS_MASTER_DIR JAB1 -15 D0449PA00X+058181Y-024311X0669Y0669R270S0
|
||||
317GA_TO_CPLD_CLK JAB1 -14 D0449PA00X+057181Y-023311X0669Y0669R270S0
|
||||
317TO_CPLD_SIGNAL JAB1 -13 D0449PA00X+057181Y-024311X0669Y0669R270S0
|
||||
317ARB JAB1 -12 D0449PA00X+056181Y-023311X0669Y0669R270S0
|
||||
317GRANT JAB1 -11 D0449PA00X+056181Y-024311X0669Y0669R270S0
|
||||
317~ACK_3V3 JAB1 -10 D0449PA00X+055181Y-023311X0669Y0669R270S0
|
||||
317~START_3V3 JAB1 -9 D0449PA00X+055181Y-024311X0669Y0669R270S0
|
||||
317~TM1_3V3 JAB1 -8 D0449PA00X+054181Y-023311X0669Y0669R270S0
|
||||
317~TM0_3V3 JAB1 -7 D0449PA00X+054181Y-024311X0669Y0669R270S0
|
||||
317~NMRQ_3V3 JAB1 -6 D0449PA00X+053181Y-023311X0669Y0669R270S0
|
||||
317~RQST_3V3 JAB1 -5 D0449PA00X+053181Y-024311X0669Y0669R270S0
|
||||
317GND JAB1 -4 D0449PA00X+052181Y-023311X0669Y0669R270S0
|
||||
317GND JAB1 -3 D0449PA00X+052181Y-024311X0669Y0669R270S0
|
||||
317+5V JAB1 -2 D0449PA00X+051181Y-023311X0669Y0669R270S0
|
||||
317+5V JAB1 -1 D0449PA00X+051181Y-024311X0669Y0669R270S0
|
||||
999
|
6989
nubus-to-ztex/nubus-to-ztex.dsn
Normal file
6989
nubus-to-ztex/nubus-to-ztex.dsn
Normal file
File diff suppressed because it is too large
Load Diff
11655
nubus-to-ztex/nubus-to-ztex.kicad_pcb
Normal file
11655
nubus-to-ztex/nubus-to-ztex.kicad_pcb
Normal file
File diff suppressed because it is too large
Load Diff
11655
nubus-to-ztex/nubus-to-ztex.kicad_pcb-bak
Normal file
11655
nubus-to-ztex/nubus-to-ztex.kicad_pcb-bak
Normal file
File diff suppressed because it is too large
Load Diff
2631
nubus-to-ztex/nubus-to-ztex.net
Normal file
2631
nubus-to-ztex/nubus-to-ztex.net
Normal file
File diff suppressed because it is too large
Load Diff
33
nubus-to-ztex/nubus-to-ztex.pro
Normal file
33
nubus-to-ztex/nubus-to-ztex.pro
Normal file
|
@ -0,0 +1,33 @@
|
|||
update=22/05/2015 07:44:53
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[pcbnew]
|
||||
version=1
|
||||
LastNetListRead=
|
||||
UseCmpFile=1
|
||||
PadDrill=0.600000000000
|
||||
PadDrillOvalY=0.600000000000
|
||||
PadSizeH=1.500000000000
|
||||
PadSizeV=1.500000000000
|
||||
PcbTextSizeV=1.500000000000
|
||||
PcbTextSizeH=1.500000000000
|
||||
PcbTextThickness=0.300000000000
|
||||
ModuleTextSizeV=1.000000000000
|
||||
ModuleTextSizeH=1.000000000000
|
||||
ModuleTextSizeThickness=0.150000000000
|
||||
SolderMaskClearance=0.000000000000
|
||||
SolderMaskMinWidth=0.000000000000
|
||||
DrawSegmentWidth=0.200000000000
|
||||
BoardOutlineThickness=0.100000000000
|
||||
ModuleOutlineThickness=0.150000000000
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
4737
nubus-to-ztex/nubus-to-ztex.rpt
Normal file
4737
nubus-to-ztex/nubus-to-ztex.rpt
Normal file
File diff suppressed because it is too large
Load Diff
121
nubus-to-ztex/nubus-to-ztex.rules
Normal file
121
nubus-to-ztex/nubus-to-ztex.rules
Normal file
|
@ -0,0 +1,121 @@
|
|||
|
||||
(rules PCB nubus-to-ztex
|
||||
(snap_angle
|
||||
fortyfive_degree
|
||||
)
|
||||
(autoroute_settings
|
||||
(fanout on)
|
||||
(autoroute on)
|
||||
(postroute on)
|
||||
(vias on)
|
||||
(via_costs 50)
|
||||
(plane_via_costs 5)
|
||||
(start_ripup_costs 100)
|
||||
(start_pass_no 2771)
|
||||
(layer_rule F.Cu
|
||||
(active on)
|
||||
(preferred_direction horizontal)
|
||||
(preferred_direction_trace_costs 1.0)
|
||||
(against_preferred_direction_trace_costs 1.0)
|
||||
)
|
||||
(layer_rule In1.Cu
|
||||
(active on)
|
||||
(preferred_direction vertical)
|
||||
(preferred_direction_trace_costs 1.1)
|
||||
(against_preferred_direction_trace_costs 1.1)
|
||||
)
|
||||
(layer_rule In2.Cu
|
||||
(active on)
|
||||
(preferred_direction horizontal)
|
||||
(preferred_direction_trace_costs 1.1)
|
||||
(against_preferred_direction_trace_costs 1.1)
|
||||
)
|
||||
(layer_rule B.Cu
|
||||
(active on)
|
||||
(preferred_direction vertical)
|
||||
(preferred_direction_trace_costs 1.0)
|
||||
(against_preferred_direction_trace_costs 1.0)
|
||||
)
|
||||
)
|
||||
(rule
|
||||
(width 152.4)
|
||||
(clear 152.6)
|
||||
(clear 76.2 (type smd_to_turn_gap))
|
||||
(clear 38.2 (type smd_smd))
|
||||
)
|
||||
(padstack "Via[0-3]_800:400_um"
|
||||
(shape
|
||||
(circle F.Cu 800.0 0.0 0.0)
|
||||
)
|
||||
(shape
|
||||
(circle In1.Cu 800.0 0.0 0.0)
|
||||
)
|
||||
(shape
|
||||
(circle In2.Cu 800.0 0.0 0.0)
|
||||
)
|
||||
(shape
|
||||
(circle B.Cu 800.0 0.0 0.0)
|
||||
)
|
||||
(attach off)
|
||||
)
|
||||
(via
|
||||
"Via[0-3]_800:400_um" "Via[0-3]_800:400_um" default
|
||||
)
|
||||
(via
|
||||
"Via[0-3]_800:400_um-kicad_default" "Via[0-3]_800:400_um" "kicad_default"
|
||||
)
|
||||
(via_rule
|
||||
default "Via[0-3]_800:400_um"
|
||||
)
|
||||
(via_rule
|
||||
"kicad_default" "Via[0-3]_800:400_um-kicad_default"
|
||||
)
|
||||
(class default
|
||||
(clearance_class default)
|
||||
(via_rule default)
|
||||
(rule
|
||||
(width 152.4)
|
||||
)
|
||||
(circuit
|
||||
(use_layer F.Cu In1.Cu In2.Cu B.Cu)
|
||||
)
|
||||
)
|
||||
(class "kicad_default"
|
||||
GND +3V3 "/B2B/JTAG_VIO" "/B2B/JTAG_TCK" "/B2B/JTAG_TDI" +5V "Net-(JCD1-Pad1)" "Net-(JCD1-Pad2)"
|
||||
/B2B/RX /B2B/TX "/B2B/JTAG_TDO" "/B2B/JTAG_TMS" "Net-(J1-Pad14)" "Net-(J1-Pad12)" "Net-(J2-Pad6)" "Net-(J2-Pad3)"
|
||||
"Net-(J2-Pad2)" "Net-(U1-Pad1)" "Net-(U2-Pad1)" "NUBUS_OE" "Net-(U2-Pad47)" "Net-(U2-Pad46)" "Net-(U2-Pad10)" "Net-(U2-Pad9)"
|
||||
"-12V" "SB0_5V" "~RESET_5V" "~SPV_5V" "~SP_5V" "~TM1_5V" "~AD1_5V" "~AD3_5V"
|
||||
"~AD5_5V" "~AD7_5V" "~AD9_5V" "~AD11_5V" "~AD13_5V" "~AD15_5V" "~AD17_5V" "~AD19_5V"
|
||||
"~AD21_5V" "~AD23_5V" "~AD25_5V" "~AD27_5V" "~AD29_5V" "~AD31_5V" "~ARB1_5V" "~ARB3_5V"
|
||||
"~ID1_5V" "~ID3_5V" "~ACK_5V" "~RQST_5V" "~NMRQ_5V" +12V "~TM2_5V" "~CM0_5V"
|
||||
"~CM1_5V" "~CM2_5V" STDBYPWR "~CLK2XEN_5V" "~CBUSY_5V" "SB1_5V" "~TM0_5V" "~AD0_5V"
|
||||
"~AD2_5V" "~AD4_5V" "~AD6_5V" "~AD8_5V" "~AD10_5V" "~AD12_5V" "~AD14_5V" "~AD16_5V"
|
||||
"~AD18_5V" "~AD20_5V" "~AD22_5V" "~AD24_5V" "~AD26_5V" "~AD28_5V" "~AD30_5V" "~PFW_5V"
|
||||
"~ARB0_5V" "~ARB2_5V" "~ID0_5V" "~ID2_5V" "~START_5V" "~CLK_5V" "~ID3_3V3" "~ID2_3V3"
|
||||
"~ID1_3V3" "~ID0_3V3" "~CLK_3V3" "~NMRQ_3V3" "~RQST_3V3" "~CLK2X_3V3" "~CLK2X_5V" "~START_3V3"
|
||||
"~ACK_3V3" "~ARB2_3V3" "~ARB3_3V3" "~ARB0_3V3" "~ARB1_3V3" "~AD31_3V3" "~AD30_3V3" "~AD29_3V3"
|
||||
"~AD28_3V3" "~AD27_3V3" "~AD26_3V3" "~AD25_3V3" "~AD24_3V3" "~AD23_3V3" "~AD22_3V3" "~AD21_3V3"
|
||||
"~AD20_3V3" "~RESET_3V3" "~TM0_3V3" "~TM1_3V3" "~TM2_3V3" "~AD0_3V3" "~AD1_3V3" "~AD2_3V3"
|
||||
"~AD3_3V3" "~AD4_3V3" "~AD5_3V3" "~AD6_3V3" "~AD7_3V3" "~AD9_3V3" "~AD8_3V3" "~AD11_3V3"
|
||||
"~AD10_3V3" "~AD13_3V3" "~AD12_3V3" "~AD15_3V3" "~AD14_3V3" "~AD17_3V3" "~AD16_3V3" "~AD19_3V3"
|
||||
"~AD18_3V3" "FPGA_VGA_HS" "/vga/VGA_HS" "Net-(R3-Pad1)" "FPGA_VGA_VS" "/vga/VGA_VS" "FPGA_G0" "FPGA_G1"
|
||||
"FPGA_G2" "FPGA_G3" "FPGA_G4" "FPGA_G5" "FPGA_G6" "FPGA_G7" "FPGA_B0" "FPGA_B1"
|
||||
"FPGA_B2" "FPGA_B3" "FPGA_B4" "FPGA_B5" "FPGA_B6" "FPGA_B7" "FPGA_VGA_CLK" "Net-(U4-Pad27)"
|
||||
"/vga/VGA_B" "Net-(U4-Pad31)" "/vga/VGA_G" "Net-(U4-Pad33)" "/vga/VGA_R" "Net-(C7-Pad1)" "Net-(C10-Pad1)" "FPGA_R0"
|
||||
"FPGA_R1" "FPGA_R2" "FPGA_R3" "FPGA_R4" "FPGA_R5" "FPGA_R6" "FPGA_R7" "Net-(J4-Pad15)"
|
||||
"Net-(J4-Pad12)" "Net-(J4-Pad11)" "Net-(J4-Pad9)" "Net-(J4-Pad4)" "/usb/USB_FLT" "/usb/USB_D-" "/usb/USB_EN" "/usb/USB_D+"
|
||||
"USBH0_D-" "USBH0_D+" LED0 "Net-(D1-Pad2)" "Net-(U5-Pad1)" "Net-(U5-Pad3)" /usb/VBus "/usb/VBus_USB0"
|
||||
SHIELD "SD_D2" "SD_D3" "SD_CMD" "SD_CLK" "SD_D0" "SD_D1" LED2
|
||||
"Net-(D7-Pad2)" LED8 "Net-(D9-Pad2)" LED1 "Net-(D8-Pad2)" "Net-(D6-Pad2)" LED3 LED4
|
||||
"Net-(D5-Pad2)" "Net-(D4-Pad2)" LED5 LED6 "Net-(D3-Pad2)" "Net-(D2-Pad2)" LED7 "Net-(JCD1-Pad27)"
|
||||
"I2C0_SCL" "I2C0_SDA" "Net-(U7-Pad3)" "Net-(U7-Pad5)" "Net-(U7-Pad6)" "Net-(U8-Pad5)" "Net-(U8-Pad3)"
|
||||
(clearance_class "kicad_default")
|
||||
(via_rule kicad_default)
|
||||
(rule
|
||||
(width 152.4)
|
||||
)
|
||||
(circuit
|
||||
(use_layer F.Cu In1.Cu In2.Cu B.Cu)
|
||||
)
|
||||
)
|
||||
)
|
53
nubus-to-ztex/nubus-to-ztex.sch
Normal file
53
nubus-to-ztex/nubus-to-ztex.sch
Normal file
|
@ -0,0 +1,53 @@
|
|||
EESchema Schematic File Version 4
|
||||
LIBS:nubus-to-ztex-cache
|
||||
EELAYER 26 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 1 7
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Sheet
|
||||
S 2250 1150 1000 500
|
||||
U 618E8C75
|
||||
F0 "B2B" 50
|
||||
F1 "B2B.sch" 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 1000 1150 1000 500
|
||||
U 618F532C
|
||||
F0 "nubus" 50
|
||||
F1 "nubus.sch" 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 2250 1850 1000 500
|
||||
U 61B62C00
|
||||
F0 "hdmi" 50
|
||||
F1 "hdmi.sch" 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 1000 2550 1000 500
|
||||
U 61B604DE
|
||||
F0 "usb" 50
|
||||
F1 "usb.sch" 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 2250 2550 1000 500
|
||||
U 61B99D2C
|
||||
F0 "fan" 50
|
||||
F1 "fan.sch" 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 1000 1850 1000 500
|
||||
U 6193AB43
|
||||
F0 "vga" 50
|
||||
F1 "vga.sch" 50
|
||||
$EndSheet
|
||||
$EndSCHEMATC
|
5614
nubus-to-ztex/nubus-to-ztex.ses
Normal file
5614
nubus-to-ztex/nubus-to-ztex.ses
Normal file
File diff suppressed because it is too large
Load Diff
3155
nubus-to-ztex/nubus-to-ztex.xml
Normal file
3155
nubus-to-ztex/nubus-to-ztex.xml
Normal file
File diff suppressed because it is too large
Load Diff
BIN
nubus-to-ztex/nubus-to-ztex.zip
Normal file
BIN
nubus-to-ztex/nubus-to-ztex.zip
Normal file
Binary file not shown.
1574
nubus-to-ztex/nubus.sch
Normal file
1574
nubus-to-ztex/nubus.sch
Normal file
File diff suppressed because it is too large
Load Diff
31
nubus-to-ztex/pkg.sh
Executable file
31
nubus-to-ztex/pkg.sh
Executable file
|
@ -0,0 +1,31 @@
|
|||
#!/bin/bash
|
||||
|
||||
GERBER_FILES="nubus-to-ztex-B.Cu.gbr nubus-to-ztex-Edge.Cuts.gbr nubus-to-ztex-F.Cu.gbr nubus-to-ztex-F.Mask.gbr nubus-to-ztex-F.Paste.gbr nubus-to-ztex-F.SilkS.gbr nubus-to-ztex-In1.Cu.gbr nubus-to-ztex-In2.Cu.gbr"
|
||||
|
||||
# nubus-to-ztex-B.Mask.gbr nubus-to-ztex-B.Paste.gbr nubus-to-ztex-B.SilkS.gbr
|
||||
|
||||
POS_FILES="nubus-to-ztex-top.pos"
|
||||
# nubus-to-ztex-bottom.pos
|
||||
|
||||
DRL_FILES="nubus-to-ztex-NPTH.drl nubus-to-ztex-PTH.drl nubus-to-ztex-PTH-drl_map.ps nubus-to-ztex-NPTH-drl_map.ps"
|
||||
|
||||
FILES="${GERBER_FILES} ${POS_FILES} ${DRL_FILES} top.pdf nubus-to-ztex.d356 nubus-to-ztex.csv"
|
||||
# bottom.pdf
|
||||
|
||||
echo $FILES
|
||||
|
||||
KICAD_PCB=nubus-to-ztex.kicad_pcb
|
||||
|
||||
ABORT=no
|
||||
for F in $FILES; do
|
||||
if test \! -f $F || test $KICAD_PCB -nt $F; then
|
||||
echo "Regenerate file $F"
|
||||
ABORT=yes
|
||||
fi
|
||||
done
|
||||
|
||||
if test $ABORT == "yes"; then
|
||||
exit -1;
|
||||
fi
|
||||
|
||||
zip nubus-to-ztex.zip $FILES top.jpg bottom.jpg
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user