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https://github.com/rdolbeau/NuBusFPGA.git
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pingmaster sort-of-work
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parent
3a52ab666f
commit
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@ -5,22 +5,29 @@ import litex
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import wishbone
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class PingMaster(Module):
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class PingMaster(Module):
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def __init__(self):
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def __init__(self, platform):
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self.bus_slv = bus_slv = wishbone.Interface()
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self.bus_slv = bus_slv = wishbone.Interface()
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self.bus_mst = bus_mst = wishbone.Interface()
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self.bus_mst = bus_mst = wishbone.Interface()
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led0 = platform.request("user_led", 0)
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led1 = platform.request("user_led", 1)
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valu_reg = Signal(32)
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valu_reg = Signal(32)
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addr_reg = Signal(32)
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addr_reg = Signal(32)
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writ_del = Signal(6)
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writ_del = Signal(6)
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addr_reg_rev = Signal(32)
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do_write = Signal()
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#addr_reg_rev = Signal(32)
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#self.comb += [ addr_reg_rev[ 0: 8].eq(addr_reg[24:32]),
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# addr_reg_rev[ 8:16].eq(addr_reg[16:24]),
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# addr_reg_rev[16:24].eq(addr_reg[ 8:16]),
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# addr_reg_rev[24:32].eq(addr_reg[ 0: 8]), ]
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self.comb += [ addr_reg_rev[ 0: 8].eq(addr_reg[24:32]),
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self.sync += [ If(writ_del != 0,
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addr_reg_rev[ 8:16].eq(addr_reg[16:24]),
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writ_del.eq(writ_del - 1),),
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addr_reg_rev[16:24].eq(addr_reg[ 8:16]),
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If(writ_del == 1,
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addr_reg_rev[24:32].eq(addr_reg[ 0: 8]), ]
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do_write.eq(1),
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)
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self.sync += If(writ_del != 0,
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]
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writ_del.eq(writ_del - 1))
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self.submodules.wishbone_fsm = wishbone_fsm = FSM(reset_state = "Reset")
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self.submodules.wishbone_fsm = wishbone_fsm = FSM(reset_state = "Reset")
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wishbone_fsm.act("Reset",
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wishbone_fsm.act("Reset",
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@ -32,7 +39,7 @@ class PingMaster(Module):
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Case(bus_slv.adr[0:1], {
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Case(bus_slv.adr[0:1], {
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0x0: [ NextValue(valu_reg, bus_slv.dat_w[0:32]), ],
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0x0: [ NextValue(valu_reg, bus_slv.dat_w[0:32]), ],
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0x1: [ NextValue(addr_reg, bus_slv.dat_w[0:32]),
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0x1: [ NextValue(addr_reg, bus_slv.dat_w[0:32]),
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NextValue(writ_del, 3), ],
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NextValue(writ_del, 63), ],
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}),
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}),
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NextValue(bus_slv.ack, 1),
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NextValue(bus_slv.ack, 1),
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).Elif(bus_slv.cyc & bus_slv.stb & ~bus_slv.we & ~bus_slv.ack, #read
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).Elif(bus_slv.cyc & bus_slv.stb & ~bus_slv.we & ~bus_slv.ack, #read
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@ -43,11 +50,17 @@ class PingMaster(Module):
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NextValue(bus_slv.ack, 1),
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NextValue(bus_slv.ack, 1),
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).Else(
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).Else(
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NextValue(bus_slv.ack, 0),
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NextValue(bus_slv.ack, 0),
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),
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If(writ_del == 1,
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NextState("Write"),),
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)
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)
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wishbone_fsm.act("Write",
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)
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self.submodules.writer_fsm = writer_fsm = FSM(reset_state = "Reset")
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writer_fsm.act("Reset",
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NextState("Idle"),)
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writer_fsm.act("Idle",
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If(do_write,
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NextValue(do_write, 0),
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NextState("Write"),),)
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writer_fsm.act("Write",
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bus_mst.cyc.eq(1),
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bus_mst.cyc.eq(1),
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bus_mst.stb.eq(1),
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bus_mst.stb.eq(1),
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bus_mst.we.eq(1),
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bus_mst.we.eq(1),
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@ -58,4 +71,5 @@ class PingMaster(Module):
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NextState("Idle")),
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NextState("Idle")),
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)
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)
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self.comb += [ led0.eq(bus_mst.cyc),
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led1.eq(writ_del != 0), ]
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@ -59,10 +59,10 @@ class NuBus2WishboneFIFO(Module):
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self.comb += nubus.mem_error.eq(0) # FIXME: TODO: ???
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self.comb += nubus.mem_error.eq(0) # FIXME: TODO: ???
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self.comb += nubus.mem_tryagain.eq(0) # FIXME: TODO: ???
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self.comb += nubus.mem_tryagain.eq(0) # FIXME: TODO: ???
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led0 = platform.request("user_led", 0)
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#led0 = platform.request("user_led", 0)
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led1 = platform.request("user_led", 1)
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#led1 = platform.request("user_led", 1)
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self.comb += [ led0.eq(wb_read.ack),
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#self.comb += [ led0.eq(wb_read.ack),
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led1.eq(write_ack), ]
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# led1.eq(write_ack), ]
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#self.submodules.write_fsm = write_fsm = FSM(reset_state = "Reset")
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#self.submodules.write_fsm = write_fsm = FSM(reset_state = "Reset")
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#write_fsm.act("Reset",
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#write_fsm.act("Reset",
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@ -255,8 +255,8 @@ class NuBusFPGA(SoCCore):
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"goblin_accel" : 0xF0901000, # accel for goblin (regs)
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"goblin_accel" : 0xF0901000, # accel for goblin (regs)
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"goblin_accel_ram" : 0xF0902000, # accel for goblin (scratch ram)
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"goblin_accel_ram" : 0xF0902000, # accel for goblin (scratch ram)
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"goblin_accel_rom" : 0xF0910000, # accel for goblin (rom)
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"goblin_accel_rom" : 0xF0910000, # accel for goblin (rom)
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"csr" : 0xF0a00000, # CSR
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"csr" : 0xF0A00000, # CSR
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"pingmaster": 0xF0b00000,
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"pingmaster": 0xF0B00000,
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"rom": 0xF0FF8000, # ROM at the end (32 KiB of it ATM)
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"rom": 0xF0FF8000, # ROM at the end (32 KiB of it ATM)
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#"END OF SLOT SPACE": 0xF0FFFFFF,
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#"END OF SLOT SPACE": 0xF0FFFFFF,
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}
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}
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@ -387,10 +387,10 @@ class NuBusFPGA(SoCCore):
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self.add_ram("goblin_accel_ram", origin=self.mem_map["goblin_accel_ram"], size=2**12, mode="rw")
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self.add_ram("goblin_accel_ram", origin=self.mem_map["goblin_accel_ram"], size=2**12, mode="rw")
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# for testing
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# for testing
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#from nubus_master_tst import PingMaster
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from nubus_master_tst import PingMaster
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#self.submodules.pingmaster = PingMaster()
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self.submodules.pingmaster = PingMaster(platform=self.platform)
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#self.bus.add_slave("pingmaster_slv", self.pingmaster.bus_slv, SoCRegion(origin=self.mem_map.get("pingmaster", None), size=0x010, cached=False))
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self.bus.add_slave("pingmaster_slv", self.pingmaster.bus_slv, SoCRegion(origin=self.mem_map.get("pingmaster", None), size=0x010, cached=False))
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#self.bus.add_master(name="pingmaster_mst", master=self.pingmaster.bus_mst)
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self.bus.add_master(name="pingmaster_mst", master=self.pingmaster.bus_mst)
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def main():
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def main():
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parser = argparse.ArgumentParser(description="SbusFPGA")
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parser = argparse.ArgumentParser(description="SbusFPGA")
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