Macintosh-HW/NuBusFPGA
1
0
Fork 0
mirror of https://github.com/rdolbeau/NuBusFPGA.git synced 2024-11-19 08:31:46 +00:00
Code Issues Projects Releases Wiki Activity

better goblin (+accel) in SBus

Browse Source
This commit is contained in:
Romain Dolbeau 2022-08-15 10:20:56 +02:00
parent d7968d9c48
commit 71d88bfb61
6 changed files with 54 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

0
nubus-to-ztex-gateware/VexRiscv_FbAccel.v → nubus-to-ztex-gateware/VexRiscv_GoblinAccel_NuBus.v
View File

9
nubus-to-ztex-gateware/blit_goblin.c
View File

@ -221,7 +221,14 @@ void from_reset(void) {
struct goblin_bt_regs* fbt = (struct goblin_bt_regs*)BASE_BT_REGS;
unsigned int cmd = fbc->reg_r5_cmd;
uint32_t srcx, wi, dstx;
switch ((fbt->mode>>24) & 0xFF) { // mode is 8 bits wrong-endian (all fbt is wrong-endian)
#if defined(GOBLIN_NUBUS)
switch ((fbt->mode>>24) & 0xFF) // mode is 8 bits wrong-endian (all fbt is wrong-endian in NuBus version)
#elif defined(GOBLIN_SBUS)
switch (fbt->mode & 0xFF)
#else
#error "Must define GOBLIN_NUBUS or GOBLIN_SBUS"
#endif
{
case mode_32bit:
srcx = fbc->reg_bitblt_src_x << 2;
wi = fbc->reg_width << 2;

6
nubus-to-ztex-gateware/blit_goblin_sbus.lds Normal file
View File

@ -0,0 +1,6 @@
OUTPUT_ARCH( "riscv" )
SECTIONS
{
. = 0x00410000;
.text : { *(.text) }
}

28
nubus-to-ztex-gateware/blit_goblin_sbus.sh Executable file
View File

@ -0,0 +1,28 @@
#!/bin/bash -x
BASE_FB=${1:-0x8F000000}
GCCDIR=~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14
GCCPFX=riscv64-unknown-elf-
GCCLINK=${GCCDIR}/bin/${GCCPFX}gcc
#GCCDIR=/opt/rv32bk
#GCCPFX=riscv32-buildroot-linux-gnu-
GCCDIR=~dolbeau2/LITEX/buildroot-rv32/output/host
GCCPFX=riscv32-buildroot-linux-gnu-
GCC=${GCCDIR}/bin/${GCCPFX}gcc
OBJCOPY=${GCCDIR}/bin/${GCCPFX}objcopy
OPT=-O3 #-fno-inline
ARCH=rv32im_zba_zbb_zbt
PARAM="-DBASE_FB=${BASE_FB} -DGOBLIN_SBUS"
if test "x$1" != "xASM"; then
$GCC $OPT -S -o blit_goblin.s $PARAM -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit_goblin.c
fi
$GCC $OPT -c -o blit_goblin.o $PARAM -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit_goblin.s &&
$GCCLINK $OPT -o blit_goblin $PARAM -march=$ARCH -mabi=ilp32 -T blit_goblin_sbus.lds -nostartfiles blit_goblin.o &&
$OBJCOPY -O binary -j .text -j .rodata blit_goblin blit_goblin.raw

16
nubus-to-ztex-gateware/goblin_accel.py
View File

@ -134,7 +134,7 @@ class GoblinAccel(Module): # AutoCSR ?
FUN_PATT_BIT = 2
FUN_TEST_BIT = 3
# to hold the Vex in reset
local_reset = Signal(reset = 1)
self.local_reset = local_reset = Signal(reset = 1)
self.sync += [
If(reg_r5_cmd[FUN_DONE_BIT],
@ -168,9 +168,7 @@ class GoblinAccel(Module): # AutoCSR ?
#timeout.eq(timeout_rst),
)
]
#led0 = platform.request("user_led", 0)
#self.comb += led0.eq(~local_reset) # Vex connection to the primary bus
self.ibus = ibus = wishbone.Interface()
#self.dbus = dbus = wishbone.Interface()
vex_reset = Signal()
@ -288,5 +286,13 @@ class GoblinAccel(Module): # AutoCSR ?
def get_netlist_name(self):
return "VexRiscv"
class GoblinAccelNuBus(GoblinAccel):
def add_sources(self, platform):
platform.add_source("/home/dolbeau/NuBusFPGA/nubus-to-ztex-gateware/VexRiscv_FbAccel.v", "verilog")
platform.add_source("/home/dolbeau/NuBusFPGA/nubus-to-ztex-gateware/VexRiscv_GoblinAccel_NuBus.v", "verilog")
class GoblinAccelSBus(GoblinAccel):
def add_sources(self, platform):
led0 = platform.request("SBUS_DATA_OE_LED")
self.comb += [ led0.eq(~self.local_reset), ]
platform.add_source("/home/dolbeau/NuBusFPGA/nubus-to-ztex-gateware/VexRiscv_GoblinAccel_SBus.v", "verilog")

2
nubus-to-ztex-gateware/nubus_to_fpga_soc.py
View File

@ -399,7 +399,7 @@ class NuBusFPGA(SoCCore):
#self.comb += pad_user_led_0.eq(self.goblin.video_framebuffer.underflow)
#self.comb += pad_user_led_1.eq(self.goblin.video_framebuffer.fb_dma.enable)
if (True):
self.submodules.goblin_accel = goblin_accel.GoblinAccel(soc = self)
self.submodules.goblin_accel = goblin_accel.GoblinAccelNuBus(soc = self)
self.bus.add_slave("goblin_accel", self.goblin_accel.bus, SoCRegion(origin=self.mem_map.get("goblin_accel", None), size=0x1000, cached=False))
self.bus.add_master(name="goblin_accel_r5_i", master=self.goblin_accel.ibus)
self.bus.add_master(name="goblin_accel_r5_d", master=self.goblin_accel.dbus)