mirror of
https://github.com/rdolbeau/NuBusFPGA.git
synced 2025-02-03 15:32:15 +00:00
HW-acceel big pattern (not sure about alignment...), add basic Icon w/ ShowInitIcon
This commit is contained in:
Romain Dolbeau
parent
173c87ea02
commit
733f446b27
@ -6,6 +6,8 @@
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#include "NuBusFPGA_HW.h"
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#include "ShowInitIcon.h"
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#define kINITid 0
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#define _BitBlt 0xAB00
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@ -45,7 +47,7 @@ static inline unsigned long brev(const unsigned long r) {
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#include "NuBusFPGA_QD.h"
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#ifdef QEMU
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#define DLOG(x) bt->debug - (x);
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#define DLOG(x) bt->debug = (x);
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#else
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#define DLOG(X)
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#endif
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@ -57,68 +59,53 @@ int hwblit(char* stack, char* p_fb_base, /* short dstshift, */ short mode, Patte
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short height = qdstack->MINRECT.bottom - qdstack->MINRECT.top;
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short dstshift = qdstack->DSTSHIFT;
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short srcshift = qdstack->SRCSHIFT;
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short expat_size = 0;
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if ((mode != 0) && (mode != 8)) { // only copy handled for now
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#ifdef QEMU
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#if 0
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DLOG(-2L)
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DLOG(mode)
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if (mode == 8) {
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DLOG(qdstack->PATROW)
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#if 0
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DLOG(pat->pat[0])
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DLOG(pat->pat[1])
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DLOG(pat->pat[2])
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DLOG(pat->pat[3])
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DLOG(pat->pat[4])
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DLOG(pat->pat[5])
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DLOG(pat->pat[6])
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DLOG(pat->pat[7])
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#endif
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}
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#endif
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return 0;
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}
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if (mode == 8) {
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register int i;
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register int i, n;
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register unsigned long expat0 = qdstack->EXPAT[0];
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if (qdstack->PATROW != 0) {
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DLOG(-6L)
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return 0;
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}
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if ((expat0 & 0xFFFF) != ((expat0 >> 16) & 0xFFFF))
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return 0;
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if ((expat0 & 0xFF) != ((expat0 >> 8) & 0xFF))
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return 0;
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for (i = 1 ; i < 16 ; i++)
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if (expat0 != qdstack->EXPAT[i]) {
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DLOG(-7L)
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DLOG(i)
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DLOG(expat0)
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DLOG(qdstack->EXPAT[i])
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return 0;
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DLOG((unsigned long)qdstack->EXPAT)
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expat_size = (qdstack->PATVMASK+1) >> 2;
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DLOG(expat_size)
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for (i = 0 ; i < expat_size ; i++) {
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DLOG(qdstack->EXPAT[i])
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}
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// PATROW is the stride between lines (bytes)
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DLOG(qdstack->PATROW)
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// PATVMASK has the number of bytes-1 in the pattern?
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DLOG(qdstack->PATVMASK)
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// PATHMASK has ???
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DLOG(qdstack->PATHMASK)
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DLOG(qdstack->PATVPOS)
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DLOG(qdstack->PATHPOS)
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if (expat_size > 16384)
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return 0;
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} else {
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if ((expat0 & 0xFFFF) != ((expat0 >> 16) & 0xFFFF))
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return 0;
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if ((expat0 & 0xFF) != ((expat0 >> 8) & 0xFF))
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return 0;
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for (i = 1 ; i < 16 ; i++)
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if (expat0 != qdstack->EXPAT[i]) {
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DLOG(-7L)
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DLOG(i)
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DLOG(expat0)
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DLOG(qdstack->EXPAT[i])
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return 0;
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}
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}
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}
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#if 0
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if (dstshift < 3) { // only 8/16/32 bits for now
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#ifdef QEMU
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DLOG(-3L)
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DLOG(dstshift)
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#endif
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return 0;
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}
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dstshift -= 3;
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if (srcshift < 3) { // only 8/16/32 bits for now
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#ifdef QEMU
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DLOG(-8L)
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DLOG(srcshift)
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#endif
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return 0;
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}
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srcshift -= 3;
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#endif
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if (srcshift != dstshift) {
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DLOG(-9L)
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@ -133,7 +120,7 @@ int hwblit(char* stack, char* p_fb_base, /* short dstshift, */ short mode, Patte
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}
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if (dstpix->baseAddr != p_fb_base) { // we're not destination
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#ifdef QEMU
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#if 0//def QEMU
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DLOG(-4L)
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DLOG((unsigned long)dstpix->baseAddr)
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#endif
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@ -143,7 +130,7 @@ int hwblit(char* stack, char* p_fb_base, /* short dstshift, */ short mode, Patte
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if ((srcpix->baseAddr != p_fb_base)
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// && ((unsigned long)srcpix->baseAddr >= 0x40000000) // and neither is main memory
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){
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#ifdef QEMU
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#if 0//def QEMU
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DLOG(-5L)
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DLOG((unsigned long)srcpix->baseAddr)
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#endif
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@ -210,6 +197,8 @@ int hwblit(char* stack, char* p_fb_base, /* short dstshift, */ short mode, Patte
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DLOG(qdstack->EXPAT[15])
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}
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#endif
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#if 0
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DLOG(-1L)
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DLOG(srcpix->rowBytes)
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@ -226,6 +215,7 @@ int hwblit(char* stack, char* p_fb_base, /* short dstshift, */ short mode, Patte
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DLOG((long)dstpix->baseAddr)
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DLOG((long)srcpix->baseAddr)
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#endif
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return 0;
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#else
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@ -251,8 +241,19 @@ int hwblit(char* stack, char* p_fb_base, /* short dstshift, */ short mode, Patte
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accel_le->reg_src_stride = (srcpix->rowBytes); // bytes // we should strip the high-order bit, but the HW ignore that for us anyway
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accel_le->reg_cmd = (1<<DO_BLIT_BIT);
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} else if (mode == 8) {
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accel_le->reg_fgcolor = (qdstack->EXPAT[0]);
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accel_le->reg_cmd = (1<<DO_FILL_BIT);
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if (qdstack->PATROW == 0) { // not big pattern, need to improve for non-constant?
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accel_le->reg_fgcolor = (qdstack->EXPAT[0]);
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accel_le->reg_cmd = (1<<DO_FILL_BIT);
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} else { // big pattern
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register unsigned short i;
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for (i = 0 ; i < expat_size ; i++) {
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((unsigned long*)(p_fb_base + GOBLIN_PATTERN_OFFSET))[i] = qdstack->EXPAT[i];
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}
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accel_le->reg_bitblt_src_x = qdstack->PATROW - 1;
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accel_le->reg_bitblt_src_y = ((qdstack->PATVMASK+1)/qdstack->PATROW)-1;
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accel_le->reg_src_stride = qdstack->PATROW;
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accel_le->reg_cmd = (1<<DO_PATT_BIT);
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}
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}
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WAIT_FOR_HW_LE(accel_le);
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@ -348,6 +349,8 @@ void main(void)
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//*debug_ptr = (unsigned long)oldBitBlt;
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SetToolTrapAddress((UniversalProcPtr)myBitBlt, _BitBlt);
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ShowInitIcon(128, true);
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/* restore the a4 world */
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SetA4(oldA4);
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// *debug_ptr = 0xBEEFDEAD;
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BIN
nubus-to-ztex-gateware/NuBusFPGAInit/NuBusFPGAInit.rsrc.bin
Normal file
BIN
nubus-to-ztex-gateware/NuBusFPGAInit/NuBusFPGAInit.rsrc.bin
Normal file
Binary file not shown.
@ -7,6 +7,10 @@
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#define GOBLIN_ACCEL_OFFSET 0x00901000
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#define GOBLIN_ACCEL_OFFSET_LE 0x00901800
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#define GOBLIN_FB_OFFSET 0x00000000
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#define GOBLIN_PATTERN_OFFSET 0x007F0000 // 8 MiB - 64 KiB
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#define u_int32_t volatile unsigned long
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// status
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@ -15,6 +19,7 @@
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// cmd
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#define DO_BLIT_BIT 0 // hardwired in goblin_accel.py
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#define DO_FILL_BIT 1 // hardwired in goblin_accel.py
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#define DO_PATT_BIT 2 // hardwired in goblin_accel.py
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#define DO_TEST_BIT 3 // hardwired in goblin_accel.py
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@ -33,10 +33,13 @@ struct control_blitter {
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#define FUN_BLIT_BIT 0 // hardwired in goblin_accel.py
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#define FUN_FILL_BIT 1 // hardwired in goblin_accel.py
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#define FUN_PATT_BIT 2 // hardwired in goblin_accel.py
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#define FUN_TEST_BIT 3 // hardwired in goblin_accel.py
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#define FUN_DONE_BIT 31
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#define FUN_BLIT (1<<FUN_BLIT_BIT)
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#define FUN_FILL (1<<FUN_FILL_BIT)
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#define FUN_PATT (1<<FUN_PATT_BIT)
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#define FUN_TEST (1<<FUN_TEST_BIT)
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#define FUN_DONE (1<<FUN_DONE_BIT)
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@ -146,6 +149,18 @@ static void bitblit(const unsigned_param_type xs,
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const unsigned_param_type dst_stride
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);
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static void patternrectfill(const unsigned_param_type xd,
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const unsigned_param_type yd,
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const unsigned_param_type wi,
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const unsigned_param_type re,
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unsigned char *pat_ptr,
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const unsigned_param_type pat_xmask,
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const unsigned_param_type pat_ymask,
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const unsigned_param_type pat_stride,
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unsigned char* dst_ptr,
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const unsigned_param_type dst_stride
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);
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static void print_hexword(unsigned int v, unsigned int bx, unsigned int by);
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static void show_status_on_screen(void);
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@ -244,6 +259,16 @@ void from_reset(void) {
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fbc->reg_dst_ptr ? (unsigned char*)fbc->reg_dst_ptr : (unsigned char*)BASE_FB,
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fbc->reg_dst_stride); // assumed to be scaled already
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} break;
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case FUN_PATT: {
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patternrectfill(dstx, fbc->reg_bitblt_dst_y,
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wi , fbc->reg_height,
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(unsigned char*)BASE_FB + (8*1024*1024) - (64*1024), // FIXME
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fbc->reg_bitblt_src_x, // unscaled
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fbc->reg_bitblt_src_y, // unscaled
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fbc->reg_src_stride,
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fbc->reg_dst_ptr ? (unsigned char*)fbc->reg_dst_ptr : (unsigned char*)BASE_FB,
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fbc->reg_dst_stride); // assumed to be scaled already
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} break;
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default:
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break;
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}
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@ -881,3 +906,52 @@ static void bitblit_fwd_fwd_copy(const unsigned_param_type xs,
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dptr_line += dst_stride;
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}
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}
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static void patternrectfill(const unsigned_param_type xd,
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const unsigned_param_type yd,
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const unsigned_param_type wi,
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const unsigned_param_type re,
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unsigned char *pat_ptr,
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const unsigned_param_type pat_xmask,
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const unsigned_param_type pat_ymask,
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const unsigned_param_type pat_stride,
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unsigned char* dst_ptr,
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const unsigned_param_type dst_stride
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) {
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struct goblin_accel_regs* fbc = (struct goblin_accel_regs*)BASE_ACCEL_REGS;
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unsigned int i, j;
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unsigned int io, jo;
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unsigned char *dptr = (dst_ptr + (yd * dst_stride) + xd);
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unsigned char *dptr_line = dptr;
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unsigned char *pat_ptr_line;
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io = xd & pat_xmask;
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jo = yd & pat_ymask;
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pat_ptr_line = pat_ptr + (jo & pat_ymask) * pat_stride;
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for (j = 0 ; j < re ; j++) {
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unsigned char *dptr_elt = dptr_line;
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i = 0;
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for ( ; i < wi && ((unsigned int)dptr_elt&0x3)!=0; i++) {
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dptr_elt[0] = pat_ptr_line[(i+io) & pat_xmask];
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dptr_elt ++;
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}
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unsigned int fsr_cst = 8*((i+io) & 0x3);
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unsigned int src0 = ((unsigned int*)pat_ptr_line)[((i+io) & pat_xmask) >> 2];
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for ( ; i < (wi-3) ; i+=4) {
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unsigned int src1 = ((unsigned int*)pat_ptr_line)[((i+io+4) & pat_xmask) >> 2];
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unsigned int val;
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asm("fsr %0, %1, %2, %3\n" : "=r"(val) : "r"(src0), "r"(src1), "r"(fsr_cst));
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((unsigned int*)dptr_elt)[0] = val;
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src0 = src1;
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dptr_elt += 4;
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}
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for ( ; i < wi ; i++) {
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dptr_elt[0] = pat_ptr_line[(i+io) & pat_xmask];
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dptr_elt ++;
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}
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dptr_line += dst_stride;
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pat_ptr_line = pat_ptr + ((j+jo) & pat_ymask) * pat_stride;
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}
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}
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@ -37,11 +37,13 @@ class GoblinAccel(Module): # AutoCSR ?
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# do-some-work flags
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do_blit = Signal()
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do_fill = Signal()
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do_patt = Signal()
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do_test = Signal()
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# cmd register reg_cmd
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DO_BLIT_BIT = 0
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DO_FILL_BIT = 1
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DO_PATT_BIT = 2
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DO_TEST_BIT = 3
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# global status register reg_status
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@ -80,6 +82,7 @@ class GoblinAccel(Module): # AutoCSR ?
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1: [ NextValue(reg_cmd, bus_dat_w_endian),
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NextValue(do_blit, bus_dat_w_endian[DO_BLIT_BIT] & ~reg_status[WORK_IN_PROGRESS_BIT]),
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NextValue(do_fill, bus_dat_w_endian[DO_FILL_BIT] & ~reg_status[WORK_IN_PROGRESS_BIT]),
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NextValue(do_patt, bus_dat_w_endian[DO_PATT_BIT] & ~reg_status[WORK_IN_PROGRESS_BIT]),
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NextValue(do_test, bus_dat_w_endian[DO_TEST_BIT] & ~reg_status[WORK_IN_PROGRESS_BIT]),
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],
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2: [ NextValue(reg_r5_cmd, bus_dat_w_endian) ],
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@ -128,6 +131,7 @@ class GoblinAccel(Module): # AutoCSR ?
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FUN_DONE_BIT = 31
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FUN_BLIT_BIT = 0
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FUN_FILL_BIT = 1
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FUN_PATT_BIT = 2
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FUN_TEST_BIT = 3
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# to hold the Vex in reset
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local_reset = Signal(reset = 1)
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@ -150,6 +154,12 @@ class GoblinAccel(Module): # AutoCSR ?
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reg_status[WORK_IN_PROGRESS_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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).Elif(do_patt & ~reg_status[WORK_IN_PROGRESS_BIT],
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do_patt.eq(0),
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reg_r5_cmd[FUN_PATT_BIT].eq(1),
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reg_status[WORK_IN_PROGRESS_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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).Elif(do_test & ~reg_status[WORK_IN_PROGRESS_BIT],
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do_test.eq(0),
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reg_r5_cmd[FUN_TEST_BIT].eq(1),
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