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Move Vex to a 128-bit Wishbone, and add a bypass to access a dedicated memory port with a 128-bits datapath. Speeds up scrolling quite nicely.

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This commit is contained in:
Romain Dolbeau 2022-06-05 18:03:23 +02:00
parent d9c21e7abb
commit 94cd6a9411
3 changed files with 3680 additions and 3069 deletions
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6636
nubus-to-ztex-gateware/VexRiscv_FbAccel.v
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111
nubus-to-ztex-gateware/goblin_accel.py
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@ -5,6 +5,9 @@ from litex.soc.interconnect.csr import *
from litex.soc.interconnect import wishbone
from litedram.common import LiteDRAMNativePort
from litedram.frontend.wishbone import LiteDRAMWishbone2Native
class GoblinAccel(Module): # AutoCSR ?
def __init__(self, soc):
platform = soc.platform
@ -157,12 +160,92 @@ class GoblinAccel(Module): # AutoCSR ?
]
#led0 = platform.request("user_led", 0)
#self.comb += led0.eq(~local_reset)
#self.comb += led0.eq(~local_reset) # Vex connection to the primary bus
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
#self.dbus = dbus = wishbone.Interface()
vex_reset = Signal()
dbus_raw = wishbone.Interface(data_width=128, adr_width=28) # wide interface from the Vex, master
dbus_sys = wishbone.Interface(data_width=128, adr_width=28) # wide interface to system wishbone
dbus_mem = wishbone.Interface(data_width=128, adr_width=28) # wide interface for direct memory access
self.dbus = dbus_sys
#masters = {}
#masters["VexRiscv_AccelFB"] = dbus_raw
##slaves["VexSystemAccess"] = dbus
##regions["VexSystemAccess"] = SoCRegion(origin=soc.mem_map.get("goblin_bt", None), size=0x00100000, cached=False)
##slaves["VexMemoryAccess"] = dbus_mem
##regions["VexSystemAccess"] = SoCRegion(origin=soc.mem_map.get("main_ram", None), size=0x10000000, cached=True)
#function_VexSystemAccess = lambda x: (x[24:28] != 0x8)
#function_VexMemoryAccess = lambda x: (x[24:28] == 0x8)
##function_VexSystemAccess = lambda x: (True)
##function_VexMemoryAccess = lambda x: (False)
#slaves = [
# (function_VexSystemAccess, dbus_sys),
# (function_VexMemoryAccess, dbus_mem),
#]
#self.submodules.crossbar = wishbone.Crossbar(
# masters = masters.values(),
# slaves = slaves,
# register = False,
# timeout_cycles = None
#)
#self.submodules.shared = wishbone.InterconnectShared(
# masters = masters.values(),
# slaves = slaves,
# register = False,
# timeout_cycles = None
#)
self.comb += [
If((dbus_raw.adr[24:28] == 0x8),
dbus_sys.cyc.eq(0),
dbus_sys.stb.eq(0),
dbus_mem.cyc.eq(dbus_raw.cyc),
dbus_mem.stb.eq(dbus_raw.stb),
dbus_raw.ack.eq(dbus_mem.ack),
dbus_raw.err.eq(dbus_mem.err),
dbus_raw.dat_r.eq(dbus_mem.dat_r),
).Else(
dbus_sys.cyc.eq(dbus_raw.cyc),
dbus_sys.stb.eq(dbus_raw.stb),
dbus_mem.cyc.eq(0),
dbus_mem.stb.eq(0),
dbus_raw.ack.eq(dbus_sys.ack),
dbus_raw.err.eq(dbus_sys.err),
dbus_raw.dat_r.eq(dbus_sys.dat_r),
),
dbus_sys.dat_w.eq(dbus_raw.dat_w),
dbus_mem.dat_w.eq(dbus_raw.dat_w),
dbus_sys.we.eq(dbus_raw.we),
dbus_mem.we.eq(dbus_raw.we),
dbus_sys.adr.eq(dbus_raw.adr),
dbus_mem.adr.eq(dbus_raw.adr),
dbus_sys.sel.eq(dbus_raw.sel),
dbus_mem.sel.eq(dbus_raw.sel),
dbus_sys.cti.eq(dbus_raw.cti),
dbus_mem.cti.eq(dbus_raw.cti),
dbus_sys.bte.eq(dbus_raw.bte),
dbus_mem.bte.eq(dbus_raw.bte),
]
# now connect the memory
# memory port
port = soc.sdram.crossbar.get_port()
assert(port.data_width == 128)
self.submodules.wb2native = LiteDRAMWishbone2Native(
wishbone = dbus_mem,
port = port,
base_address = soc.bus.regions["main_ram"].origin
)
self.comb += vex_reset.eq(ResetSignal("sys") | local_reset)
self.specials += Instance(self.get_netlist_name(),
i_clk = ClockSignal("sys"),
@ -178,17 +261,17 @@ class GoblinAccel(Module): # AutoCSR ?
i_iBusWishbone_ERR = ibus.err,
o_iBusWishbone_CTI = ibus.cti,
o_iBusWishbone_BTE = ibus.bte,
o_dBusWishbone_CYC = dbus.cyc,
o_dBusWishbone_STB = dbus.stb,
i_dBusWishbone_ACK = dbus.ack,
o_dBusWishbone_WE = dbus.we,
o_dBusWishbone_ADR = dbus.adr,
i_dBusWishbone_DAT_MISO = dbus.dat_r,
o_dBusWishbone_DAT_MOSI = dbus.dat_w,
o_dBusWishbone_SEL = dbus.sel,
i_dBusWishbone_ERR = dbus.err,
o_dBusWishbone_CTI = dbus.cti,
o_dBusWishbone_BTE = dbus.bte,)
o_dBusWishbone_CYC = dbus_raw.cyc,
o_dBusWishbone_STB = dbus_raw.stb,
i_dBusWishbone_ACK = dbus_raw.ack,
o_dBusWishbone_WE = dbus_raw.we,
o_dBusWishbone_ADR = dbus_raw.adr,
i_dBusWishbone_DAT_MISO = dbus_raw.dat_r,
o_dBusWishbone_DAT_MOSI = dbus_raw.dat_w,
o_dBusWishbone_SEL = dbus_raw.sel,
i_dBusWishbone_ERR = dbus_raw.err,
o_dBusWishbone_CTI = dbus_raw.cti,
o_dBusWishbone_BTE = dbus_raw.bte,)
self.add_sources(platform)

2
nubus-to-ztex-gateware/nubus_to_fpga_soc.py
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@ -320,7 +320,7 @@ class NuBusFPGA(SoCCore):
self.submodules.wishbone_master_nubus = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_master_sys, cd_master="nubus", cd_slave="sys")
nubus_writemaster_sys = wishbone.Interface(data_width=self.bus.data_width)
wishbone_slave_nubus = wishbone.Interface(data_width=self.bus.data_width)
self.submodules.wishbone_slave_sys = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_slave_nubus, cd_master="sys", cd_slave="nubus")
self.submodules.wishbone_slave_sys = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_slave_nubus, cd_master="sys", cd_slave="nubus", force_delay=6) # force delay needed to avoid back-to-back transaction running into issue https://github.com/alexforencich/verilog-wishbone/issues/4
self.submodules.nubus = nubus_full.NuBus(platform=platform,
wb_read=self.wishbone_master_nubus,
wb_write=nubus_writemaster_sys,