From b988cee925ef92e511a6d2da8568974905a0ce88 Mon Sep 17 00:00:00 2001 From: Romain Dolbeau Date: Fri, 4 Nov 2022 09:28:55 +0100 Subject: [PATCH] commit patch for newer Litex --- nubus-to-ztex-gateware/DepVideoEqu.a | 1 - nubus-to-ztex-gateware/NuBusFPGADrvr.a | 0 nubus-to-ztex-gateware/NuBusFPGAPrimaryInit.a | 1 - nubus-to-ztex-gateware/NuBusFPGASecondaryInit.a | 0 nubus-to-ztex-gateware/VintageBusFPGA_Common | 2 +- nubus-to-ztex-gateware/nubus_to_fpga_export.py | 6 ++++-- nubus-to-ztex-gateware/nubus_to_fpga_soc.py | 1 + nubus-to-ztex-gateware/rom.a | 1 - nubus-to-ztex-gateware/sdram_init.py | 2 +- 9 files changed, 7 insertions(+), 7 deletions(-) delete mode 100755 nubus-to-ztex-gateware/DepVideoEqu.a delete mode 100644 nubus-to-ztex-gateware/NuBusFPGADrvr.a delete mode 100644 nubus-to-ztex-gateware/NuBusFPGAPrimaryInit.a delete mode 100644 nubus-to-ztex-gateware/NuBusFPGASecondaryInit.a delete mode 100644 nubus-to-ztex-gateware/rom.a diff --git a/nubus-to-ztex-gateware/DepVideoEqu.a b/nubus-to-ztex-gateware/DepVideoEqu.a deleted file mode 100755 index d6eb7ac..0000000 --- a/nubus-to-ztex-gateware/DepVideoEqu.a +++ /dev/null @@ -1 +0,0 @@ -NuBusFPGAID EQU $BEEF defMinorBase EQU 0 ; beginning defMinorLength EQU $C0000 ; 768 KiB Pages8s EQU 1 ; no idea defmBounds_Ts EQU 0 defmBounds_Ls EQU 0 defmBounds_Bs EQU 480 defmBounds_Rs EQU 640 DrHwNuBusFPGA EQU $BEEF ; placeholder defmBaseOffset EQU 0 ; beginning, placeholder devVersion EQU 0 ; placeholder defmHRes EQU $480000 ;Horizontal Pixels/inch defmVRes EQU $480000 ;Vertical pixels/inch defmDevType EQU 0 ;0 = CLUTType defmPlaneBytes EQU 0 ;Offset from one plane to the next. SGammaResID EQU 0 RB8s EQU 640 ChunkyIndexed EQU 0 defVersion EQU 0 ;Version = 0 ROMSize EQU $1000 ;4K byte ROM \ No newline at end of file diff --git a/nubus-to-ztex-gateware/NuBusFPGADrvr.a b/nubus-to-ztex-gateware/NuBusFPGADrvr.a deleted file mode 100644 index e69de29..0000000 diff --git a/nubus-to-ztex-gateware/NuBusFPGAPrimaryInit.a b/nubus-to-ztex-gateware/NuBusFPGAPrimaryInit.a deleted file mode 100644 index a78c4f4..0000000 --- a/nubus-to-ztex-gateware/NuBusFPGAPrimaryInit.a +++ /dev/null @@ -1 +0,0 @@ - DC.B sExec2 ; code revision DC.B sCPU68020 ; CPU type is 68020 DC.W 0 ; reserved DC.L Begin1stInit-* ; offset to code WITH seBlock,spBlock Begin1stInit MOVE.W #1,seStatus(A0) ; assume a good return MOVE.L #$F0000000,D1 ; Dl <- F0000000 MOVE.B seSlot(A0),D0 ; get slot number BFINS D0,D1{4:4} ; Dl <- Fs000000 MOVE.L D1,A1 ; copy to address reg ;;; INITIALIZE SOME STUFF HERE SUBA #spBlockSize,SP ; make an spB10ck MOVE.L SP,A0 ; get pointer to parms MOVE.B D0,spSlot(A0) ; identify the slot CLR.B SpExtDev(A0) ; external device = 0 RTS ENDWITH \ No newline at end of file diff --git a/nubus-to-ztex-gateware/NuBusFPGASecondaryInit.a b/nubus-to-ztex-gateware/NuBusFPGASecondaryInit.a deleted file mode 100644 index e69de29..0000000 diff --git a/nubus-to-ztex-gateware/VintageBusFPGA_Common b/nubus-to-ztex-gateware/VintageBusFPGA_Common index c7d1176..3423585 160000 --- a/nubus-to-ztex-gateware/VintageBusFPGA_Common +++ b/nubus-to-ztex-gateware/VintageBusFPGA_Common @@ -1 +1 @@ -Subproject commit c7d117677ecd10b4990ccf42187265c53a46c1e2 +Subproject commit 342358535e10c4efc1660a442aba68c79ae7d166 diff --git a/nubus-to-ztex-gateware/nubus_to_fpga_export.py b/nubus-to-ztex-gateware/nubus_to_fpga_export.py index af11c9d..12694e6 100644 --- a/nubus-to-ztex-gateware/nubus_to_fpga_export.py +++ b/nubus-to-ztex-gateware/nubus_to_fpga_export.py @@ -88,8 +88,10 @@ def get_csr_header_split(regions, constants, csr_base=None, with_access_function if not isinstance(region.obj, Memory): for csr in region.obj: nr = (csr.size + region.busword - 1)//region.busword - r += _get_rw_functions_c(csr.name, origin, nr, region.busword, alignment, - getattr(csr, "read_only", False), with_access_functions) + r += _get_rw_functions_c(reg_name=csr.name, reg_base=origin, nwords=nr, busword=region.busword, alignment=alignment, + read_only=getattr(csr, "read_only", False), + csr_base=0, with_csr_base_define=False, + with_access_functions=with_access_functions) origin += alignment//8*nr if hasattr(csr, "fields"): for field in csr.fields.fields: diff --git a/nubus-to-ztex-gateware/nubus_to_fpga_soc.py b/nubus-to-ztex-gateware/nubus_to_fpga_soc.py index eb46a50..29751b4 100644 --- a/nubus-to-ztex-gateware/nubus_to_fpga_soc.py +++ b/nubus-to-ztex-gateware/nubus_to_fpga_soc.py @@ -181,6 +181,7 @@ class NuBusFPGA(SoCCore): sys_clk_freq=sys_clk_freq, clk_freq=sys_clk_freq, csr_paging=0x800, # default is 0x800 + bus_interconnect = "crossbar", **kwargs) # Quoting the doc: diff --git a/nubus-to-ztex-gateware/rom.a b/nubus-to-ztex-gateware/rom.a deleted file mode 100644 index 7b921d3..0000000 --- a/nubus-to-ztex-gateware/rom.a +++ /dev/null @@ -1 +0,0 @@ -;Include files PRINT OFF INCLUDE 'SysErr.a' ;Macintosh System equates INCLUDE 'SysEqu.a' ;Macintosh System equates INCLUDE 'ROMEqu.a' ;Declaration ROM equates INCLUDE 'SlotEqu.a' ;Slot Manager equates and macros INCLUDE 'TimeEqu.a' ;Macintosh traps INCLUDE 'Traps.a' ;Macintosh traps INCLUDE 'VideoEqu.a' ;Video driver equates INCLUDE 'DepVideoEqu.a' PRINT ON MACHINE MC68020 DclROM MAIN sRsrc_Board EQU 1 ; board sResource (>0 & <128) sRsrc_VidS8 EQU $80 ; functional sResources _sRsrcDir OSLstEntry sRsrc_Board,_sRsrc_Board ; board sRsrc List OSLstEntry sRsrc_VidS8,_sRsrc_VidS8 ; video sRsrc List DatLstEntry EndOfList,0 ; end of list STRING C _sRsrc_Board OSLstEntry sRsrcType,_BoardType ; offset to board descriptor OSLstEntry sRsrcName,_BoardName ; offset to name of board DatLstEntry boardId,NuBusFPGAID ; board ID # (assigned by DTS) OSLstEntry PrimaryInit,_sPInitRec ; offset to PrimaryInit exec blk OSLstEntry VendorInfo,_VendorInfo ; offset to vendor info record ;OSLstEntry SecondaryInit,_sSInitRec ; offset to SecondaryInit block DatLstEntry EndOfList,0 ; end of list _BoardType DC.W CatBoard ; board sResource DC.W TypBoard DC.W 0 DC.W 0 _BoardName DC.L 'SBusFPGA Video' ; name of board ; _VidICON ; optional icon, not needed ; _sVidNameDir ; optional name(s), not needed _sPInitRec DC.L _EndsPInitRec-_sPInitRec ; physical block size INCLUDE 'NuBusFPGAPrimaryInit.a' ; the header/code ALIGN 2 _EndsPInitRec ;_sSInitRec ; DC.L _EndsSInitRec-_sSInitRec ; physical block size ; INCLUDE 'NuBusFPGASecondaryInit.a' ; the header/code ; ALIGN 2 ;_EndsSInitRec STRING C _VendorInfo OSLstEntry VendorId,_VendorId ; offset to vendor ID OSLstEntry RevLevel,_RevLevel ; offset to revision OSLstEntry PartNum,_PartNum ; offset to part number record OSLstEntry Date,_Date ; offset to ROM build date DatLstEntry EndOfList,0 _VendorId DC.L 'Romain Dolbeau' ; vendor ID _RevLevel DC.L 'NuBusFPGA V1.0' ; revision level _PartNum DC.L 'Part Number' ; part number _Date DC.B '&SysDate' ; date _sRsrc_VidS8 OSLstEntry sRsrcType,_VideoType ; video type descriptor OSLstEntry sRsrcName,_VideoName ; offset to driver name string ; OSLstEntry sRsrcDrvrDir,_VidDrvrDir ; offset to driver directory DatLstEntry sRsrcHWDevId,1 ; hardware device ID OSLstEntry MinorBaseOS,_MinorBase ; offset to frame buffer array OSLstEntry MinorLength,_MinorLength ; offset to frame buffer length OSLstEntry sGammaDir,_GammaDirS ; directory for 640x480 monitor ; Parameters OSLstEntry FirstVidMode,_EBMs ; offset to EightBitMode parms DatLstEntry EndOfList,0 ; end of list STRING C _VideoType DC.W CatDisplay ; DC.W TypVideo ; DC.W DrSwApple ; DC.W DrHwNuBusFPGA ; _VideoName DC.L 'Video_NuBusFPGA' ; video driver name _MinorBase DC.L defMinorBase ; frame buffer offset _MinorLength DC.L defMinorLength ; frame buffer length ;_VidDrvrDir ; OSLstEntry sMacOS68020,_sMacOS68020 driver directory for Mac OS ; DatLstEntry EndOfList,0 ; ;_sMacOS68020 ; DC.L _End020Drvr- sMacOS68020 ; physical block size ; INCLUDE 'NuBusFPGADrvr.a' ; driver code ;_End020Drvr STRING C _GammaDirS ; for the 640x480 monitor OSLstEntry 128,_SmallGamma DatLstEntry EndOfList,0 _SmallGamma DC.L _EndSmallGamma-_SmallGamma DC.W SGammaResID DC.B 'Small Gamma' ; Monitors name ALIGN 2 DC.W $0000 ; gVersion DC.W DrHwNuBusFPGA ; gType DC.W $0000 ; gFormulaSize DC.W $0001 ; gChanCnt DC.W $0100 ; gDataCnt DC.W $0008 ; gChanWidth DC.L $0005090B,$0E101315,$17191B1D,$1E202224 DC.L $2527282A,$2C2D2F30,$31333436,$37383A3B DC.L $3C3E3F40,$42434445,$4748494A,$4B4D4E4F DC.L $50515254,$55565758,$595A5B5C,$5E5F6061 DC.L $62636465,$66676869,$6A6B6C6D,$6E6F7071 DC.L $72737475,$76777879,$7A7B7C7D,$7E7F8081 DC.L $81828384,$85868788,$898A8B8C,$8C8D8E8F DC.L $90919293,$94959596,$9798999A,$9B9B9C9D DC.L $9E9FA0A1,$A1A2A3A4,$A5A6A6A7,$A8A9AAAB DC.L $ABACADAE,$AFB0B0B1,$B2B3B4B4,$B5B6B7B8 DC.L $B8B9BABB,$BCBCBDBE,$BFC0C0C1,$C2C3C3C4 DC.L $C5C6C7C7,$C8C9CACA,$CBCCCDCD,$CECFD0D0 DC.L $D1D2D3D3,$D4D5D6D6,$D7D8D9D9,$DADBDCDC DC.L $DDDEDFDF,$E0E1E1E2,$E3E4E4E5,$E6E7E7E8 DC.L $E9B9EAEB,$ECECEDEE,$EEEFF0F1,$F1F2F3F3 DC.L $F4F5F5F6,$F7F8F8F9,$FAFAFBFC,$FCFDFEFF _EndSmallGamma _EBMs OSLstEntry mVidParams,_EBVParms ; offset to vid parameters DatLstEntry mPageCnt,Pages8s ; number of video pages DatLstEntry mDevType,defmDevType ; device type DatLstEntry EndOfList,0 ; end of list _EBVParms DC.L _EndEBVParms-_EBVParms ; physical block size DC.L defmBaseOffset ; QuickDraw base offset ; vpBaseOffset DC.W RB8s ; physRowBytes ; vpRowBytes DC.W defmBounds_Ts,defmBounds_Ls,defmBounds_Bs,defmBounds_Rs ; vpBounds DC.W defVersion ; bmVersion ; vpVersion DC.W 0 ; packType not used ; vpPackType DC.L 0 ; packSize not used ; vpPackSize DC.L defmHRes ; bmHRes DC.L defmVRes ; bmVRes DC.W ChunkyIndexed ; bmPixelType DC.W 8 ; bmPixelSize DC.W 1 ; bmCmpCount DC.W 8 ; bmCmpSize DC.L defmPlaneBytes ; bmPlaneBytes _EndEBVParms WITH FHeaderRec ORG ROMSize-FHeaderRec.fhBlockSize DC.L (_sRsrcDir-*)**$00FFFFFF ;offset to sResource directory DC.L ROMSize ;length of declaration data DC.L 0 ;CRC {Patched by crcPatch} DC.B 2 ;revision (1-9) DC.B AppleFormat ; format DC.L TestPattern ;test pattern DC.B 0 ;reserved byte DC.B $0F ;ByteLanes: 1111 0001 ENDWITH END \ No newline at end of file diff --git a/nubus-to-ztex-gateware/sdram_init.py b/nubus-to-ztex-gateware/sdram_init.py index de0e881..a21b60e 100644 --- a/nubus-to-ztex-gateware/sdram_init.py +++ b/nubus-to-ztex-gateware/sdram_init.py @@ -28,7 +28,7 @@ sdram_dfii_pi0_baddress = sdram_dfii_base + 0x010 # /!\ keep up to date with csr /!\ ddrphy_base = 0xf0a00000 ddrphy_rst = ddrphy_base + 0x000 -ddrphy_dly_sel = ddrphy_base + 0x010 +ddrphy_dly_sel = ddrphy_base + 0x004 ddrphy_rdly_dq_rst = ddrphy_base + 0x014 ddrphy_rdly_dq_inc = ddrphy_base + 0x018 ddrphy_rdly_dq_bitslip_rst = ddrphy_base + 0x01c