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track HW changes
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@ -226,6 +226,9 @@ int hwblit(char* stack, char* p_fb_base, /* short dstshift, */ short mode, Patte
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#else
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WAIT_FOR_HW_LE(accel_le);
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accel_le->reg_op = 0x3; // GXcopy
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accel_le->reg_depth = 0; // current
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accel_le->reg_width = (width); // pixels
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accel_le->reg_height = (height);
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accel_le->reg_bitblt_dst_x = (dstv.left); // pixels
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@ -17,11 +17,12 @@
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#define WORK_IN_PROGRESS_BIT 0
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// cmd
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#define DO_BLIT_BIT 0 // hardwired in goblin_accel.py
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#define DO_FILL_BIT 1 // hardwired in goblin_accel.py
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#define DO_PATT_BIT 2 // hardwired in goblin_accel.py
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#define DO_TEST_BIT 3 // hardwired in goblin_accel.py
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#define DO_BLIT_BIT 0 // all hardwired in goblin_accel.py
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#define DO_FILL_BIT 1
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#define DO_PATT_BIT 2
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#define DO_RSMSK8DST32_BIT 3
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#define DO_RSRC32MSK32DST32_BIT 4
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#define DO_RSRC32DST32_BIT 5
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#define FUN_DONE_BIT 31
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@ -40,11 +41,11 @@ struct goblin_accel_regs {
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u_int32_t reg_status; // 0
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u_int32_t reg_cmd;
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u_int32_t reg_r5_cmd;
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u_int32_t resv0;
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u_int32_t reg_op;
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u_int32_t reg_width; // 4
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u_int32_t reg_height;
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u_int32_t reg_fgcolor;
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u_int32_t resv2;
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u_int32_t reg_depth;
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u_int32_t reg_bitblt_src_x; // 8
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u_int32_t reg_bitblt_src_y;
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u_int32_t reg_bitblt_dst_x;
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@ -53,6 +54,10 @@ struct goblin_accel_regs {
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u_int32_t reg_dst_stride;
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u_int32_t reg_src_ptr; // 14
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u_int32_t reg_dst_ptr;
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u_int32_t reg_msk_x; // 16
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u_int32_t reg_msk_y;
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u_int32_t reg_msk_stride; // 18
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u_int32_t reg_msk_ptr;
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};
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