mirror of
https://github.com/rdolbeau/NuBusFPGA.git
synced 2025-04-02 00:29:31 +00:00
add micro-sd HW support
This commit is contained in:
Romain Dolbeau
parent
77852b8d40
commit
f9886f7280
@ -2,7 +2,7 @@
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source /opt/Xilinx/Vivado/2020.1/settings64.sh
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export LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2020.1/lib/lnx64.o/SuSE
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python3 nubus_to_fpga_soc.py --build --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6 --goblin --goblin-res 1920x1080@60Hz --hdmi # --ethernet
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python3 nubus_to_fpga_soc.py --build --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6 --goblin --goblin-res 1920x1080@60Hz --hdmi --sdcard --flash # --ethernet
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#python3 nubus_to_fpga_soc.py --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6
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@ -11,3 +11,15 @@ python3 nubus_to_fpga_soc.py --build --csr-csv csr.csv --csr-json csr.json --var
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# --hdmi
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grep -A10 'Design Timing Summary' build/ztex213_nubus_V1_2/gateware/ztex213_nubus_V1_2_timing.rpt
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###
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# For 16 MiB Flash NOR (W25Q128.V):
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# truncate -s $((16*1024*1024)) vid_decl_rom.bin
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# flashrom -c W25Q128.V -p linux_spi:dev=/dev/spidev0.0,spispeed=2000 -l nubus_prom.layout -i ROM -w vid_decl_rom.bin
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#
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# where nubus_prom.layout contains:
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###
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# 00000000:00007fff ROM
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# 00008000:00ffffff VDISK
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###
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@ -37,6 +37,7 @@ from VintageBusFPGA_Common.goblin_accel import *
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# Wishbone stuff
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from VintageBusFPGA_Common.cdc_wb import WishboneDomainCrossingMaster
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from VintageBusFPGA_Common.fpga_blk_dma import *
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from VintageBusFPGA_Common.fpga_sd_dma import *
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from nubus_mem_wb import NuBus2Wishbone
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from nubus_memfifo_wb import NuBus2WishboneFIFO
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@ -181,8 +182,26 @@ class _CRG(Module):
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class NuBusFPGA(SoCCore):
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def __init__(self, variant, version, sys_clk_freq, goblin, hdmi, goblin_res, ethernet, **kwargs):
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class NuBusFPGA(SoCCore): # Add SDCard -----------------------------------------------------------------------------------
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# WiP
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def add_sdcard_custom(self, name="sdcard", mode="read+write"):
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# Imports.
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from litesdcard.phy import SDPHY
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from litesdcard.core import SDCore
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# Checks.
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assert mode in ["read", "write", "read+write"]
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# Pads.
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sdcard_pads = self.platform.request(name)
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# Core.
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self.check_if_exists("sdphy")
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self.check_if_exists("sdcore")
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self.sdphy = SDPHY(sdcard_pads, self.platform.device, self.clk_freq, cmd_timeout=10e-1, data_timeout=10e-1)
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self.sdcore = SDCore(self.sdphy)
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def __init__(self, variant, version, sys_clk_freq, goblin, hdmi, goblin_res, sdcard, flash, ethernet, **kwargs):
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print(f"Building NuBusFPGA for board version {version}")
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kwargs["cpu_type"] = "None"
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@ -193,6 +212,9 @@ class NuBusFPGA(SoCCore):
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self.sys_clk_freq = sys_clk_freq
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self.platform = platform = ztex213_nubus.Platform(variant = variant, version = version)
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if (flash and (version == "V1.2")):
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platform.add_extension(ztex213_nubus._flashtemp_pmod_io_v1_2)
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if (ethernet and (version == "V1.2")):
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platform.add_extension(ztex213_nubus._rmii_eth_extpmod_io_v1_2)
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@ -253,7 +275,9 @@ class NuBusFPGA(SoCCore):
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"csr" : 0xF0A00000, # CSR
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"pingmaster": 0xF0B00000,
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"ethmac": 0xF0C00000,
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#"spiflash": 0xF0D00000, # testing
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"rom": 0xF0FF8000, # ROM at the end (32 KiB of it ATM)
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"spiflash": 0xF0FF8000, # FIXME currently the flash is in the ROM spot, limited to 32 KiB
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#"END OF SLOT SPACE": 0xF0FFFFFF,
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}
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self.mem_map.update(wb_mem_map)
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@ -263,6 +287,8 @@ class NuBusFPGA(SoCCore):
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xdc_timings_filename = None;
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#if (version == "V1.0"):
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# xdc_timings_filename = "/home/dolbeau/nubus-to-ztex-gateware/nubus_fpga_V1_0_timings.xdc"
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if (version == "V1.2"):
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xdc_timings_filename = "nubus_fpga_V1_2_timings.xdc"
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if (xdc_timings_filename != None):
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xdc_timings_file = open(xdc_timings_filename)
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@ -274,14 +300,25 @@ class NuBusFPGA(SoCCore):
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#print(fix_line)
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platform.add_platform_command(fix_line)
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rom_file = "rom_{}.bin".format(version.replace(".", "_"))
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rom_data = soc_core.get_mem_data(filename_or_regions=rom_file, endianness="little") # "big"
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# rom = Array(rom_data)
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#print("\n****************************************\n")
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#for i in range(len(rom)):
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# print(hex(rom[i]))
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#print("\n****************************************\n")
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self.add_ram("rom", origin=self.mem_map["rom"], size=2**15, contents=rom_data, mode="r") ## 32 KiB, must match mmap
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if (not flash):
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rom_file = "rom_{}.bin".format(version.replace(".", "_"))
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rom_data = soc_core.get_mem_data(filename_or_regions=rom_file, endianness="little") # "big"
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# rom = Array(rom_data)
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#print("\n****************************************\n")
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#for i in range(len(rom)):
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# print(hex(rom[i]))
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#print("\n****************************************\n")
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self.add_ram("rom", origin=self.mem_map["rom"], size=2**15, contents=rom_data, mode="r") ## 32 KiB, must match mmap
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if (flash):
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from litespi.modules.generated_modules import W25Q128JV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x",
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clk_freq = sys_clk_freq/4, # Fixme; PHY freq ?
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module=W25Q128JV(Codes.READ_1_1_4),
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region_size = 0x00008000, # 32 KiB
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with_mmap=True, with_master=False)
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#from wb_test import WA2D
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#self.submodules.wa2d = WA2D(self.platform)
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@ -379,15 +416,18 @@ class NuBusFPGA(SoCCore):
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self.comb += irq_line.eq(fb_irq) # active low, enable if one is low
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else:
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# details for usesampling in the NuBus python object
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usesampling = True
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usesampling = False
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wishbone_master_sys = wishbone.Interface(data_width=self.bus.data_width)
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if (not usesampling): # we need an extra CDC
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self.submodules.wishbone_master_nubus = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_master_sys, cd_master="nubus", cd_slave="sys") # for non-sampling only
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nubus_writemaster_sys = wishbone.Interface(data_width=self.bus.data_width)
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wishbone_slave_nubus = wishbone.Interface(data_width=self.bus.data_width)
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self.submodules.wishbone_slave_sys = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_slave_nubus, cd_master="sys", cd_slave="nubus", force_delay=6) # force delay needed to avoid back-to-back transaction running into issue https://github.com/alexforencich/verilog-wishbone/issues/4
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self.submodules.wishbone_slave_sys = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_slave_nubus, cd_master="sys", cd_slave="nubus", force_delay=9) # force delay needed to avoid back-to-back transaction running into issue https://github.com/alexforencich/verilog-wishbone/issues/4
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#led0 = platform.request("user_led", 0)
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#led1 = platform.request("user_led", 1)
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#self.comb += [ led0.eq(self.wishbone_slave_sys.stb),
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# led1.eq(self.wishbone_slave_sys.cyc), ]
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burst_size=4
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data_width = burst_size * 4
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@ -407,9 +447,7 @@ class NuBusFPGA(SoCCore):
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("dmaaddress", 32),
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]
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self.submodules.tosbus_fifo = ClockDomainsRenamer({"read": "nubus", "write": "sys"})(AsyncFIFOBuffered(width=layout_len(self.tosbus_layout), depth=1024//data_width))
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self.submodules.fromsbus_fifo = ClockDomainsRenamer({"write": "nubus", "read": "sys"})(AsyncFIFOBuffered(width=layout_len(self.fromsbus_layout), depth=512//data_width))
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self.submodules.fromsbus_req_fifo = ClockDomainsRenamer({"read": "nubus", "write": "sys"})(AsyncFIFOBuffered(width=layout_len(self.fromsbus_req_layout), depth=512//data_width))
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irq_line = self.platform.request("nmrq_3v3_n") # active low
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fb_irq = Signal(reset = 1) # active low
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dma_irq = Signal(reset = 1) # active low
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@ -422,7 +460,13 @@ class NuBusFPGA(SoCCore):
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#]
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self.comb += irq_line.eq(fb_irq & dma_irq & audio_irq) # active low, enable if one is low
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self.submodules.tosbus_fifo = ClockDomainsRenamer({"read": "nubus", "write": "sys"})(AsyncFIFOBuffered(width=layout_len(self.tosbus_layout), depth=1024//data_width))
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self.submodules.fromsbus_fifo = ClockDomainsRenamer({"write": "nubus", "read": "sys"})(AsyncFIFOBuffered(width=layout_len(self.fromsbus_layout), depth=512//data_width))
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self.submodules.fromsbus_req_fifo = ClockDomainsRenamer({"read": "nubus", "write": "sys"})(AsyncFIFOBuffered(width=layout_len(self.fromsbus_req_layout), depth=512//data_width))
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#if (not sdcard): # fixme: temporay exclusion
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self.submodules.exchange_with_mem = ExchangeWithMem(soc=self,
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platform=platform,
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tosbus_fifo=self.tosbus_fifo,
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@ -434,8 +478,20 @@ class NuBusFPGA(SoCCore):
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burst_size=burst_size,
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do_checksum = False,
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clock_domain="nubus")
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self.comb += dma_irq.eq(self.exchange_with_mem.irq)
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#else:
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# self.add_sdcard_custom()
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# self.submodules.exchange_with_sd = ExchangeWithSD(soc=self,
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# platform=platform,
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# tosbus_fifo=self.tosbus_fifo,
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# fromsbus_fifo=self.fromsbus_fifo,
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# fromsbus_req_fifo=self.fromsbus_req_fifo,
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# sd_source=self.sdcore.source,
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# sd_sink=self.sdcore.sink,
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# burst_size=burst_size,
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# clock_domain="nubus")
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# self.comb += dma_irq.eq(self.exchange_with_sd.irq)
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self.submodules.nubus = nubus_full_unified.NuBus(soc=self,
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version=version,
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@ -491,13 +547,17 @@ class NuBusFPGA(SoCCore):
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self.add_ram("goblin_accel_rom", origin=self.mem_map["goblin_accel_rom"], size=rounded_goblin_rom_len, contents=goblin_rom_data, mode="r")
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self.add_ram("goblin_accel_ram", origin=self.mem_map["goblin_accel_ram"], size=2**12, mode="rw")
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if (ethernet):
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# we need the CRG to provide the cd_eth clock: "use refclk_cd as RMII reference clock (provided by user design) (no external clock).
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self.ethphy = LiteEthPHYRMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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self.add_ethernet(phy=self.ethphy, data_width = 32)
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print(f"%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% {self.ethmac.interface.sram.ev.irq}") # FIXME HANDLEME
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if (sdcard):
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self.add_sdcard()
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# irq?
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if (ethernet):
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# we need the CRG to provide the cd_eth clock: "use refclk_cd as RMII reference clock (provided by user design) (no external clock).
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self.ethphy = LiteEthPHYRMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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self.add_ethernet(phy=self.ethphy, data_width = 32)
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print(f"%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% {self.ethmac.interface.sram.ev.irq}") # FIXME HANDLEME
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# for testing
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if (False):
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@ -515,14 +575,28 @@ def main():
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parser.add_argument("--goblin", action="store_true", help="add a goblin framebuffer")
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parser.add_argument("--hdmi", action="store_true", help="The framebuffer uses HDMI (default to VGA, required for V1.2)")
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parser.add_argument("--goblin-res", default="640x480@60Hz", help="Specify the goblin resolution")
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parser.add_argument("--sdcard", action="store_true", help="add a sdcard controller (V1.2 only)")
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parser.add_argument("--flash", action="store_true", help="add a Flash device [V1.2+FLASHTEMP PMod]")
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parser.add_argument("--ethernet", action="store_true", help="Add Ethernet (V1.2 w/ custom PMod only)")
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builder_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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if (args.sdcard and (args.version == "V1.0")):
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print(" ***** ERROR ***** : Ethernet not supported on V1.0\n");
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assert(False)
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if (args.flash and (args.version == "V1.0")):
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print(" ***** ERROR ***** : Flash not supported on V1.0\n");
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assert(False)
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if (args.ethernet and (args.version == "V1.0")):
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print(" ***** ERROR ***** : Ethernet not supported on V1.0\n");
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assert(False)
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if (args.ethernet and args.flash):
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print(" ***** ERROR ***** : Only one PMod usable on V1.2\n");
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assert(False)
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if ((not args.hdmi) and (args.version == "V1.2")):
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print(" ***** ERROR ***** : VGA not supported on V1.2\n");
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@ -535,6 +609,8 @@ def main():
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goblin=args.goblin,
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hdmi=args.hdmi,
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goblin_res=args.goblin_res,
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sdcard=args.sdcard,
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flash=args.flash,
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ethernet=args.ethernet)
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version_for_filename = args.version.replace(".", "_")
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@ -214,17 +214,30 @@ connectors_v1_2 = [
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("P1", "M1 L1 N2 N1 R2 P2 T1 R1 P4 P3 P5 N5"), # check sequence! currently in pmod-* order
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]
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# Extension
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def flashtemp_pmod_io(pmod):
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return [
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# completely inconsistent with the SBus entry as P1 is in a different order...
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("spiflash4x", 0,
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Subsignal("cs_n", Pins(f"{pmod}:2")),
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Subsignal("clk", Pins(f"{pmod}:5")),
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Subsignal("dq", Pins(f"{pmod}:7 {pmod}:4 {pmod}:6 {pmod}:3")),
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IOStandard("LVCMOS33")
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),
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]
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_flashtemp_pmod_io_v1_2 = flashtemp_pmod_io("P1")
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# Ethernet ----------------------------------------------------------------------------------------------
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# custom not-quite-pmod
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def rmii_eth_extpmod_io(extpmod):
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return [
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("eth_clocks", 0,
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Subsignal("ref_clk", Pins(f"{extpmod}:10")),
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Subsignal("ref_clk", Pins(f"{extpmod}:8")),
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IOStandard("LVCMOS33"),
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),
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("eth", 0,
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Subsignal("rst_n", Pins(f"{extpmod}:3")),
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Subsignal("rx_data", Pins(f"{extpmod}:8 {extpmod}:11")),
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Subsignal("rx_data", Pins(f"{extpmod}:11 {extpmod}:10")),
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Subsignal("crs_dv", Pins(f"{extpmod}:6")),
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Subsignal("tx_en", Pins(f"{extpmod}:2")),
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Subsignal("tx_data", Pins(f"{extpmod}:0 {extpmod}:1")),
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