Romain Dolbeau
|
07c70f0731
|
3D
|
2023-03-26 11:49:10 +02:00 |
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Romain Dolbeau
|
90408c748c
|
even more JLCPCB BoM optimization
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2023-03-26 11:46:25 +02:00 |
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Romain Dolbeau
|
c7a9bf620d
|
thinking out loud, not relevant to NuBus
|
2023-03-26 11:44:51 +02:00 |
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Romain Dolbeau
|
ef12c60dcb
|
upd
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2023-03-26 11:44:12 +02:00 |
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Romain Dolbeau
|
7c970780f3
|
more JLCPCB BoM optimization
|
2023-03-18 13:31:35 +01:00 |
|
Romain Dolbeau
|
08ca99092f
|
some BoM optimization
|
2023-03-18 11:54:30 +01:00 |
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Romain Dolbeau
|
4273f41847
|
mising file for SW SDRAM Init
|
2023-01-29 09:17:24 +01:00 |
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Romain Dolbeau
|
0b7ccab573
|
mising file for SW SDRAM Init
|
2023-01-29 09:17:18 +01:00 |
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Romain Dolbeau
|
b2ef57a8dc
|
move SDRAM init from HW to SW
|
2023-01-27 22:25:12 +01:00 |
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Romain Dolbeau
|
42c0a18371
|
track V1.2 pcb update
|
2023-01-14 11:03:01 +01:00 |
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Romain Dolbeau
|
5585709334
|
update
|
2023-01-14 11:00:01 +01:00 |
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Romain Dolbeau
|
8981ce5bc6
|
update satus
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2023-01-12 19:29:42 +01:00 |
|
Romain Dolbeau
|
873e185cc3
|
HW mono support
|
2023-01-11 22:41:43 +01:00 |
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Romain Dolbeau
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ca779f3d26
|
8-bits support
|
2023-01-10 23:14:02 +01:00 |
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Romain Dolbeau
|
8ecda4c1d8
|
submodule for HDMI-Alt
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2023-01-08 15:30:56 +01:00 |
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Romain Dolbeau
|
d0b44c8143
|
HDMI Audio
|
2023-01-08 15:11:22 +01:00 |
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Romain Dolbeau
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06c7d389a2
|
Merge branch 'master' of github.com:rdolbeau/NuBusFPGA
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2022-12-20 08:20:16 +01:00 |
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Romain Dolbeau
|
149ac2fcef
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preliminary support for the hdl-util/hdmi contorller as an alternative
|
2022-12-20 08:19:41 +01:00 |
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Romain Dolbeau
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b32bd64923
|
Merge branch 'master' of github.com:rdolbeau/NuBusFPGA
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2022-12-11 17:05:30 +01:00 |
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Romain Dolbeau
|
13d0e6519c
|
get ns816-declrom as a submodule, add auto-buidling of nubus_checksum
|
2022-12-11 17:00:58 +01:00 |
|
Romain Dolbeau
|
b54c08ef46
|
Smaller via, greater power/gnd clearance
|
2022-12-01 23:55:06 +01:00 |
|
Romain Dolbeau
|
531c77ac81
|
BoM, power plane, serial back to THT, ...
|
2022-12-01 23:12:30 +01:00 |
|
Romain Dolbeau
|
91bfcca0a3
|
Merge branch 'master' of github.com:rdolbeau/NuBusFPGA
|
2022-11-18 19:32:40 +01:00 |
|
Romain Dolbeau
|
7172cdecef
|
minor cleanups
|
2022-11-18 19:32:34 +01:00 |
|
Romain Dolbeau
|
62f01c463b
|
note on V1.0 vs. V1.2
|
2022-11-18 17:47:03 +01:00 |
|
Romain Dolbeau
|
3434158dab
|
update common
|
2022-11-18 17:36:47 +01:00 |
|
Romain Dolbeau
|
e0f5d2e50b
|
update readme
|
2022-11-18 17:35:23 +01:00 |
|
Romain Dolbeau
|
5a21397887
|
update
|
2022-11-18 16:46:00 +01:00 |
|
Romain Dolbeau
|
0408bee291
|
more THT->SMT, lexx expensive parts/assembly (?)
|
2022-11-13 14:21:11 +01:00 |
|
Romain Dolbeau
|
12624eca94
|
rounded cutouts...
|
2022-11-12 12:44:01 +01:00 |
|
Romain Dolbeau
|
a3d0514ce2
|
full BOM
|
2022-11-12 11:48:47 +01:00 |
|
Romain Dolbeau
|
f04a5cb94f
|
more update to V1.2 to try to limit cost
|
2022-11-12 11:42:40 +01:00 |
|
Romain Dolbeau
|
b1720f45bb
|
more JTAG from TH to SMD
|
2022-11-12 11:42:40 +01:00 |
|
Romain Dolbeau
|
aacb0f1caa
|
comments
|
2022-11-05 14:59:33 +01:00 |
|
Romain Dolbeau
|
8ed2e15222
|
merge sampling a not-sampling to avoid code duplication
|
2022-11-05 14:54:35 +01:00 |
|
Romain Dolbeau
|
22d663b050
|
Merge branch 'master' of github.com:rdolbeau/NuBusFPGA
|
2022-11-05 07:37:49 +01:00 |
|
Romain Dolbeau
|
597b922d9d
|
relative lib
|
2022-11-05 07:37:40 +01:00 |
|
Romain Dolbeau
|
35beaf2c6a
|
missing lib
|
2022-11-05 07:35:12 +01:00 |
|
Romain Dolbeau
|
b988cee925
|
commit patch for newer Litex
|
2022-11-04 09:28:55 +01:00 |
|
Romain Dolbeau
|
036ce0a3ce
|
support both version for now
|
2022-11-01 15:42:59 +01:00 |
|
Romain Dolbeau
|
4c2eb5f6d2
|
split
|
2022-11-01 15:35:31 +01:00 |
|
Romain Dolbeau
|
5e106ee084
|
renames
|
2022-11-01 15:34:02 +01:00 |
|
Romain Dolbeau
|
d3746505d0
|
renames files to V1_2
|
2022-11-01 15:31:34 +01:00 |
|
Romain Dolbeau
|
4ab5382a2f
|
arbiter source file needed
|
2022-11-01 14:54:29 +01:00 |
|
Romain Dolbeau
|
d52bda7883
|
fix V1.2 TB
|
2022-11-01 14:37:20 +01:00 |
|
Romain Dolbeau
|
b7a941e61b
|
typo
|
2022-11-01 14:36:46 +01:00 |
|
Romain Dolbeau
|
93e7cd20c1
|
typos
|
2022-11-01 12:41:58 +01:00 |
|
Romain Dolbeau
|
b621ee2eb5
|
draft integration of CPLD in FPGA - can't have internal tri-state signals...
|
2022-11-01 11:36:51 +01:00 |
|
Romain Dolbeau
|
15a6d9cfc1
|
typo
|
2022-11-01 11:34:06 +01:00 |
|
Romain Dolbeau
|
9ce702debb
|
update xdc
|
2022-11-01 09:45:57 +01:00 |
|