Macintosh-HW/NuBusFPGA
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191 Commits

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Author SHA1 Message Date
Romain Dolbeau
c0fbdca5d3 preliminary burst support for DMA 2022-07-14 17:17:53 +02:00
Romain Dolbeau
5e7e7d5e2c 'back'port superslot to non-sampling NuBus interface 2022-07-14 09:34:29 +02:00
Romain Dolbeau
d7a344555e dCtlDevBase might be empty, but dCtlSlot is fine... 2022-07-14 09:33:15 +02:00
Romain Dolbeau
3f3371a054 fix messed up timing... 2022-07-14 08:54:23 +02:00
Romain Dolbeau
7913f6bced upadte README 2022-06-26 13:27:33 +02:00
Romain Dolbeau
363dd56600 checking in slot 2022-06-26 13:22:12 +02:00
Romain Dolbeau
c6d6e26438 detect slot in INIT; detect slot in RAMDsk driver ; auto-mount RAMDDsk 2022-06-26 12:31:43 +02:00
Romain Dolbeau
724d4406f9 better patterns 2022-06-25 12:54:10 +02:00
Romain Dolbeau
733f446b27 HW-acceel big pattern (not sure about alignment...), add basic Icon w/ ShowInitIcon 2022-06-25 08:51:17 +02:00
Romain Dolbeau
173c87ea02 LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650 2022-06-24 23:37:18 +02:00
Romain Dolbeau
2d2cbdbafe update ioRange; it doesn't actually affect the cache, only the MMU which we don't use... 2022-06-12 13:46:58 +02:00
Romain Dolbeau
972f628e80 use some custom RLE to initiliaze the RAM disk with a valid HFS FS. Still doesn't mount at boot though. 2022-06-12 13:45:41 +02:00
Romain Dolbeau
2000161727 in _sampling, map whole SDRAm in superslot and use the first 248 Mib as a RAM disk with driver in the DeclRom 2022-06-07 23:05:08 +02:00
Romain Dolbeau
9b9f0efb6e draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel 2022-06-06 23:36:43 +02:00
Romain Dolbeau
9d4fbadbd4 commit current Vex config 2022-06-05 18:04:00 +02:00
Romain Dolbeau
94cd6a9411 Move Vex to a 128-bit Wishbone, and add a bypass to access a dedicated memory port with a 128-bits datapath. Speeds up scrolling quite nicely. 2022-06-05 18:03:23 +02:00
Romain Dolbeau
d9c21e7abb stat module 2022-06-04 18:56:41 +02:00
Romain Dolbeau
85c62fb331 new interface 2022-06-04 17:25:58 +02:00
Romain Dolbeau
76c29d5b69 accel in 16/32 ; includes adding MUL to Vex & fixing a FIFO overrun in NuBus in 32 bits mode 2022-06-04 14:55:40 +02:00
Romain Dolbeau
9a50f36153 add a byte-reversed access mode to accel registers, avoid the byte-reverse on the host 2022-06-04 11:11:28 +02:00
Romain Dolbeau
fbcfe3152c DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus 2022-06-04 09:53:09 +02:00
Romain Dolbeau
6271ddbef8 pingmaster sort-of-work 2022-05-30 19:06:33 +02:00
Romain Dolbeau
3a52ab666f buffers (fifo) write from NuBus to Wishbone, to improve write BW 2022-05-30 13:15:20 +02:00
Romain Dolbeau
c8e8113c81 preliminary support for pattern-to-screen, reusing single-byte rectfill 2022-05-16 16:40:05 +02:00
Romain Dolbeau
607832abc0 struct-based access to stack 2022-05-16 14:11:35 +02:00
Romain Dolbeau
d53a70ba9e Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag) 2022-05-15 14:43:15 +02:00
Romain Dolbeau
f867f02c83 add 16-bits/thousands of colors 2022-04-22 23:00:25 +02:00
Romain Dolbeau
44fa491540 C secondary, add rsrc directory w/o assembly 2022-04-19 23:31:31 +02:00
Romain Dolbeau
3be6333be7 32-bits 'mllions of colors' 2022-04-18 17:04:32 +02:00
Romain Dolbeau
e2994879bc 1/2/4/8 bit support 2022-04-18 14:10:17 +02:00
Romain Dolbeau
8a3e58a75c try for 1/8 bpp support in rom/drvr 2022-04-18 11:51:07 +02:00
Romain Dolbeau
b5a718a2b5 new picture 2022-04-17 11:53:03 +02:00
Romain Dolbeau
62b2c48b32 update to first tested version 2022-04-17 11:25:48 +02:00
Romain Dolbeau
de1aaf8161 some missing stuff, minor HW update, SW 2022-02-05 15:32:44 +01:00
Romain Dolbeau
68e63497af more updates 2022-01-29 11:03:47 +01:00
Romain Dolbeau
2d50954892 large clean-up update 2022-01-15 12:42:19 +01:00
Romain Dolbeau
9297c355ed Switch from 5V 74FCT245 to 3.3V 74LVT245 2022-01-09 18:19:49 +01:00
Romain Dolbeau
6e18af0035 another update after discussion on tinkerdifferent 2022-01-09 17:57:34 +01:00
Romain Dolbeau
b664739ba2 large update 2022-01-09 11:39:59 +01:00
Romain Dolbeau
a040aba8e0
typos 2021-12-21 08:27:11 +01:00
Romain Dolbeau
5f0bc43139 push to github 2021-12-21 08:26:30 +01:00