38 Commits

Author	SHA1	Message	Date
Romain Dolbeau	b2ef57a8dc	move SDRAM init from HW to SW	2023-01-27 22:25:12 +01:00
Romain Dolbeau	42c0a18371	track V1.2 pcb update	2023-01-14 11:03:01 +01:00
Romain Dolbeau	d0b44c8143	HDMI Audio	2023-01-08 15:11:22 +01:00
Romain Dolbeau	149ac2fcef	preliminary support for the hdl-util/hdmi contorller as an alternative	2022-12-20 08:19:41 +01:00
Romain Dolbeau	aacb0f1caa	comments	2022-11-05 14:59:33 +01:00
Romain Dolbeau	8ed2e15222	merge sampling a not-sampling to avoid code duplication	2022-11-05 14:54:35 +01:00
Romain Dolbeau	b988cee925	commit patch for newer Litex	2022-11-04 09:28:55 +01:00
Romain Dolbeau	036ce0a3ce	support both version for now	2022-11-01 15:42:59 +01:00
Romain Dolbeau	d3746505d0	renames files to V1_2	2022-11-01 15:31:34 +01:00
Romain Dolbeau	4ab5382a2f	arbiter source file needed	2022-11-01 14:54:29 +01:00
Romain Dolbeau	93e7cd20c1	typos	2022-11-01 12:41:58 +01:00
Romain Dolbeau	f0a6a4643f	move blit_goblin to common	2022-10-31 16:38:29 +01:00
Romain Dolbeau	86fd0d5c18	more stuff moved to common	2022-10-31 15:58:47 +01:00
Romain Dolbeau	f2da1f1163	move goblin to common	2022-10-31 15:45:24 +01:00
Romain Dolbeau	239b74823f	move to submodules XiBus	2022-10-31 15:28:08 +01:00
Romain Dolbeau	c3ec10e2dd	named parameters for more compatibility	2022-10-09 09:02:30 +02:00
Romain Dolbeau	c08acd77ed	DMA + IRQ for RAM Disk	2022-10-08 18:23:01 +02:00
Romain Dolbeau	6040bca13a	refactor ram dsk driver a bit more, some work toward multiplexed interrupt	2022-10-08 10:39:18 +02:00
Romain Dolbeau	be8a2ec995	sampling more configurable	2022-09-21 23:06:17 +02:00
Romain Dolbeau	71d88bfb61	better goblin (+accel) in SBus	2022-08-15 10:20:56 +02:00
Romain Dolbeau	d70ba3e434	rename blit to blit_goblin	2022-07-23 12:58:13 +02:00
Romain Dolbeau	abdb178089	trying to debug DMA for RAMDsk	2022-07-23 12:53:30 +02:00
Romain Dolbeau	c0fbdca5d3	preliminary burst support for DMA	2022-07-14 17:17:53 +02:00
Romain Dolbeau	5e7e7d5e2c	'back'port superslot to non-sampling NuBus interface	2022-07-14 09:34:29 +02:00
Romain Dolbeau	9b9f0efb6e	draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel	2022-06-06 23:36:43 +02:00
Romain Dolbeau	94cd6a9411	Move Vex to a 128-bit Wishbone, and add a bypass to access a dedicated memory port with a 128-bits datapath. Speeds up scrolling quite nicely.	2022-06-05 18:03:23 +02:00
Romain Dolbeau	d9c21e7abb	stat module	2022-06-04 18:56:41 +02:00
Romain Dolbeau	fbcfe3152c	DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus	2022-06-04 09:53:09 +02:00
Romain Dolbeau	6271ddbef8	pingmaster sort-of-work	2022-05-30 19:06:33 +02:00
Romain Dolbeau	3a52ab666f	buffers (fifo) write from NuBus to Wishbone, to improve write BW	2022-05-30 13:15:20 +02:00
Romain Dolbeau	d53a70ba9e	Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag)	2022-05-15 14:43:15 +02:00
Romain Dolbeau	f867f02c83	add 16-bits/thousands of colors	2022-04-22 23:00:25 +02:00
Romain Dolbeau	3be6333be7	32-bits 'mllions of colors'	2022-04-18 17:04:32 +02:00
Romain Dolbeau	62b2c48b32	update to first tested version	2022-04-17 11:25:48 +02:00
Romain Dolbeau	de1aaf8161	some missing stuff, minor HW update, SW	2022-02-05 15:32:44 +01:00
Romain Dolbeau	68e63497af	more updates	2022-01-29 11:03:47 +01:00
Romain Dolbeau	b664739ba2	large update	2022-01-09 11:39:59 +01:00
Romain Dolbeau	5f0bc43139	push to github	2021-12-21 08:26:30 +01:00