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cb5d09df4d
@ -10,7 +10,7 @@ This project was 'spun off' the [SBusFPGA](https://github.com/rdolbeau/SBusFPGA)
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## Current status
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First prototype is working in a Quadra 650, running MacOS 8.1. It implements a single-screen-resolution, windowboxed multi-resolution, depth-switchable (1/2/4/8/16/32 bits) framebuffer over DVI-in-HDMI-connector (will work with any HDMI-compliant monitor). The framebuffer can be used as secondary/primary/only framebuffer in the machine running OS8.1. Qemu tests indicate this should work with 7.1 & 7.5/7.6 as well. An alternate HDMI PHY also supports audio, enabled as a 8/16 bits, mono/stereo, 44.1 kHz output component in MacOS.
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First prototype is working in a Quadra 650, running MacOS 8.1. It implements a single-screen-resolution, windowboxed multi-resolution, depth-switchable (1/2/4/8/16/32 bits) framebuffer over DVI-in-HDMI-connector (will work with any HDMI-compliant monitor). The framebuffer can be used as secondary/primary/only framebuffer in the machine running OS8.1. Qemu tests indicate this should work with 7.1 & 7.5/7.6 as well. An alternate HDMI PHY also supports audio, enabled as a 8/16 bits, mono/stereo, 44.1 Hz output compoenent in MacOS.
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Some basic acceleration now exists for 8/16/32 bits, doing rectangle screen-to-screen blits and pattern rectangle fills. 1/2/4 bits also has some acceleration, but only for byte-aligned cases.
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@ -17,10 +17,6 @@ APPLEINCS=${NS816DECLROMDIR}/atrap.inc ${NS816DECLROMDIR}/declrom.inc ${NS816DEC
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HRES=1920
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VRES=1080
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QEMU=no
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ifeq ($(QEMU),yes)
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CFLAGS+=-DQEMU
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endif
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CSRC_VIDEO=NuBusFPGADrvr_OpenClose.c NuBusFPGADrvr_Ctrl.c NuBusFPGADrvr_Status.c NuBusFPGAPrimaryInit_Primary.c NuBusFPGAPrimaryInit_RamInit.c NuBusFPGASecondaryInit_Secondary.c
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CSRC_RAMDSK=NuBusFPGARAMDskDrvr_OpenClose.c NuBusFPGARAMDskDrvr_Ctrl.c NuBusFPGARAMDskDrvr_Prime.c NuBusFPGARAMDskDrvr_Status.c myrle.c
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@ -34,10 +34,8 @@ UInt32 Primary(SEBlock* seblock) {
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vres = __builtin_bswap32((UInt32)PRIM_READREG(GOBOFB_VRES)); // fixme: endianness
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/* initialize DRAM controller */
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#ifndef QEMU
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sdram_init(a32);
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#endif
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/* grey the screen */
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/* should switch to HW ? */
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a32_l0 = a32;
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@ -269,7 +269,7 @@ int main(int argc, char **argv) {
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fprintf(fd, "\tOSLstEntry\tsRsrc_GoboFB_R%hux%hu,_sRsrc_GoboFB_R%hux%hu/* video sRsrc List */\n", hres, vres, hres, vres);
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}
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}
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fprintf(fd, "\tOSLstEntry\tsRsrc_RAMDsk,_sRsrc_RAMDsk\n");
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//fprintf(fd, "\tOSLstEntry\tsRsrc_RAMDsk,_sRsrc_RAMDsk\n");
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fprintf(fd, "\tOSLstEntry\tsRsrc_HDMIAudio,_sRsrc_HDMIAudio\n");
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fprintf(fd, "\tDatLstEntry endOfList, 0\n");
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@ -1 +1 @@
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Subproject commit 9e350c5962f1dc8f43091a3f44a7c1f8071d2bff
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Subproject commit f93c95ba1eda007ffce0cf5f9c5a3421afbcfdc6
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@ -2,7 +2,7 @@
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source /opt/Xilinx/Vivado/2020.1/settings64.sh
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export LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2020.1/lib/lnx64.o/SuSE
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python3 nubus_to_fpga_soc.py --build --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6 --goblin --goblin-res 1920x1080@60Hz --hdmi # --ethernet
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python3 nubus_to_fpga_soc.py --build --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6 --goblin --goblin-res 1920x1080@60Hz --hdmi
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#python3 nubus_to_fpga_soc.py --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6
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@ -20,13 +20,12 @@ class NuBus(Module):
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#led1 = platform.request("user_led", 1)
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if (usesampling):
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# when using 'sampling', the NuBus clock is sampled at sys_clk frequency instead of used directly
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# the other signals are still sampled synchronously, and the buffer used from sysclk afterwards
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# when using 'sampling', the NuBus signals are sampled at sys_clk frequency instead of synchronously using nubus_clk
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# I'm not completely sure about timings, but in practice it seems to work...
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# The major benefit is that when a read is detected, it is sent to the Wishbone synchronously as the signals are already in sys_clk
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# And when Wishbone answers, we just wait for the next detected NuBus edge to answer
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# It significantly improves read latency
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# Writes don't see the same improvement, as they always are fire-and-forget in a FIFO anyway
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# Writes don't see the same improvement, are they always are fire-and-forget in a FIFO anyway
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nub_clk = ClockSignal(cd_nubus)
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nub_resetn = ~ResetSignal(cd_nubus)
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nub_clk_prev_bits = 4 # how many cycles after posedge do we still dare set some signals (i.e. still before setup time before negedge)
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@ -40,16 +39,10 @@ class NuBus(Module):
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self.sync += [
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nub_clk_prev[i].eq(nub_clk_prev[i-1]) for i in range(1, nub_clk_prev_bits)
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]
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#self.sync += [
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# nub_clk_negedge.eq(~nub_clk & nub_clk_prev[0]),
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# nub_clk_posedge.eq( nub_clk & ~nub_clk_prev[0]),
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# nub_clk_insetup.eq( nub_clk & (nub_clk_prev != ((2**nub_clk_prev_bits)-1))), # if one of the previous X cycles is zero, we're early enough to set up signals
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#]
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# this should use double sampling; however using [1] and [2] break, perhaps the detection is too late?
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self.comb += [
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nub_clk_negedge.eq(~nub_clk_prev[0] & nub_clk_prev[1]),
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nub_clk_posedge.eq( nub_clk_prev[0] & ~nub_clk_prev[1]),
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nub_clk_insetup.eq( nub_clk_prev[0] & (nub_clk_prev[1:nub_clk_prev_bits] != ((2**(nub_clk_prev_bits-1))-1))), # if one of the previous X cycles is zero, we're early enough to set up signals
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self.sync += [
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nub_clk_negedge.eq(~nub_clk & nub_clk_prev[0]),
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nub_clk_posedge.eq( nub_clk & ~nub_clk_prev[0]),
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nub_clk_insetup.eq( nub_clk & (nub_clk_prev != ((2**nub_clk_prev_bits)-1))), # if one of the previous X cycles is zero, we're early enough to set up signals
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]
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# Signals for tri-stated nubus access
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@ -155,34 +148,66 @@ class NuBus(Module):
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write_fifo_din = Record(write_fifo_layout)
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self.comb += write_fifo.din.eq(write_fifo_din.raw_bits())
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# nubus-synchronous sampling (in Verilog for negedge)
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self.specials += Instance("nubus_sampling",
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i_nub_clkn = ClockSignal(cd_nubus),
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i_nub_resetn = ~ResetSignal(cd_nubus),
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i_nub_tm0n = tm0_i_n,
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i_nub_tm1n = tm1_i_n,
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i_nub_startn = start_i_n,
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i_nub_rqstn = rqst_i_n,
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i_nub_ackn = ack_i_n,
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i_nub_adn = ad_i_n,
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o_tm0 = sampled_tm0,
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o_tm1 = sampled_tm1,
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o_start = sampled_start,
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o_rqst = sampled_rqst,
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o_ack = sampled_ack,
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o_ad = sampled_ad,
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o_sel = decoded_sel,
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o_block = decoded_block,
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o_busy = decoded_busy,
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)
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if (usesampling):
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# sys_clk sampling of the nubus signals
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self.sync += [
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#If((~nub_clk & nub_clk_prev[0]), # simultaneous with setting negedge
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If(nub_clk_negedge,
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sampled_tm0.eq(~tm0_i_n),
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sampled_tm1.eq(~tm1_i_n),
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sampled_start.eq(~start_i_n),
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sampled_rqst.eq(~rqst_i_n),
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sampled_ack.eq(~ack_i_n),
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sampled_ad.eq(~ad_i_n),
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)
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]
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self.comb += [
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decoded_block.eq(sampled_ad[1] & ~sampled_ad[0] & ~sampled_tm0), # 1x block write or 1x block read
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decoded_sel[3].eq(sampled_tm1 & sampled_ad[1] & sampled_ad[0] & sampled_tm0 # Byte 3
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| sampled_tm1 & sampled_ad[1] & sampled_ad[0] & ~sampled_tm0 # Half 1
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| sampled_tm1 & ~sampled_ad[1] & ~sampled_ad[0] & ~sampled_tm0 # Word
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),
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decoded_sel[2].eq(sampled_tm1 & sampled_ad[1] & ~sampled_ad[0] & sampled_tm0 # Byte 2
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| sampled_tm1 & sampled_ad[1] & sampled_ad[0] & ~sampled_tm0 # Half 1
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| sampled_tm1 & ~sampled_ad[1] & ~sampled_ad[0] & ~sampled_tm0 # Word
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),
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decoded_sel[1].eq(sampled_tm1 & ~sampled_ad[1] & sampled_ad[0] & sampled_tm0 # Byte 1
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| sampled_tm1 & ~sampled_ad[1] & sampled_ad[0] & ~sampled_tm0 # Half 0
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| sampled_tm1 & ~sampled_ad[1] & ~sampled_ad[0] & ~sampled_tm0 # Word
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),
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decoded_sel[0].eq(sampled_tm1 & ~sampled_ad[1] & ~sampled_ad[0] & sampled_tm0 # Byte 0
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| sampled_tm1 & ~sampled_ad[1] & sampled_ad[0] & ~sampled_tm0 # Half 0
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| sampled_tm1 & ~sampled_ad[1] & ~sampled_ad[0] & ~sampled_tm0 # Word
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),
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]
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else:
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# nubus-synchronous sampling (in Verilog for negedge)
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self.specials += Instance("nubus_sampling",
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i_nub_clkn = ClockSignal(cd_nubus),
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i_nub_resetn = ~ResetSignal(cd_nubus),
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i_nub_tm0n = tm0_i_n,
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i_nub_tm1n = tm1_i_n,
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i_nub_startn = start_i_n,
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i_nub_rqstn = rqst_i_n,
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i_nub_ackn = ack_i_n,
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i_nub_adn = ad_i_n,
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o_tm0 = sampled_tm0,
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o_tm1 = sampled_tm1,
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o_start = sampled_start,
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o_rqst = sampled_rqst,
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o_ack = sampled_ack,
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o_ad = sampled_ad,
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o_sel = decoded_sel,
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o_block = decoded_block,
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o_busy = decoded_busy,
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)
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self.read_ctr = read_ctr = Signal(32)
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self.writ_ctr = writ_ctr = Signal(32)
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if (usesampling):
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# ############# usesampling FSM
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self.submodules.slave_fsm = slave_fsm = FSM(reset_state="Reset")
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slave_fsm.act("Reset",
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NextState("Idle")
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@ -299,9 +324,7 @@ class NuBus(Module):
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ack_o_n.eq(0),
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NextState("Idle"),
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)
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# ############# end of usesampling FSM
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else:
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# ############# non-usesampling FSM
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self.submodules.slave_fsm = slave_fsm = ClockDomainsRenamer(cd_nubus)(FSM(reset_state="Reset"))
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slave_fsm.act("Reset",
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NextState("Idle")
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@ -358,7 +381,6 @@ class NuBus(Module):
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NextState("Idle"),
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)
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)
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# ############# end of non-usesampling FSM
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# connect the write FIFO inputs
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self.comb += [ write_fifo_din.adr.eq(current_adr), # recorded
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@ -699,15 +721,13 @@ class NuBus(Module):
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nub_adn = platform.request("ad_3v3_n") # V1.0: from CPLD ; V1.2: from shifters
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nub_idn = platform.request("id_3v3_n") # V1.0: from CPLD (4 bits) ; V1.2: from shifters (3 bits, /ID3 is always 0)
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# idem between V1.0 and V1.2
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self.specials += Tristate(nub_adn, ad_o_n, ad_oe, ad_i_n)
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# Tri-state
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if (version == "V1.0"):
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# tri-state communication with CPLD
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self.specials += Tristate(nub_tm0n, tm0_o_n, tmo_oe, tm0_i_n)
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self.specials += Tristate(nub_tm1n, tm1_o_n, tmo_oe, tm1_i_n)
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self.specials += Tristate(nub_ackn, ack_o_n, tmo_oe, ack_i_n)
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self.specials += Tristate(nub_adn, ad_o_n, ad_oe, ad_i_n)
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self.specials += Tristate(nub_startn, start_o_n, master_oe, start_i_n)
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elif (version == "V1.2"):
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# input only
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@ -715,6 +735,7 @@ class NuBus(Module):
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tm0_i_n.eq(nub_tm0n),
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tm1_i_n.eq(nub_tm1n),
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ack_i_n.eq(nub_ackn),
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ad_i_n.eq(nub_adn),
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start_i_n.eq(nub_startn),
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]
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else:
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@ -766,7 +787,6 @@ class NuBus(Module):
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nf_grant = platform.request("grant") # V1.0: from cpld
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nf_nubus_master_dir = platform.request("nubus_master_dir") # V1.0: to cpld
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nf_fpga_to_cpld_signal = platform.request("fpga_to_cpld_signal") # V1.0: to cpld, 'rqstoen'
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# NuBus90 signals, , for completeness
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nub_clk2xn = ClockSignal(cd_nubus90)
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@ -780,9 +800,20 @@ class NuBus(Module):
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nf_fpga_to_cpld_signal.eq(~rqst_oe),
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]
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if (usesampling):
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self.sync += [
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If((~nub_clk & nub_clk_prev[0]), # simultaneous with setting negedge
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decoded_busy.eq(~decoded_busy & nub_ackn & ~nub_startn # beginning of transaction
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| decoded_busy & nub_ackn & nub_resetn), # hold during cycle
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)
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]
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if (version == "V1.2"):
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self.nubus_oe = nubus_oe = Signal() # improveme
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self.specials += Instance("nubus_cpldinfpga",
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i_nubus_oe = soc.hold_reset, # improveme, handled in SoC
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||||
i_nubus_oe = nubus_oe, # improveme: handled in soc
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i_tmoen = ~tmo_oe,
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i_nubus_master_dir = master_oe,
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i_rqst_oe_n = ~rqst_oe,
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@ -24,8 +24,6 @@ from litedram.phy import s7ddrphy
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from litedram.frontend.dma import *
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from liteeth.phy.rmii import LiteEthPHYRMII
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from migen.genlib.cdc import BusSynchronizer
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from migen.genlib.resetsync import AsyncResetSynchronizer
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@ -47,8 +45,7 @@ class _CRG(Module):
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||||
def __init__(self, platform, version, sys_clk_freq,
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goblin=False,
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hdmi=False,
|
||||
pix_clk=0,
|
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ethernet=False):
|
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pix_clk=0):
|
||||
self.clock_domains.cd_sys = ClockDomain() # 100 MHz PLL, reset'ed by NuBus (via pll), SoC/Wishbone main clock
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||||
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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@ -62,9 +59,7 @@ class _CRG(Module):
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||||
else:
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||||
self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
|
||||
if (ethernet):
|
||||
self.clock_domains.cd_eth = ClockDomain()
|
||||
|
||||
|
||||
|
||||
# # #
|
||||
clk48 = platform.request("clk48")
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@ -84,10 +79,9 @@ class _CRG(Module):
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||||
if (version == "V1.2"):
|
||||
self.clock_domains.cd_bank34 = ClockDomain()
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clk54 = platform.request("clk54")
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platform.add_platform_command("create_clock -name clk54 -period 18.51851851851851851 [get_nets clk54]")
|
||||
self.clk54_bufg = Signal()
|
||||
self.specials += Instance("BUFG", i_I=clk54, o_O=self.clk54_bufg)
|
||||
self.comb += self.cd_bank34.clk.eq(self.clk54_bufg)
|
||||
self.comb += self.cd_native.clk.eq(self.clk54_bufg)
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||||
else:
|
||||
clk54 = None
|
||||
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@ -124,11 +118,6 @@ class _CRG(Module):
|
||||
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
|
||||
platform.add_platform_command("create_generated_clock -name sys4x90clk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
|
||||
num_clk = num_clk + 1
|
||||
if (ethernet):
|
||||
pll.create_clkout(self.cd_eth, 50e6, phase=90) # fixme: what if sys_clk_feq != 100e6?
|
||||
platform.add_platform_command("create_generated_clock -name ethclk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
|
||||
num_clk = num_clk + 1
|
||||
|
||||
self.comb += pll.reset.eq(~rst_nubus_n) # | ~por_done
|
||||
platform.add_false_path_constraints(clk48, self.cd_nubus.clk) # FIXME?
|
||||
platform.add_false_path_constraints(self.cd_nubus.clk, clk48) # FIXME?
|
||||
@ -182,7 +171,7 @@ class _CRG(Module):
|
||||
|
||||
|
||||
class NuBusFPGA(SoCCore):
|
||||
def __init__(self, variant, version, sys_clk_freq, goblin, hdmi, goblin_res, ethernet, **kwargs):
|
||||
def __init__(self, variant, version, sys_clk_freq, goblin, hdmi, goblin_res, **kwargs):
|
||||
print(f"Building NuBusFPGA for board version {version}")
|
||||
|
||||
kwargs["cpu_type"] = "None"
|
||||
@ -194,9 +183,6 @@ class NuBusFPGA(SoCCore):
|
||||
|
||||
self.platform = platform = ztex213_nubus.Platform(variant = variant, version = version)
|
||||
|
||||
if (ethernet and (version == "V1.2")):
|
||||
platform.add_extension(ztex213_nubus._rmii_eth_extpmod_io_v1_2)
|
||||
|
||||
use_goblin_alt = True
|
||||
if ((not use_goblin_alt) or (not hdmi)):
|
||||
from VintageBusFPGA_Common.goblin_fb import goblin_rounded_size, Goblin
|
||||
@ -252,12 +238,11 @@ class NuBusFPGA(SoCCore):
|
||||
"goblin_audio_ram" : 0xF0920000, # audio for goblin (RAM buffers)
|
||||
"csr" : 0xF0A00000, # CSR
|
||||
"pingmaster": 0xF0B00000,
|
||||
"ethmac": 0xF0C00000,
|
||||
"rom": 0xF0FF8000, # ROM at the end (32 KiB of it ATM)
|
||||
#"END OF SLOT SPACE": 0xF0FFFFFF,
|
||||
}
|
||||
self.mem_map.update(wb_mem_map)
|
||||
self.submodules.crg = _CRG(platform=platform, version=version, sys_clk_freq=sys_clk_freq, goblin=goblin, hdmi=hdmi, pix_clk=litex.soc.cores.video.video_timings[goblin_res]["pix_clk"], ethernet=ethernet)
|
||||
self.submodules.crg = _CRG(platform=platform, version=version, sys_clk_freq=sys_clk_freq, goblin=goblin, hdmi=hdmi, pix_clk=litex.soc.cores.video.video_timings[goblin_res]["pix_clk"])
|
||||
|
||||
## add our custom timings after the clocks have been defined
|
||||
xdc_timings_filename = None;
|
||||
@ -335,7 +320,7 @@ class NuBusFPGA(SoCCore):
|
||||
#hold_reset_ctr = Signal(30, reset=960000000)
|
||||
hold_reset_ctr = Signal(5, reset=31)
|
||||
self.sync.native += If(hold_reset_ctr>0, hold_reset_ctr.eq(hold_reset_ctr - 1))
|
||||
self.hold_reset = hold_reset = Signal() # in reset if high, out-of-reset if low
|
||||
hold_reset = Signal()
|
||||
self.comb += hold_reset.eq(~(hold_reset_ctr == 0))
|
||||
pad_nubus_oe = platform.request("nubus_oe")
|
||||
self.comb += pad_nubus_oe.eq(hold_reset)
|
||||
@ -491,42 +476,25 @@ class NuBusFPGA(SoCCore):
|
||||
self.add_ram("goblin_accel_rom", origin=self.mem_map["goblin_accel_rom"], size=rounded_goblin_rom_len, contents=goblin_rom_data, mode="r")
|
||||
self.add_ram("goblin_accel_ram", origin=self.mem_map["goblin_accel_ram"], size=2**12, mode="rw")
|
||||
|
||||
if (ethernet):
|
||||
# we need the CRG to provide the cd_eth clock: "use refclk_cd as RMII reference clock (provided by user design) (no external clock).
|
||||
self.ethphy = LiteEthPHYRMII(
|
||||
clock_pads = self.platform.request("eth_clocks"),
|
||||
pads = self.platform.request("eth"))
|
||||
self.add_ethernet(phy=self.ethphy, data_width = 32)
|
||||
print(f"%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% {self.ethmac.interface.sram.ev.irq}") # FIXME HANDLEME
|
||||
|
||||
# for testing
|
||||
if (False):
|
||||
if (True):
|
||||
from nubus_master_tst import PingMaster
|
||||
self.submodules.pingmaster = PingMaster(nubus=self.nubus, platform=self.platform)
|
||||
self.bus.add_slave("pingmaster_slv", self.pingmaster.bus_slv, SoCRegion(origin=self.mem_map.get("pingmaster", None), size=0x010, cached=False))
|
||||
self.bus.add_master(name="pingmaster_mst", master=self.pingmaster.bus_mst)
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description="NuBusFPGA")
|
||||
parser = argparse.ArgumentParser(description="SbusFPGA")
|
||||
parser.add_argument("--build", action="store_true", help="Build bitstream")
|
||||
parser.add_argument("--variant", default="ztex2.13a", help="ZTex board variant (default ztex2.13a)")
|
||||
parser.add_argument("--version", default="V1.0", help="NuBusFPGA board version (default V1.0)")
|
||||
parser.add_argument("--sys-clk-freq", default=100e6, help="NuBusFPGA system clock (default 100e6 = 100 MHz)")
|
||||
parser.add_argument("--goblin", action="store_true", help="add a goblin framebuffer")
|
||||
parser.add_argument("--hdmi", action="store_true", help="The framebuffer uses HDMI (default to VGA, required for V1.2)")
|
||||
parser.add_argument("--hdmi", action="store_true", help="The framebuffer uses HDMI (default to VGA)")
|
||||
parser.add_argument("--goblin-res", default="640x480@60Hz", help="Specify the goblin resolution")
|
||||
parser.add_argument("--ethernet", action="store_true", help="Add Ethernet (V1.2 w/ custom PMod only)")
|
||||
builder_args(parser)
|
||||
vivado_build_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
if (args.ethernet and (args.version == "V1.0")):
|
||||
print(" ***** ERROR ***** : Ethernet not supported on V1.0\n");
|
||||
assert(False)
|
||||
|
||||
if ((not args.hdmi) and (args.version == "V1.2")):
|
||||
print(" ***** ERROR ***** : VGA not supported on V1.2\n");
|
||||
assert(False)
|
||||
|
||||
soc = NuBusFPGA(**soc_core_argdict(args),
|
||||
variant=args.variant,
|
||||
@ -534,8 +502,7 @@ def main():
|
||||
sys_clk_freq=int(float(args.sys_clk_freq)),
|
||||
goblin=args.goblin,
|
||||
hdmi=args.hdmi,
|
||||
goblin_res=args.goblin_res,
|
||||
ethernet=args.ethernet)
|
||||
goblin_res=args.goblin_res)
|
||||
|
||||
version_for_filename = args.version.replace(".", "_")
|
||||
|
||||
|
@ -104,8 +104,8 @@ _nubus_io_v1_2 = [
|
||||
## extra 54 MHz clock reference for bank 34
|
||||
("clk54", 0, Pins("R3"), IOStandard("LVCMOS33")),
|
||||
## leds on the NuBus board
|
||||
("user_led", 0, Pins("V9"), IOStandard("lvcmos33")), #LED0
|
||||
("user_led", 1, Pins("U9"), IOStandard("lvcmos33")), #LED1; both are overlapping with serial TX/RX
|
||||
("user_led", 0, Pins("U9"), IOStandard("lvcmos33")), #LED0
|
||||
("user_led", 1, Pins("V9"), IOStandard("lvcmos33")), #LED1; both are overlapping with serial TX/RX
|
||||
## serial header for console
|
||||
("serial", 0,
|
||||
Subsignal("tx", Pins("V9")), # FIXME: might be the other way round
|
||||
|
Loading…
Reference in New Issue
Block a user