NuBusFPGA/nubus-to-ztex/NuBus/74LVC126AD_118.lib
2021-12-21 08:26:30 +01:00

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EESchema-LIBRARY Version 2.3
#encoding utf-8
#(c) SnapEDA 2016 (snapeda.com)
#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
#
# 74LVC126AD,118
#
DEF 74LVC126AD,118 U 0 40 Y Y 1 L N
F0 "U" -212 804 50 H V L BNN
F1 "74LVC126AD,118" -184 -1082 50 H V L BNN
F2 "SOIC127P600X175-14N" 0 0 50 H I L BNN
F3 "NXP" 0 0 50 H I L BNN
F4 "1631665" 0 0 50 H I L BNN
F5 "74LVC126AD,118" 0 0 50 H I L BNN
F6 "03P2781" 0 0 50 H I L BNN
F7 "SOIC-14" 0 0 50 H I L BNN
DRAW
P 2 0 0 16 -500 700 -500 -900 N
P 2 0 0 16 -500 -900 500 -900 N
P 2 0 0 16 500 -900 500 700 N
P 2 0 0 16 500 700 -500 700 N
X VCC 14 -700 500 200 R 40 40 0 0 W
X 1OE 1 -700 300 200 R 40 40 0 0 I
X 2OE 4 -700 200 200 R 40 40 0 0 I
X 3OE 10 -700 100 200 R 40 40 0 0 I
X 4OE 13 -700 0 200 R 40 40 0 0 I
X 1A 2 -700 -200 200 R 40 40 0 0 I
X 2A 5 -700 -300 200 R 40 40 0 0 I
X 3A 9 -700 -400 200 R 40 40 0 0 I
X 4A 12 -700 -500 200 R 40 40 0 0 I
X GND 7 -700 -700 200 R 40 40 0 0 P
X 1Y 3 700 -200 200 L 40 40 0 0 O
X 2Y 6 700 -300 200 L 40 40 0 0 O
X 3Y 8 700 -400 200 L 40 40 0 0 O
X 4Y 11 700 -500 200 L 40 40 0 0 O
ENDDRAW
ENDDEF
#
# End Library