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ConsoleTest
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update to first tested version
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2022-04-17 11:25:48 +02:00 |
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DeclROM
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LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650
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2022-06-24 23:37:18 +02:00 |
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NuBusFPGAInit
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draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel
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2022-06-06 23:36:43 +02:00 |
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.gitignore
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LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650
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2022-06-24 23:37:18 +02:00 |
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74fct245.v
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push to github
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2021-12-21 08:26:30 +01:00 |
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blit.c
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LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650
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2022-06-24 23:37:18 +02:00 |
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blit.lds
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Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag)
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2022-05-15 14:43:15 +02:00 |
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blit.sh
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LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650
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2022-06-24 23:37:18 +02:00 |
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CG6.scala
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commit current Vex config
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2022-06-05 18:04:00 +02:00 |
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DepVideoEqu.a
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update to first tested version
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2022-04-17 11:25:48 +02:00 |
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do
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DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus
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2022-06-04 09:53:09 +02:00 |
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fb_dma.py
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update to first tested version
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2022-04-17 11:25:48 +02:00 |
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fb_video.py
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update to first tested version
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2022-04-17 11:25:48 +02:00 |
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GenGoblinAccel.scala
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LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650
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2022-06-24 23:37:18 +02:00 |
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goblin_accel.py
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Move Vex to a 128-bit Wishbone, and add a bypass to access a dedicated memory port with a 128-bits datapath. Speeds up scrolling quite nicely.
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2022-06-05 18:03:23 +02:00 |
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goblin_fb.py
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Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag)
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2022-05-15 14:43:15 +02:00 |
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ldsdsupport.h
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LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650
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2022-06-24 23:37:18 +02:00 |
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MakeFile
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push to github
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2021-12-21 08:26:30 +01:00 |
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nubus_arbiter.v
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update to first tested version
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2022-04-17 11:25:48 +02:00 |
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nubus_cpld.ucf
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update to first tested version
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2022-04-17 11:25:48 +02:00 |
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nubus_cpld.v
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DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus
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2022-06-04 09:53:09 +02:00 |
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nubus_cpu_wb.py
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Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag)
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2022-05-15 14:43:15 +02:00 |
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nubus_fpga_V1_0_timings.xdc
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update to first tested version
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2022-04-17 11:25:48 +02:00 |
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nubus_full_sampling.py
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in _sampling, map whole SDRAm in superslot and use the first 248 Mib as a RAM disk with driver in the DeclRom
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2022-06-07 23:05:08 +02:00 |
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nubus_full.py
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draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel
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2022-06-06 23:36:43 +02:00 |
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nubus_master_tst.py
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stat module
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2022-06-04 18:56:41 +02:00 |
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nubus_mem_wb.py
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buffers (fifo) write from NuBus to Wishbone, to improve write BW
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2022-05-30 13:15:20 +02:00 |
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nubus_memfifo_wb.py
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pingmaster sort-of-work
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2022-05-30 19:06:33 +02:00 |
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nubus_sampling.v
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DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus
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2022-06-04 09:53:09 +02:00 |
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nubus_stat.py
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stat module
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2022-06-04 18:56:41 +02:00 |
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nubus_to_fpga_export.py
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more updates
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2022-01-29 11:03:47 +01:00 |
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nubus_to_fpga_soc.py
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draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel
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2022-06-06 23:36:43 +02:00 |
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nubus-to-ztex-io-signal.xdc
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push to github
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2021-12-21 08:26:30 +01:00 |
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nubus-to-ztex-pin-signal.xdc
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push to github
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2021-12-21 08:26:30 +01:00 |
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nubus.py
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DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus
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2022-06-04 09:53:09 +02:00 |
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nubus.v
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DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus
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2022-06-04 09:53:09 +02:00 |
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NuBusFPGADrvr.a
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update to first tested version
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2022-04-17 11:25:48 +02:00 |
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NuBusFPGAPrimaryInit.a
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update to first tested version
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2022-04-17 11:25:48 +02:00 |
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NuBusFPGASecondaryInit.a
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update to first tested version
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2022-04-17 11:25:48 +02:00 |
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post_process_timings.sh
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update to first tested version
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2022-04-17 11:25:48 +02:00 |
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rom.a
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update to first tested version
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2022-04-17 11:25:48 +02:00 |
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sdram_init.py
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Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag)
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2022-05-15 14:43:15 +02:00 |
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slave_tb.sv
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draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel
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2022-06-06 23:36:43 +02:00 |
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sn74lvt125.v
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more updates
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2022-01-29 11:03:47 +01:00 |
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VexRiscv_FbAccel.v
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LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650
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2022-06-24 23:37:18 +02:00 |
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ztex213_nubus.py
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update to first tested version
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2022-04-17 11:25:48 +02:00 |
