mirror of
https://github.com/rdolbeau/NuBusFPGA.git
synced 2024-12-23 01:30:32 +00:00
140 lines
5.0 KiB
Python
140 lines
5.0 KiB
Python
#!/usr/bin/env python3
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from migen import *
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from wb_master import *
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from wb_master import _WRITE_CMD, _WAIT_CMD, _DONE_CMD
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dfii_control_sel = 0x01
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dfii_control_cke = 0x02
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dfii_control_odt = 0x04
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dfii_control_reset_n = 0x08
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dfii_command_cs = 0x01
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dfii_command_we = 0x02
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dfii_command_cas = 0x04
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dfii_command_ras = 0x08
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dfii_command_wrdata = 0x10
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dfii_command_rddata = 0x20
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# /!\ keep up to date with csr /!\
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sdram_dfii_base = 0xf0a01800
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sdram_dfii_control = sdram_dfii_base + 0x000
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sdram_dfii_pi0_command = sdram_dfii_base + 0x004
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sdram_dfii_pi0_command_issue = sdram_dfii_base + 0x008
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sdram_dfii_pi0_address = sdram_dfii_base + 0x00c
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sdram_dfii_pi0_baddress = sdram_dfii_base + 0x010
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# /!\ keep up to date with csr /!\
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ddrphy_base = 0xf0a00000
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ddrphy_rst = ddrphy_base + 0x000
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ddrphy_dly_sel = ddrphy_base + 0x010
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ddrphy_rdly_dq_rst = ddrphy_base + 0x014
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ddrphy_rdly_dq_inc = ddrphy_base + 0x018
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ddrphy_rdly_dq_bitslip_rst = ddrphy_base + 0x01c
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ddrphy_rdly_dq_bitslip = ddrphy_base + 0x020
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ddrphy_wdly_dq_bitslip_rst = ddrphy_base + 0x024
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ddrphy_wdly_dq_bitslip = ddrphy_base + 0x028
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ddrphy_rdphase = ddrphy_base + 0x02c
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ddrphy_wdphase = ddrphy_base + 0x030
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def period_to_cycles(sys_clk_freq, period):
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return int(period*sys_clk_freq)
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def ddr3_init_instructions(sys_clk_freq):
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return [
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_WAIT_CMD | period_to_cycles(sys_clk_freq, 0.001),
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# phase
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_WRITE_CMD, ddrphy_rdphase, 2,
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_WRITE_CMD, ddrphy_wdphase, 3,
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# software control
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_WRITE_CMD, sdram_dfii_control, dfii_control_reset_n | dfii_control_odt | dfii_control_cke,
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# reset
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_WRITE_CMD, ddrphy_rst, 1,
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_WAIT_CMD | period_to_cycles(sys_clk_freq, 0.001),
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_WRITE_CMD, ddrphy_rst, 0,
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_WAIT_CMD | period_to_cycles(sys_clk_freq, 0.001),
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# release reset
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_WRITE_CMD, sdram_dfii_pi0_address, 0x0,
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_WRITE_CMD, sdram_dfii_pi0_baddress, 0,
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_WRITE_CMD, sdram_dfii_control, dfii_control_odt|dfii_control_reset_n,
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_WAIT_CMD | period_to_cycles(sys_clk_freq, 0.005),
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# bring cke high
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_WRITE_CMD, sdram_dfii_pi0_address, 0x0,
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_WRITE_CMD, sdram_dfii_pi0_baddress, 0,
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_WRITE_CMD, sdram_dfii_control, dfii_control_cke|dfii_control_odt|dfii_control_reset_n,
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_WAIT_CMD | period_to_cycles(sys_clk_freq, 0.001),
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# load mode register 2, CWL = 5
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_WRITE_CMD, sdram_dfii_pi0_address, 0x200,
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_WRITE_CMD, sdram_dfii_pi0_baddress, 2,
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_WRITE_CMD, sdram_dfii_pi0_command, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs,
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_WRITE_CMD, sdram_dfii_pi0_command_issue, 1,
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# load mode register 3
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_WRITE_CMD, sdram_dfii_pi0_address, 0x0,
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_WRITE_CMD, sdram_dfii_pi0_baddress, 3,
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_WRITE_CMD, sdram_dfii_pi0_command, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs,
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_WRITE_CMD, sdram_dfii_pi0_command_issue, 1,
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# load mode register 1
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_WRITE_CMD, sdram_dfii_pi0_address, 0x6,
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_WRITE_CMD, sdram_dfii_pi0_baddress, 1,
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_WRITE_CMD, sdram_dfii_pi0_command, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs,
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_WRITE_CMD, sdram_dfii_pi0_command_issue, 1,
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# load mode register 0, CL=6, BL=8
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_WRITE_CMD, sdram_dfii_pi0_address, 0x920,
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_WRITE_CMD, sdram_dfii_pi0_baddress, 0,
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_WRITE_CMD, sdram_dfii_pi0_command, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs,
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_WRITE_CMD, sdram_dfii_pi0_command_issue, 1,
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_WAIT_CMD | period_to_cycles(sys_clk_freq, 0.0002),
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# zq calibration
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_WRITE_CMD, sdram_dfii_pi0_address, 0x400,
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_WRITE_CMD, sdram_dfii_pi0_baddress, 0,
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_WRITE_CMD, sdram_dfii_pi0_command, dfii_command_we|dfii_command_cs,
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_WRITE_CMD, sdram_dfii_pi0_command_issue, 1,
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_WAIT_CMD | period_to_cycles(sys_clk_freq, 0.0002),
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# hardware control
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_WRITE_CMD, sdram_dfii_control, dfii_control_sel,
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]
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def ddr3_config_instructions(bitslip, delay):
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r = []
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for module in range(2):
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r += [_WRITE_CMD, ddrphy_dly_sel, 1<<module ]
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r += [_WRITE_CMD, ddrphy_wdly_dq_bitslip_rst, 1<<module ]
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r += [_WRITE_CMD, ddrphy_dly_sel, 0 ]
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for module in range(2):
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r += [_WRITE_CMD, ddrphy_dly_sel, 1<<module ]
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r += [_WRITE_CMD, ddrphy_rdly_dq_bitslip_rst, 1]
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for i in range(bitslip):
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r += [_WRITE_CMD, ddrphy_rdly_dq_bitslip, 1]
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r += [_WRITE_CMD, ddrphy_rdly_dq_rst, 1]
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for i in range(delay):
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r += [_WRITE_CMD, ddrphy_rdly_dq_inc, 1]
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r += [_WRITE_CMD, ddrphy_dly_sel, 0 ]
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return r
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class DDR3Init(WishboneMaster):
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def __init__(self, sys_clk_freq, bitslip, delay):
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WishboneMaster.__init__(self,
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ddr3_init_instructions(sys_clk_freq) +
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ddr3_config_instructions(bitslip, delay) +
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[_DONE_CMD])
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class DDR3FBInit(WishboneMaster):
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def __init__(self, sys_clk_freq, bitslip, delay):
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WishboneMaster.__init__(self,
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ddr3_init_instructions(sys_clk_freq) +
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ddr3_config_instructions(bitslip, delay) +
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[_DONE_CMD])
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