NuBusFPGA/nubus-to-ztex/TPD12S016PWR.lib
2021-12-21 08:26:30 +01:00

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EESchema-LIBRARY Version 2.3
#encoding utf-8
#(c) SnapEDA 2016 (snapeda.com)
#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
#
# TPD12S016PWR
#
DEF TPD12S016PWR U 0 40 Y Y 1 L N
F0 "U" -500 1239 50 H V L BNN
F1 "TPD12S016PWR" -500 -1300 50 H V L BNN
F2 "SOP65P640X120-24N" 0 0 50 H I L BNN
F3 "" 0 0 50 H I L BNN
F4 "1.2 mm" 0 0 50 H I L BNN "MAXIMUM_PACKAGE_HEIGHT"
F5 "Texas Instruments" 0 0 50 H I L BNN "MANUFACTURER"
F6 "F" 0 0 50 H I L BNN "PARTREV"
F7 "IPC 7351B" 0 0 50 H I L BNN "STANDARD"
DRAW
S -500 -1200 500 1200 0 0 10 f
X CLK- 15 700 500 200 L 40 40 0 0 B C
X CLK+ 16 700 600 200 L 40 40 0 0 B C
X CEC_A 1 -700 -400 200 R 40 40 0 0 B
X CEC_B 7 700 -400 200 L 40 40 0 0 B
X CT_HPD 12 -700 600 200 R 40 40 0 0 I
X HPD_A 4 -700 -300 200 R 40 40 0 0 O
X HPD_B 10 700 -300 200 L 40 40 0 0 I
X LS_OE 5 -700 400 200 R 40 40 0 0 I
X SCL_A 2 -700 -500 200 R 40 40 0 0 B
X SCL_B 8 700 -500 200 L 40 40 0 0 B
X SDA_A 3 -700 -600 200 R 40 40 0 0 B
X SDA_B 9 700 -600 200 L 40 40 0 0 B
X VCC5V 11 -700 800 200 R 40 40 0 0 I
X VCCA 24 -700 1100 200 R 40 40 0 0 W
X 5V_OUT 13 700 800 200 L 40 40 0 0 O
X GND_6 6 700 -900 200 L 40 40 0 0 W
X D1+ 21 700 200 200 L 40 40 0 0 B
X D1- 20 700 100 200 L 40 40 0 0 B
X GND_14 14 700 -1000 200 L 40 40 0 0 W
X GND_19 19 700 -1100 200 L 40 40 0 0 W
X D2+ 23 700 0 200 L 40 40 0 0 B
X D2- 22 700 -100 200 L 40 40 0 0 B
X D0+ 18 700 400 200 L 40 40 0 0 B
X D0- 17 700 300 200 L 40 40 0 0 B
ENDDRAW
ENDDEF
#
# End Library